WO2002093574A1 - Appareil d'enregistrement et de reproduction d'informations - Google Patents

Appareil d'enregistrement et de reproduction d'informations Download PDF

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Publication number
WO2002093574A1
WO2002093574A1 PCT/JP2002/004518 JP0204518W WO02093574A1 WO 2002093574 A1 WO2002093574 A1 WO 2002093574A1 JP 0204518 W JP0204518 W JP 0204518W WO 02093574 A1 WO02093574 A1 WO 02093574A1
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WIPO (PCT)
Prior art keywords
edge
timing
window pulse
detected
signal
Prior art date
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PCT/JP2002/004518
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English (en)
Japanese (ja)
Inventor
Tadashi Nakata
Shigeru Saito
Original Assignee
Sony Corporation
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Publication of WO2002093574A1 publication Critical patent/WO2002093574A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
    • G11B7/004—Recording, reproducing or erasing methods; Read, write or erase circuits therefor
    • G11B7/005—Reproducing

Definitions

  • the present invention relates to an information recording / reproducing apparatus, and in particular, to an information recording / reproducing apparatus capable of stably supplying a sample signal used for tracking a disc to a PLL block when recording or reproducing the information on a disc-shaped recording medium.
  • the present invention relates to a recording / reproducing device. Background art
  • MDs Mini Discs
  • an address area serving as a seam between data and data has a rotational fluctuation or an unevenness caused by rotation of the disk-shaped recording medium. Many children are not long enough to absorb the reading error caused by the core.
  • the address areas 11a to 11j define the land area 12 as a data area and the group.
  • the area 13 is configured to be partitioned in the rotation direction.
  • the drive area 13 is formed as a meandering groove on the disk 1, and the portion left uncut as the meandering groove forms the land area 12.
  • data can be recorded only in the land area 12 or only in the group area 13 or both.
  • discontinuously recorded data can be restored as continuous data by connecting the data so that the beginning and end of the data to be connected match.
  • the buffer area is widened, the data redundancy will be increased.Therefore, near Owl, the buffer area is reduced in order to increase the density of data.
  • the permissible deviation of the write data in the land area 12 and the group area 13 is becoming very small. Therefore, in a configuration in which data is read simply by synchronizing with a fixed clock, a reading error cannot be sufficiently absorbed.
  • the address areas 11a to 11j are simply referred to as the address areas 11 when it is not necessary to individually distinguish them. The same applies to other parts.
  • a clock signal used for the recording or reproducing process is generated from a unique built-in clock generator built in the device. Instead of using a clock signal, a clock signal is generated and used based on the rotation information of disk 1.
  • the rotation information of the disc 1 is based on the intensity of the reflected laser beam for tracking, which irradiates the wobble (tracking groove for tracking) 14 formed along the land area 12 or the group area 13. Is obtained by detecting a change in More specifically, as shown in the upper part of FIG. 2, the reflected light from the fiber 14 is read with its light intensity changed in accordance with the meandering of the fiber 14. When this read signal is binarized by a predetermined value, a sample signal as shown in the lower part of FIG. 2 is obtained.
  • the information recording / reproducing apparatus acquires the rotation information (rotation speed) of the disk 1 by sequentially measuring the detection timing (cycle) of the edge of this double signal, and further acquires the acquired information. By outputting the wobble signal to the PLL (Phase Locked Loop) circuit, the PLL circuitry required for various processes is generated.
  • PLL Phase Locked Loop
  • the information recording / reproducing device predicts the timing of the next edge to be detected from the timing of the detected edge (the interval between edges is calculated from the clock generated by the PLL circuit up to that time). It can be predicted), and a window pulse with a predetermined pulse width centered on the predicted timing is generated, and during the period when the window pulse is high (when the pulse is formed high)
  • the signal detected in step (2) is regarded as an edge, and the process of predicting the position of the next edge from the detected edge and generating a window pulse is repeated.
  • the deviation of the timing (interval) at which the edge is detected cannot be corrected within the time corresponding to the pulse width of the window pulse, and even if a signal different from the edge occurs, Unless it occurs within the time corresponding to the pulse width of the window pulse, it is not detected as an edge, so that erroneous detection is suppressed.
  • the time from the time t1 to the time t4 as shown in FIG. 3A is detected by the respective window pulses at t 21 to t 22 and at times t 23 to t 24.
  • the interval A between times t1 to t3 is usually the interval at which edges are detected. However, for example, as shown in FIG.
  • the next window pulse is generated at equal intervals (time A).
  • the edge detection timing is delayed only once at time t, 5, and the edge cannot be detected in the window pulse after time t, 27 to t, 28.
  • the light intensity signal (wobble signal) of the reflected light from 14 has been detected correctly, it is not possible to accurately supply the wobble signal to the PLL circuit.
  • a method of increasing the pulse width of the window pulse is conceivable.However, as the pulse width increases, erroneous detection increases in proportion to the pulse width. There was a problem that signals could not be supplied. Disclosure of the invention
  • the present invention has been made in view of such a situation, and when an edge of a double signal cannot be detected in a window pulse, a pulse (hereinafter, referred to as a sub-window pulse) is generated at a timing different from the window pulse. After generating the edge and detecting the edge within the sub-window pulse, the window pulse is generated again based on the timing of the detected edge, so that a stable wobble signal can be supplied to the PLL circuit. This enables accurate and stable recording or reproduction of data on a disk-shaped recording medium.
  • a pulse hereinafter, referred to as a sub-window pulse
  • An information recording / reproducing apparatus is an information recording and reproducing Signal as a binary signal, an edge detecting means for detecting the edge, a reference signal generating means for generating a reference signal based on a timing at which the edge is detected, and a wobble signal based on the reference signal. Comparing the timing of the window pulse and the edge with the window pulse generating means for generating a window pulse at a timing near the time at which the next edge is expected to be detected based on the reference signal; First comparing means for outputting a signal indicating the timing at which the edge is detected to the reference signal generating means when the edge detection timing is within the window pulse; and a window when the edge is not within the window path.
  • a sub-window pulse generating means for generating a sub-window pulse different from the pulse;
  • a second comparing unit that compares the timing of the edge of the subwindow with the timing of the edge of the subwindow and outputs a signal indicating the timing of detecting the edge to the reference signal generating unit when the timing of detecting the edge is within the subwindow pulse. It is characterized by
  • the sub-window pulse may include an opening pulse.
  • An information recording / reproducing method comprises the steps of: reading an opponent used for tracking on a recording medium as a binary signal; detecting an edge of the binarized signal; and a timing at which the edge is detected.
  • the window pulse generation step of generating a window pulse by the timing and the timing of the window pulse and the edge are compared. When the edge detection timing is within the window pulse, the etching required in the reference signal generation step is performed.
  • the program of the recording medium of the present invention reads the sample used for tracking on the recording medium as a binary signal and controls the edge detection based on the edge detection timing.
  • a reference signal generation control step for controlling generation of a reference signal, a sample signal generation control step for controlling generation of a sample signal based on the reference signal, and a next edge is detected based on the reference signal.
  • the window pulse generation step which controls the generation of the window pulse at the timing near the predicted time, is compared with the window pulse and the edge timing. When the edge detection timing is within the window pulse, the reference signal generation control step is performed.
  • a first comparison control step for controlling the force a subwindow pulse generation control step for controlling generation of a subwindow pulse different from the window pulse when the edge is not within the window pulse; and comparing the timing of the subwindow pulse with the edge;
  • the program according to the present invention reads a pebble used for tracking on a recording medium as a binarized signal, and generates a reference signal based on an edge detection control step for controlling the detection of the edge and a timing at which the edge is detected.
  • a reference signal generation control step for controlling the generation of a wobble signal based on the reference signal; and a near signal generation control step for controlling the generation of a wobble signal based on the reference signal.
  • the window pulse generation step which controls the generation of the window pulse by the timing, compares the window pulse with the edge timing.
  • the reference signal generation control A first comparison control step for controlling an output of a signal indicating a timing at which an edge required in the step processing is detected; and generating a sub-window pulse different from the window pulse when the edge is not within the window pulse.
  • the sub-window pulse generation control step to be controlled is compared with the sub-window pulse and the edge timing.
  • a pebble used for tracking on a recording medium is read as a binarized signal, its edge is detected, and the timing at which an edge is detected is detected.
  • a reference signal is generated based on the reference signal
  • a wobble signal is generated based on the reference signal
  • a window pulse is generated based on the reference signal at a timing close to when the next edge is expected to be detected.
  • the timing of the window pulse is compared with the timing of the edge. When the timing at which the edge is detected is within the window pulse, a signal indicating the timing at which the edge required for generating the reference signal is detected is output.
  • a subwindow pulse different from the window pulse is generated, and Are compared the timing of Ndouparusu edge, data Imingu detected edge when it is within the sub-window pulse, a signal indicating the timing at which the edge is detected that is required for generation of the reference signal is output.
  • FIG. 1 is a diagram showing a configuration of a disk-shaped recording medium.
  • FIG. 2 is a timing chart for explaining the binarization of the pebble signal.
  • FIG. 3A is a timing chart showing the timing of the cobbled signal.
  • FIG. 3B is a timing chart showing the timing of the main window pulse.
  • FIG. 3C is a timing chart showing the timing of edge detection.
  • FIG. 4 is a block diagram showing a configuration of the digital information recording / reproducing apparatus.
  • FIG. 5 is a block diagram showing a configuration of the timing generation circuit.
  • FIG. 6 is a flowchart illustrating main wobble detection processing.
  • FIG. 7 is a flowchart illustrating main wobble detection processing.
  • FIG. 8 is a timing chart illustrating a main wobble detection process and a sub wobble detection process.
  • FIG. 8A is a timing chart for explaining the main and sub-population detection processes.
  • FIG. 8B is a timing chart illustrating the main-wobble detection process and the sub-population detection process.
  • FIG. 8C is a timing chart illustrating the main sample detection process and the sub sample detection process.
  • FIG. 8D is a timing chart for explaining the main wobble detection process and the sub wobble detection process.
  • FIG. 8E is a timing chart for explaining the main wobble detection process and the sub wobble detection process.
  • FIG. 9 is a flowchart illustrating the sub-wobble detection process.
  • FIG. 10 is a flowchart illustrating the sub-population detection processing.
  • FIG. 11 is a diagram illustrating a medium. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 4 is a block diagram showing a configuration of an embodiment of a digital video camera according to the present invention.
  • the video encoder 31 compresses and encodes a video signal of an image captured by a video camera including an image sensor such as a CCD (Charge Coupled Device) and outputs the video signal to the file generator 35 as a video elementary stream. I do.
  • the audio encoder 32 is a microphone (not shown)
  • An audio signal supplied from an audio generation unit such as a lophone is compression-encoded and output to the file generator 35 as an audio elementary list V-room.
  • the compression encoding method of the video signal and the audio signal input to the video encoder 31 and the audio encoder 32 is, for example, MPEG (Moving Picture Experts).
  • the file generator 35 is input from the video encoder 31 and the audio encoder 32.
  • the video elementary stream and audio elementary stream input are played back by software without using special hardware.
  • the file is converted into a file structure that can be used and output to the memory controller 38 as a moving image file corresponding to the software.
  • the software mentioned here may be, for example, QuickTime (trademark) or other software.
  • the memory 37 sequentially stores moving image files input from the file generator 35 via the memory controller 38.
  • the memory controller 38 is controlled by the system control microcomputer 39, and when a predetermined write command is input, reads the moving image file stored in the memory 37, and outputs the error correction code / decoder 41 Output to
  • the system control microcomputer 39 has a CPU (Central Processing
  • RAM Random Access Memory
  • ROM Read Only Memory
  • the CPU appropriately reads the program stored in the ROM into the RAM and executes predetermined processing. It controls the decoder 36 and the memory controller 38, and exchanges various data with the drive control microphone port computer 39.
  • the error correction code decoder 41 is controlled by the drive control microcomputer 42, writes a moving image file into the memory 40, generates interleave and error correction code redundant data, and adds redundant data.
  • the read data is read from the memory 40 and supplied to the data modulator / demodulator 43.
  • the drive control microcomputer 4 2 CPU, RAM, and is composed of such as ROM, Nde properly read the program the CPU is stored in the ROM in the RAM and executes the predetermined processing, the error correction code Z decoder 4 1, Controls the servo circuit 47 and the timing generation circuit 46.
  • the data modulator / demodulator 43 facilitates clock extraction during reproduction based on the clock input from the timing generation circuit 46 when recording digital data on the disc 1, and causes problems such as intersymbol interference. It modulates the data of the moving image file so that it does not exist and supplies it to the magnetic field modulation driver 44, and at the same time, outputs a signal for driving the optical block 47.
  • the magnetic field modulation driver 44 applies a magnetic field to the disk 1 by driving the magnetic field head 49 according to the input signal.
  • the optical block 47 irradiates the recording laser beam to the disc 1 and also irradiates the tracking laser beam.
  • the servo circuit 45 is controlled by the drive control microcomputer 42, controls the position of the optical block 47 based on the clock signal supplied from the timing generation circuit 46, and rotates the motor 48. Control.
  • the rotation speed of the motor 48 is controlled in various modes such as a CLV (constant linear velocity) mode, a CAV (constant angular velocity) mode, or a ZCAV (constant linear velocity in zone) mode.
  • the timing generation circuit 46 is controlled by the drive control microcomputer 42, generates a clock signal based on the tracking signal (a wobble signal generated by the wobble 14) supplied from the optical block 47, and generates a clock signal. It is supplied to the circuit 45 and the data modem 43. The details of the timing generation circuit 46 will be described later with reference to FIG.
  • the optical block 47 is controlled by the servo circuit 45 based on the clock signal from the timing generation circuit 46, reads data recorded on the disk 1, and outputs the data to the data modem 43. I do.
  • the data modulator / demodulator 43 demodulates the data input from the optical block 47 and performs error correction coding / decoding as a moving image file. Output to container 4 1
  • the error correction code / decoder 41 writes the input moving image file into the memory 40 once, executes deinterleaving processing and error correction processing, and supplies it to the memory controller 38.
  • the memory controller 38 writes the input moving image file into the memory 37, reads the data written into the memory 37 based on a command from the system control microcomputer 39, and outputs the data to the file decoder 3. Output to 6.
  • the file decoder 36 is controlled by the system control microcomputer 39, decomposes the moving image data into a video elementary stream and an audio elementary stream, and converts the video elementary stream to the video decoder 33, and outputs the video elementary stream to the video decoder 33. And outputs the elementary streams to the audio decoders 34, respectively.
  • the video decoder 33 and the audio decoder 34 decode the compression code and output a video signal and an audio signal, respectively.
  • the video encoder 31 is image-compressed by a camera including an image sensor such as a CCD (Charge Coupled Device), compression-encodes an input video signal, and outputs it as a video element and an elementary stream to the file generator 35.
  • the audio encoder 32 compresses and encodes an audio signal supplied from an audio generation unit such as a microphone (not shown), and outputs it to the file generator 35 as an audio elementary stream.
  • the file generator 35 has a file structure so that the video elementary stream and the audio elementary stream input from the video encoder 31 and the audio encoder 32 can be reproduced in synchronization with a moving image or the like by software. Are converted, multiplexed, and output to the memory controller 38 as a moving image file corresponding to the software.
  • the memory controller 38 sequentially writes the input moving image files into the memory 37, and when a data write command is issued from the system control microcomputer 39, the moving image files written in the memory 37 are sequentially read. Memory 3 7 And outputs it to the error correction code / decoder 41.
  • the system control microcomputer 39 controls the transfer speed of the memory controller 38 to the error correction code / decoder 41 to about 1 to 2 of the write speed to the disk 1. That is, the system control microcomputer 39 continuously writes the moving image file while monitoring the moving image data written in the memory 37 so as not to overflow or underflow. In contrast to this, reading of the moving image file from the memory 37 is controlled to be performed intermittently.
  • the error correction code Z decoder 41 temporarily writes the moving image file input from the memory controller 38 into the memory 40, generates redundant data of the interleave and error correction code, and stores the data to which the redundant data has been added. Read from 40 and supply to data modem 43. '
  • the data modulator / demodulator 43 modulates the data of the moving image file based on the clock signal input from the timing generation circuit 46 and supplies the data to the magnetic field modulation driver 44 and at the same time, drives the optical block 47 Output a signal for
  • the magnetic field modulation driver 44 applies a magnetic field to the disk 1 by driving the magnetic field head 49 according to the input signal.
  • the optical block 47 irradiates the recording laser beam to the disc 1 and also irradiates the tracking laser beam.
  • the servo circuit 45 controls the position of the optical block 47 and the rotation speed of the motor 48 based on the clock supplied from the timing generation circuit 46. At this time, since the data read from the memory controller 38 is intermittently supplied, the recording operation on the disc 1 is performed not intermittently but intermittently. By the above processing, the optical block 47 and the magnetic field head 49 cooperate to write data on the disk 1.
  • the optical block 47 reads out the data recorded on the disc 1 based on the clock signal from the timing generation circuit 46 in response to a command from the servo circuit 45. Output to data modulator / demodulator 43. At this time, the timing generation circuit 46 generates a predetermined clock signal based on the sample signal according to a command from the drive control microcomputer 42, and outputs the clock signal to the data modem 43.
  • the data modulator / demodulator 43 demodulates the data input from the optical block 47 based on the clock signal, and outputs the data to the error correction code decoder 41 as a moving image file.
  • the error correction code / decoder 41 temporarily writes the input moving image file into the memory 40, executes the ding leave processing and the error correction processing, and supplies the processed data to the memory controller 38.
  • the memory controller 38 writes the input moving image file into the memory 37, reads the data written into the memory 37 based on a command from the system control microcomputer 39, and outputs the data to the file decoder 3. Output to 6.
  • the system control microcomputer 39 monitors the amount of data written to the memory 37 and the amount of data output from the memory 37 to the file decoder 36, and the memory 37 does not overflow or underflow. So that the memory controller 38 and the drive control microcomputer 42 are controlled.
  • the file decoder 36 decomposes the video elementary stream and the audio elementary stream multiplexed into the moving image data based on the command of the system control microcomputer 39, and video-decodes the video elementary stream.
  • the audio elementary stream is output to the audio decoder 34, respectively.
  • the video decoder 33 and the audio decoder 34 decode the compression codes, respectively, and do not display the video signal and the audio signal, respectively.
  • the display unit such as an LCD (Liquid Crystal Display) and the audio such as a speaker. Output to each output device. ,
  • the timing signal is read from the optical block 47 and read from the optical block 47 to the timing generation circuit 46 via the RF amplifier 61, the BPF 62, and the comparator 63.
  • the RF (Radio Frequency) amplifier 61 amplifies the analog wobble signal input from the optical block 47 to a level that can be processed by a subsequent device, and outputs the amplified signal to a BPF (Band Pass Filter) 62.
  • the BPF 62 extracts only signals within a predetermined frequency range required for processing from the signals input from the RF amplifier 61 and outputs the extracted signals to the comparator 63.
  • the comparator 63 binarizes the signal extracted from the BPF 62 with reference to a predetermined value, and outputs it as a digital signal to the edge detector 81 of the timing generation circuit 46. That is, the signal as shown in the upper part of FIG. 2 input from the BPF 62 is binarized, converted into a digital signal as shown in the lower part of FIG. 2, and output to the edge detector 81.
  • the edge detector 81 of the timing generation circuit 46 receives a rising edge portion or a falling edge portion (hereinafter, simply referred to as an edge portion) from the binarized sample signal input from the comparator 63. Is detected and output as an edge detection signal to the AND circuits 101 and 111 of the main combo interpolation section 82 and the sub-population interpolation section 83. That is, as shown in FIG. 3A, the edge detector 81 extracts an edge detection signal as shown in FIG. 3C from the signal input from the comparator 63, and outputs the edge detection signal as a main detection signal. 2, and output to the AND circuits 101 and 111 of the sub-wobble interpolation unit 83.
  • the main wobble interpolation unit 82 compares the edge detection signal input from the edge detector 81 with a main window pulse described later, and based on the edge detection signal when an edge is detected in the main window pulse. In addition, a wobble signal is supplied to the subsequent PLL block 87.
  • the sub-wobble interpolation unit 83 generates a sub-window pulse to search the edge detection timing when no edge is detected in the main window pulse in the main The detection timing is notified to the main sample interpolation unit 82, and the main sample interpolation unit 82 detects an edge again in the main window.
  • the AND circuit 101 of the main sample interpolation unit 82 is input from the edge detector 81
  • the detected edge detection signal is compared with the main window pulse input from the main window pulse generator 104, and when an edge is detected within the rising timing of the main window pulse, a predetermined
  • the counter value is output to terminal 102a of switch 102.
  • Switch 102 is controlled by controller 84 and is normally connected to terminal 102a.
  • the timing counter 103 receives a main window pulse generator 104, based on a predetermined counter value input from the AND circuit 101 or the AND circuit 111 via the switch 102. Also, a reference signal is output to the cobble signal generator 105. More specifically, the timing counter 103 counts the count value at fixed time intervals based on PLLCK (PLL clock input from the subsequent PLL block 87). A predetermined reference signal is output at the timing when the counting of the count value is completed. That is, for example, when 10 is input as a count value, the timing counter 103 has passed 10 clocks of PLL clock from the timing at which the count value was input. Later, a reference signal is generated.
  • PLLCK PLL clock input from the subsequent PLL block 87
  • the same counter value is always input from the AND circuit 101, as a result, a reference signal is generated at a certain timing from the edge detection timing, and the main window pulse generator 104 and the wobbled signal It will be output to generator 105. Since the timing at which an edge is detected by the edge detector 81 depends on the rotation speed of the disk 1, the reference signal output from the timing counter 103 is not necessarily constant. The timing is based on the rotation speed of the disk 1.
  • the timing counter 103 will output the last value from the AND circuit 101 or 111 based on the PLLCK.
  • a reference signal is generated at predetermined intervals from the input timing and output to the main window pulse generator 104 and the sample signal generator 105.
  • the main window pulse generator 104 is controlled by the controller 84. Then, based on the reference signal input from the timing counter 103, a main window pulse having a predetermined pulse width is generated around the timing at which the edge is predicted to be detected, and an AND circuit is generated. Output to 101.
  • the double signal generator 105 is controlled by the controller 84, generates a stable double signal based on the reference signal input from the timing counter 103, and outputs it to the switch 86. . That is, the timing at which the vobble signal read by the optical block 47 input to the edge detector 81 is not read due to an address area, a scratch, or the like may occur as described above. In 5, in the optical block 47 (in the edge detector 81), an interpolation process is performed based on the reference signal input from the timing counter 103, even if no sample signal (edge) is detected. Outputs a stable signal to the subsequent PLL block 87.
  • the switch 86 is controlled by the controller 84, and the signal input from either the cobbled signal generator 105 or the 1 / M divider 85 is sent to the phase comparator 91 of the PLL block 87. Output. More particularly, the Woburu signal generator 1 0 5, about 1 0 0 k H z is a signal of a frequency of, until the rotation of the disk 1 is stabilized, 1 ⁇ 0 k H Z with predetermined accuracy Unable to generate a nearby wobble signal, a signal from the MCK (Master Clock) consisting of a crystal oscillator is supplied during normal stable rotation until the disk rotation stabilizes.
  • MCK Master Clock
  • the controller 84 controls the switch 86, connects to the terminal 86a until the rotation is stabilized, and switches to the terminal 86b after the rotation is stabilized. In this switching process, the controller 84 samples the wobble signal output from the wobble signal generator 105 and outputs a predetermined frequency. When a number of double signals are detected, switch 86 is switched.
  • the phase comparator 91 is connected to a 1 / M frequency divider 85 via a switch 86, or a wobble signal input from either the wobble signal generator 105 or a 1 / N frequency divider 9
  • the phase of the signal input from 4 is compared, and the comparison result is output to the loop filter 92.
  • the loop filter 92 removes noise included in the comparison result input from the phase comparator 91, and outputs the result to a VCO (Voltage Control Oscillator) 93.
  • VCO Voltage Control Oscillator
  • VC093 controls the voltage from a power supply (not shown) based on the comparison result input from the phase comparator 91 via the loop filter 92 to generate a PLL clock of about 36 MHz.
  • the signal is supplied to a timing generator and timing counters 103 and 113 (not shown), and output to a 1 / N divider 94. That is, the 1ZN frequency divider divides the input PLL clock by a factor of 360 and outputs the result to the phase comparator 91.
  • the phase comparator 91, the loop filter 92, the VC093, and the 1ZN frequency divider 94 constitute a so-called PLL block 87 with these configurations.
  • the AND circuit 111 of the sub-wobble interpolation unit 83 compares the edge detection signal input from the edge detector 81 with the sub-window pulse supplied from the sub-window pulse generator 112, and generates an edge within the sub-window pulse. When a detection signal is detected, a count value indicating a predetermined timing is output to the timing counter 113 and the switch 102 at the detected timing.
  • the sub window pulse generator 112 is controlled by the controller 84, and the main window output from the main window pulse generator 104 based on the reference signal supplied from the timing counter 113 is Generates different sub-window pulses and outputs them to the AND circuit. More specifically, when a signal is not output after the AND circuit 101 at a predetermined timing (no edge is detected in the main window), the controller 84 detects this and outputs an enable signal. Is output to the subwindow pulse generator 112 and the timing counter 113 to start operation. At this time, the sub window pulse generator 1 1 2 The first subwindow pulse is generated as an open pulse. If the edge detection signal exists and is not simply detected in the main window pulse, the edge will be detected in the sub-window pulse as the release pulse. In FIGS.
  • the main window pulse and the sub-window pulse generate a signal having a predetermined pulse width even after the edge signal is detected, but this is for convenience of explanation. It is displayed as such, and is controlled by edge signals input from the timing counters 103, 113 and AND circuits 101, 111, respectively. The output of the sub window pulse is stopped after the edge is detected, and the edge is not detected until the next main window pulse and sub window pulse are output.
  • the controller 84 is controlled by the drive control microcomputer 42 and controls the entire operation of the timing generator 46.
  • the switch 86 is controlled by the drive control microcomputer 42, and is connected to the terminal 86b. I do. Further, it is assumed that the switch 102 is connected to the terminal 102 a.
  • step S1 the edge detector 81 at time t101 shown in FIG. 8A uses the binary signal of the cobble read by the optical block 47 input from the comparator 63. As shown in FIG. 8C, an edge is detected and output to the AND circuits 101 and 111 as an edge detection signal.
  • step S2 the AND circuit 101 determines whether or not the edge input from the edge detector 81 exists within the main window ⁇ pulse input from the main window pulse generator 104, For example, when it is determined that the edge detection signal exists in the main window at times t1 21 to t1 22 as shown in FIG. 8B as shown at time t101 in FIG. 8C, The processing proceeds to step S3.
  • step S3 the controller 84 executes the sub-population processing described later. It is determined whether or not the process has been performed. If it is determined that the process has not been performed, the process proceeds to step S4.
  • step S4 the AND circuit 101 outputs a counter value indicating a predetermined timing to the timing counter 103.
  • step S5 the timing counter 103 receives the counter value from the AND circuit 101, counts the time corresponding to the counter value from the received timing, and then outputs the reference signal to the main window pulse generator 1 0 4 and output to the multiple signal generator 105.
  • step S6 based on the reference signal input from the timing counter 103, the main window pulse generator 104 outputs a predetermined pulse centering on the time at which the next edge is predicted to be detected.
  • a main window pulse having a width is generated and output to the AND circuit 101, and the double signal generator 105 generates a double signal based on the reference signal input from the timing counter 103. Then, the data is output to the phase comparator 91 via the switch 86, and the processing returns to step S1.
  • the main window pulse generator 104 In response to this reference signal, the main window pulse generator 104 outputs a main window pulse having a predetermined pulse width centered on the predicted time t 103 at which the next edge is detected (from time t 1 23 to time t 1 23 to t 1 1 2 4 main window pulse) and outputs the same to the AND circuit 101, and the cobble signal generator 105 generates a cobble signal based on this reference signal and outputs the same through the switch 86.
  • Phase comparator 9 Output to 1.
  • the edge to be detected at time t105 shown in FIG. 8A is delayed for some reason and is detected at time t'105, then, The main window pulse generated by the main window pulse generator 104 is shifted (delayed) in position. Further, at the next time t107, the same state as the interval up to that time (time tl01, t103, t105, and t107 are respectively shown in FIG. At a fixed interval corresponding to time A), the edge is detected at time t'105, and the next window pulse is the window from time t'127 to t, window 128 since a pulse originally edges detected at time t 1 0 7, in c step S 2 that may not be detected within the window pulse.
  • step S 7 the processing step S 7 (FIG. 7 Proceed to). It should be noted that the time B in FIG. 8B is substantially the same as the time A from the edge detected at the time t'105 shifted to the next edge detection.
  • the controller 84 determines whether the edge has been NG (No Good) consecutively X times (for example, 4 times) in the main window panorama, that is, four consecutive edges have been detected as the main window pulse. It is determined whether or not an edge could not be detected within the main window pulse. If it was determined that an edge could be detected within the main window pulse, the processing was performed. Goes to step S8.
  • step S8 the controller determines whether or not the sub-wobble interpolation process is being executed. If it is determined that the sub-wobble interpolation process is not being executed, in step S9, the controller starts a sub-wobble interpolation process described later. When it is determined that the sub-wobble interpolation processing is already being executed, the processing in step S9 is skipped.
  • step S10 the timing counter 103 sets the main clock based on the PLL clock input from VC093. The reference signal is output to the window pulse generator 104 and the wobbled signal generator 105.
  • step S11 the signal generator 104 outputs a timing counter.
  • a sample signal is output to the PLL block 87 based on the reference signal from 103, and the main window pulse generator 104 generates a main window pulse based on the reference signal.
  • step S3 when the sub-wobble capturing process is already being executed, in step S12, the controller 84 determines that the edge has been detected in the main window, so that the sub-wobble capturing process is performed. Resets the number of times of edge detection in, and stops the sub-population interpolation processing.
  • step S7 four consecutive NGs, that is, if an edge cannot be detected in the main window pulse four consecutive times
  • step S13 the controller 84
  • the main interpolation process is stopped, and if the supplemental capture process is being executed, the sub-population interpolation process is also stopped and the process is terminated.
  • step S21 the edge detector 81 detects an edge from the binary signal input from the comparator 63. Then, the controller 84 outputs an enable signal to the sub-window pulse generator 111 and the timing counter 113, and outputs the enable signal to the sub-window pulse generator 111. Then, an open pulse is generated as a sub-window pulse, and the timing counter 113 outputs a reference signal.
  • step S22 the AND circuit 111 determines whether the edge input from the edge detector 81 has been detected in the subwindow pulse, and determines that an edge has been detected in the subwindow pulse.
  • step S23 the count value indicating the predetermined timing is output to the timing counter 113 and the terminal 102b of the switch 102 in step S23.
  • step S24 the timing counter 1 13 It receives the input counter value, generates a reference signal based on this, and outputs it to the sub-window pulse generator 112.
  • step S25 the sub-window pulse generator 112 generates a sub-window pulse based on the reference signal input from the timing counter 113 and outputs it to the AND circuit 111.
  • step S26 the controller 84 determines whether or not an edge is detected in the sub-window, for example, four times in succession. If it is determined that an edge has been detected, the process proceeds to step S27. .
  • step S27 the controller 84 controls the switch 102, connects it to the terminal 102b, and outputs the value indicating the timing from the AND circuit 111 to the timing counter 103 only once. After that, connect the switch 102 to the terminal 102a.
  • step S28 the controller 84 stops the operations of the subwindow generator 112 and the timing counter 113, and ends the processing. If it is determined in step S22 that an edge is not detected within the sub-window pulse, in step S29, the controller 84 determines whether or not a command to stop operation has been issued by main / off / interpolation processing. However, if the operation stop has not been instructed, the process returns to step S1, and the subsequent processes are repeated. In step S29 (FIG. 9), when the operation stop command is issued, that is, when the operation stop is instructed by the process of step S13 in FIG. 6, the process is terminated.
  • step S26 for example, if it is determined that no edge has been detected in the subwindow pulse four consecutive times, the process returns to step S22, and the subsequent processes are repeated. That is, the processing of steps S22 to S26 is repeated until an edge is detected in the subwindow pulse four times in a row. More specifically, the sub-window pulse generator 112 generates a release pulse (time t ′ 1 28 8) as shown in FIG. 8D based on the enable signal from the controller 8 ′ 4. To t ′ 1 2 9) are generated. At this time, as shown in FIG. 8A, if an edge is detected with a shift only at time t, 105, an edge is detected within this release pulse, for example, at time t109. Will be.
  • the timing counter 113 detects the sub-window pulse at time til 3 to t 13 2 which is the next sub-window pulse from the timing t 109 at which the edge was detected (FIG. 8). D). At this time, since the edge is detected at the time till, the edge is detected within the subwindow pulse of t13 to t132.
  • the switch 102 when an edge is detected four times consecutively in the subwindow pulse, the switch 102 is switched to the terminal 102 b, and the output of the AND circuit 111 is output only once by the timing counter 110. By being output to 3, the reference signal from the timing counter 103 is synchronized with the timing counter 113.
  • the sub wobbled interpolation unit 83 starts the supposable interpolation process (in parallel with the main wobbled interpolation process).
  • the sub-population interpolator 83 outputs the timing of the detected edge to the main copier interpolator 82 only once via the switch 102.
  • the unit 82 can detect edges and edges.
  • the main window pulse generator 104 can generate a main window pulse synchronized with the sub window pulse, and can again detect an edge in the main window pulse.
  • the edge position is detected using the sub-window pulse, and the edge can be detected again in the main window pulse.
  • the stable video signal is supplied to the PLL block 87 by the recorder 105, so that the digital video camera can record data stably on the disc 1. And the recorded data can be read stably.
  • any other disc-shaped recording medium configured to read out the power tracking signal from the page 14 described in the case of the MD as an example of the disc 1 may be used.
  • the switch 102 is switched when the number of times that an edge is detected in the subwindow pulse is four has been described. If the number of wedges is equal to or greater than the number of times, any other number may be used. That is, in the above example, an example is described in which the number of wobbles for which an edge is detected three times is recorded in the address area.
  • a stable wobble signal can be supplied to the PLL block, so that high-density and stable data can be recorded or reproduced on the disk-shaped recording medium.
  • the series of processes described above can be executed by hardware, but can also be executed by software.
  • the programs that make up the software execute various functions by installing a computer built into a dedicated hard disk or by installing various programs. It can be installed on a general-purpose personal computer from a program storage medium.
  • FIG. 11 shows a configuration of an embodiment of a personal computer when the digital recording / reproducing apparatus is realized by software.
  • the CPU 201 of the personal computer controls the entire operation of the personal computer. Also, the CPU 201 responds to a command input from the input unit 206 including a keyboard and a mouse from the user via the bus 204 and the input / output interface 205.
  • ROM Read Only Memory
  • CPU 201 can operate a magnetic disk 2 1 1 connected to drive 2 10
  • the program read from the optical disk 212, magneto-optical disk 211, or semiconductor memory 214 and installed in the storage unit 208 is loaded into the RAM (Random Access Memory) 203 and executed. I do.
  • the functions of the information recording / reproducing apparatus described above are realized by software.
  • the CPU 201 controls the communication unit 209 to communicate with the outside and exchange data.
  • the program storage medium on which the program is recorded is a magnetic disk 2 1 1 (on which the program is recorded, which is distributed separately from the computer to provide the program to the user.
  • Optical disk 2 1 2 (including CD-ROM (Compact Disk-Read Only Memory), DVD (Digital Versati le Di sk)), magneto-optical disk 2 1 3 (including MD (Mini- Disc)) or package media consisting of semiconductor memory 214, etc., as well as being provided to the user in a state in which they are pre-installed in the computer.
  • ROM 202 in which the program is recorded And a hard disk included in the storage unit 208.
  • a step of describing a program recorded on a recording medium is not limited to processing performed in chronological order according to the described order, but is not necessarily performed in chronological order. Alternatively, it includes processing that is executed individually.
  • a stable wobble signal can be supplied to a PLL block, and high-density and stable data can be recorded or reproduced on a disk-shaped recording medium.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Optical Recording Or Reproduction (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

Selon cette invention, une unité de commande (84) actionne un générateur (112) d'impulsions de fenêtre secondaire ainsi qu'un compteur temporel (113) lorsqu'un signal de détection de contours, émis par un détecteur (81) de contours, se trouve en dehors d'une fenêtre principale d'un détecteur d'impulsions (104) de fenêtre principale. Le générateur d'impulsions (112) de fenêtre secondaire génère une impulsion de fenêtre secondaire de la phase opposée à celle de la fenêtre principale. Un circuit AND (11) effectue une comparaison avec le signal de détection de contours et envoie une valeur de comptage correspondante au compteur temporel (113) et à l'unité de commande (84) lorsqu'un contour se trouve dans l'impulsion de fenêtre secondaire. L'unité de commande (84) commute un commutateur (102) à un terminal (102b), pour permettre à un signal provenant du circuit AND (111) d'être acheminé jusqu'au compteur temporel (103) une fois seulement, et connecte à nouveau le commutateur à un terminal (102a). Cette invention peut être appliquée à un appareil servant à enregistrer et à reproduire un support d'enregistrement de type disque.
PCT/JP2002/004518 2001-05-11 2002-05-09 Appareil d'enregistrement et de reproduction d'informations WO2002093574A1 (fr)

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JP2001141044A JP2002334525A (ja) 2001-05-11 2001-05-11 情報記録再生装置および方法、記録媒体、並びにプログラム
JP2001-141044 2001-05-11

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729311A (ja) * 1993-05-14 1995-01-31 Sony Corp デイスク再生装置
JPH10312540A (ja) * 1997-05-09 1998-11-24 Sony Corp 光ディスクの製造方法、光ディスク及び光ディスク装置
JP2000260131A (ja) * 1999-03-04 2000-09-22 Seiko Epson Corp 同期信号の検出保護方法およびその検出保護回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0729311A (ja) * 1993-05-14 1995-01-31 Sony Corp デイスク再生装置
JPH10312540A (ja) * 1997-05-09 1998-11-24 Sony Corp 光ディスクの製造方法、光ディスク及び光ディスク装置
JP2000260131A (ja) * 1999-03-04 2000-09-22 Seiko Epson Corp 同期信号の検出保護方法およびその検出保護回路

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