WO2002084399A1 - Procede de fabrication de masque opc, masque opc et puce associee - Google Patents

Procede de fabrication de masque opc, masque opc et puce associee Download PDF

Info

Publication number
WO2002084399A1
WO2002084399A1 PCT/JP2002/003449 JP0203449W WO02084399A1 WO 2002084399 A1 WO2002084399 A1 WO 2002084399A1 JP 0203449 W JP0203449 W JP 0203449W WO 02084399 A1 WO02084399 A1 WO 02084399A1
Authority
WO
WIPO (PCT)
Prior art keywords
opc mask
new test
test pattern
chip
pattern
Prior art date
Application number
PCT/JP2002/003449
Other languages
English (en)
French (fr)
Inventor
Hidetoshi Ohnuma
Chie Niikura
Original Assignee
Sony Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corporation filed Critical Sony Corporation
Publication of WO2002084399A1 publication Critical patent/WO2002084399A1/ja

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/36—Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • G03F7/70441—Optical proximity correction [OPC]

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
PCT/JP2002/003449 2001-04-13 2002-04-05 Procede de fabrication de masque opc, masque opc et puce associee WO2002084399A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001115632A JP3856197B2 (ja) 2001-04-13 2001-04-13 Ｏｐマスクの製作方法
JP2001-115632 2001-04-13

Publications (1)

Publication Number Publication Date
WO2002084399A1 true WO2002084399A1 (fr) 2002-10-24

Family

ID=18966500

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2002/003449 WO2002084399A1 (fr) 2001-04-13 2002-04-05 Procede de fabrication de masque opc, masque opc et puce associee

Country Status (5)

Country Link
US (1) US20030177467A1 (ja)
JP (1) JP3856197B2 (ja)
KR (1) KR20030007951A (ja)
TW (1) TW554406B (ja)
WO (1) WO2002084399A1 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100444179C (zh) * 2005-11-08 2008-12-17 国际商业机器公司 优化集成电路芯片的方法

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SG137657A1 (en) * 2002-11-12 2007-12-28 Asml Masktools Bv Method and apparatus for performing model-based layout conversion for use with dipole illumination
CN1320404C (zh) * 2003-10-09 2007-06-06 中芯国际集成电路制造(上海)有限公司 集成电路适用的模块化光学近接校正配置及其方法
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
JP2006189724A (ja) * 2005-01-07 2006-07-20 Toshiba Corp パターン抽出システム、測定ポイント抽出方法、パターン抽出方法及びパターン抽出プログラム
US7550237B2 (en) * 2005-01-19 2009-06-23 Winbond Electronics Corp. Systems and methods for determining width/space limits for mask layout
US7325225B2 (en) * 2005-10-05 2008-01-29 Yasushi Tanaka Method and apparatus for reducing OPC model errors
KR100702794B1 (ko) * 2005-12-14 2007-04-03 동부일렉트로닉스 주식회사 Ｏｐｃ 검증을 통한 마스크 레이아웃 보정 방법
KR100662961B1 (ko) 2005-12-17 2006-12-28 동부일렉트로닉스 주식회사 광근접보정 모델링 데이타 추출을 위한 테스트 패턴제작방법
KR100731071B1 (ko) * 2005-12-28 2007-06-22 동부일렉트로닉스 주식회사 마스크 레이아웃의 보정방법
KR100735535B1 (ko) * 2006-07-10 2007-07-04 삼성전자주식회사 마스크 제작 방법
KR100807229B1 (ko) * 2006-07-31 2008-02-28 삼성전자주식회사 마스크의 설계 패턴 보정 방법
KR100811269B1 (ko) * 2006-09-19 2008-03-07 주식회사 하이닉스반도체 광근접 효과 보정을 위한 패턴 모델링 방법
KR100818999B1 (ko) * 2006-10-09 2008-04-02 삼성전자주식회사 마스크 제작 방법
JP2008139688A (ja) * 2006-12-04 2008-06-19 Toshiba Corp 半導体集積回路の製造方法、マスクの製造方法、半導体マスクデータ製造装置、マスクパターンの修正方法、及び設計レイアウトの修正方法
KR100826655B1 (ko) 2007-05-21 2008-05-06 주식회사 하이닉스반도체 광 근접 효과 보정 방법
KR100884985B1 (ko) * 2007-07-19 2009-02-23 주식회사 동부하이텍 광학적 근접보정 모델 조절 시스템 및 데이터 처리 방법
JP4934236B2 (ja) * 2007-09-29 2012-05-16 Ｈｏｙａ株式会社 グレートーンマスクブランク、グレートーンマスクの製造方法及びグレートーンマスク、並びにパターン転写方法
KR100880234B1 (ko) * 2007-10-02 2009-01-28 주식회사 동부하이텍 Ｏｐｃ 마스크 제조방법
KR100906053B1 (ko) * 2007-10-11 2009-07-03 주식회사 동부하이텍 반도체 소자의 ｃｄ 검사 방법
KR101096979B1 (ko) 2010-05-07 2011-12-20 주식회사 하이닉스반도체 반도체 소자의 패턴 균일도 조절 방법
JP5708103B2 (ja) * 2011-03-18 2015-04-30 富士通セミコンダクター株式会社 設計支援方法
CN103513506B (zh) * 2012-06-19 2016-04-13 上海华虹宏力半导体制造有限公司 光学临近效应修正方法
CN104678695B (zh) * 2013-11-26 2019-03-12 中芯国际集成电路制造(上海)有限公司 测试图形的标记方法和标记装置
CN111149063B (zh) * 2017-09-27 2022-04-22 Asml荷兰有限公司 确定器件制造工艺的控制参数的方法
KR20220079649A (ko) * 2019-10-16 2022-06-13 어플라이드 머티어리얼스, 인코포레이티드 패턴들을 형성하는 방법 및 리소그래피 시스템
CN111427240B (zh) * 2020-03-25 2021-06-04 合肥晶合集成电路股份有限公司 一种建立光学数据校正模型的方法
CN116931389B (zh) * 2023-09-18 2023-12-08 粤芯半导体技术股份有限公司 线宽测量方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5776640A (en) * 1996-06-24 1998-07-07 Hyundai Electronics Industries Co., Ltd. Photo mask for a process margin test and a method for performing a process margin test using the same
JPH11218899A (ja) * 1998-01-29 1999-08-10 Sony Corp マスクパターンの補正方法およびその装置
JP2000314954A (ja) * 1999-03-04 2000-11-14 Matsushita Electric Ind Co Ltd Ｌｓｉ用パターンのレイアウト作成方法、ｌｓｉ用パターンの形成方法及びｌｓｉ用マスクデータの作成方法
JP2001100390A (ja) * 1999-09-27 2001-04-13 Toshiba Microelectronics Corp 露光用マスクのパターン補正方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3934719B2 (ja) * 1995-12-22 2007-06-20 株式会社東芝 光近接効果補正方法
US6243855B1 (en) * 1997-09-30 2001-06-05 Kabushiki Kaisha Toshiba Mask data design method
JP3909654B2 (ja) * 2001-05-10 2007-04-25 ソニー株式会社 ルールベースｏｐｃの評価方法およびシミュレーションベースｏｐｃモデルの評価方法並びにマスクの製造方法
KR100506106B1 (ko) * 2001-09-29 2005-08-05 가부시끼가이샤 도시바 마스크 패턴 작성 방법 및 반도체 장치의 제조 방법
JP3615182B2 (ja) * 2001-11-26 2005-01-26 株式会社東芝 光近接効果補正方法及び光近接効果補正システム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5776640A (en) * 1996-06-24 1998-07-07 Hyundai Electronics Industries Co., Ltd. Photo mask for a process margin test and a method for performing a process margin test using the same
JPH11218899A (ja) * 1998-01-29 1999-08-10 Sony Corp マスクパターンの補正方法およびその装置
JP2000314954A (ja) * 1999-03-04 2000-11-14 Matsushita Electric Ind Co Ltd Ｌｓｉ用パターンのレイアウト作成方法、ｌｓｉ用パターンの形成方法及びｌｓｉ用マスクデータの作成方法
JP2001100390A (ja) * 1999-09-27 2001-04-13 Toshiba Microelectronics Corp 露光用マスクのパターン補正方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100444179C (zh) * 2005-11-08 2008-12-17 国际商业机器公司 优化集成电路芯片的方法

Also Published As

Publication number Publication date
TW554406B (en) 2003-09-21
JP2002311562A (ja) 2002-10-23
US20030177467A1 (en) 2003-09-18
JP3856197B2 (ja) 2006-12-13
KR20030007951A (ko) 2003-01-23

Similar Documents

Publication Publication Date Title
WO2002084399A1 (fr) Procede de fabrication de masque opc, masque opc et puce associee
KR100872731B1 (ko) 룰 베이스 ｏｐｃ의 평가 방법 및 시뮬레이션 베이스 ｏｐｃ 모델의 평가 방법
US10025894B2 (en) System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking
WO2005081910A3 (en) Generalization of the photo process window and its application to opc test pattern design
WO2005008747A3 (en) Methods and systems for inspection of wafers and reticles using designer intent data
JP2008509452A (ja) モノリシックなシリコンベースの光電子回路の設計、シミュレーション、及び検査用の統合的アプローチ
TWI468964B (zh) 製作電性正確的積體電路的方法
CN101311825A (zh) 修正光学邻近效应的方法
CN103472672B (zh) 校正光学邻近校正模型的方法
JP2006332348A (ja) 半導体集積回路の設計方法およびライブラリの設計方法
KR20110094467A (ko) 리타겟 프로세스 모델링 방법, 및 그 프로세스 모델링 방법을 이용한 마스크 제조방법
KR102622415B1 (ko) 표준 셀 설계 시스템, 그것의 표준 셀 설계 최적화 방법, 및 반도체 설계 시스템
TW200509215A (en) Pattern dimension correction method and verification method using OPC, mask and semiconductor device fabricated by using the correction method, and system and program for executing the correction method
US20110172983A1 (en) Method for incorporating pattern dependent effects in circuit simulations
WO2004081988A3 (en) Model pattern simulation of semiconductor wafer processing steps
CN105334694A (zh) 一种光刻胶侧墙角度的预测及改善方法
Bogaerts et al. Layout-aware yield prediction of photonic circuits
CN103777457A (zh) 一种用于接触孔图形设计的光学邻近修正的方法
JP2006343217A (ja) 回路シミュレーション方法および回路シミュレーション装置
US20100037193A1 (en) Method of correcting pattern layout
CN104698761A (zh) 基于面积的opc模型校准方法
WO2012081158A1 (ja) 回路シミュレーション方法及び半導体集積回路
KR102089083B1 (ko) 회로 설계의 누설 전력을 조기에 추정하기 위한 시스템 및 방법
KR20080020417A (ko) Ｃｍｏｓ 소자의 ｓｐｉｃｅ 모델링 방법
CN104765246A (zh) 集成目标图形优化与光学邻近修正的方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR US

WWE Wipo information: entry into national phase

Ref document number: 1020027016868

Country of ref document: KR

WWE Wipo information: entry into national phase

Ref document number: 10311157

Country of ref document: US

WWP Wipo information: published in national office

Ref document number: 1020027016868

Country of ref document: KR