WO2002069284A1 - Zeiterfassungsvorrichtung und zeiterfassungsverfahren unter verwendung eines halbleiterelements - Google Patents
Zeiterfassungsvorrichtung und zeiterfassungsverfahren unter verwendung eines halbleiterelements Download PDFInfo
- Publication number
- WO2002069284A1 WO2002069284A1 PCT/EP2002/001013 EP0201013W WO02069284A1 WO 2002069284 A1 WO2002069284 A1 WO 2002069284A1 EP 0201013 W EP0201013 W EP 0201013W WO 02069284 A1 WO02069284 A1 WO 02069284A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- gate electrode
- semiconductor element
- nitride layer
- layer
- charges
- Prior art date
Links
- 238000001514 detection method Methods 0.000 title claims abstract 7
- 239000004065 semiconductor Substances 0.000 title claims description 25
- 150000004767 nitrides Chemical class 0.000 claims abstract description 50
- 238000002347 injection Methods 0.000 claims abstract description 31
- 239000007924 injection Substances 0.000 claims abstract description 31
- 230000005484 gravity Effects 0.000 claims abstract description 14
- 230000005540 biological transmission Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 18
- 230000000694 effects Effects 0.000 claims description 10
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 239000002800 charge carrier Substances 0.000 description 13
- 238000005259 measurement Methods 0.000 description 8
- 230000006399 behavior Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001609 comparable effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000009979 protective mechanism Effects 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F1/00—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers
- G04F1/005—Apparatus which can be set and started to measure-off predetermined or adjustably-fixed time intervals without driving mechanisms, e.g. egg timers using electronic timing, e.g. counting means
-
- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Definitions
- the present invention relates to time recording devices and methods, and in particular to those time recording devices and methods that can be used to implement a currentless time standard, for example to enable a delay in the access time to a chip.
- Electronic circuits for example chip card ICs
- Electronic circuits are subject to a special requirement with regard to warding off unauthorized access.
- electronic circuits that perform security-relevant functions for example chip card ICs
- encryption methods In order to provide such encryption methods, the electronic circuit can be addressed with only gradually changing signal patterns, for example in the context of a DPA (differential power analysis), the electronic circuit being periodically switched on and off in the case of such attacks.
- DPA differential power analysis
- Circuit or the chip card IC enables a certain number of switch-on processes. This attack can be aggravated or prevented by extending the time between the switch-on processes or by allowing only a certain number of switch-on processes in a given time interval.
- a semiconductor integrated circuit is known from US Pat. No. 5,760,644, by means of which a time lapse can be detected.
- charge carriers are introduced into a storage dielectric for this purpose, changes in the electric field caused by the charge introduced into the dielectric being used for time recording. This electric field changes with increasing natural charge loss in the dielectric material, so that the measurement of the electric field over time enables statements to be made about an elapsed time.
- US Pat. No. 5760,644 charge carriers are introduced into a storage dielectric for this purpose, changes in the electric field caused by the charge introduced into the dielectric being used for time recording. This electric field changes with increasing natural charge loss in the dielectric material, so that the measurement of the electric field over time enables statements to be made about an elapsed time.
- the ONO structure (oxide nitride oxide structure) of a SONOS transistor (silicon ONO silicon transistor) or the NO structure (nitride oxide structure) of an SNOS transistor is used as the storage dielectric (Silicon-NO-silicon transistor) is used.
- the ONO dielectric or the NO dielectric of the above-mentioned memory transistors the time-dependent loss of charge of the electrons stored in nitride is verified by the changed threshold voltage of the cell.
- the object of the present invention is to provide an apparatus and a method for time tracking, allowing a largely temperature-independent and can not be influenced from outside "realization of a time standard.
- a time recording device comprises a semiconductor element with a transistor structure, for example in the form of an EEPROM cell.
- a gate dielectric is arranged over the channel region of the memory transistor, over which a floating gate Electrode is arranged, which is isolated from a control gate electrode by an NO layer sequence (nitride oxide layer sequence) or an ONO layer sequence (oxide nitride oxide layer sequence).
- charges are now injected into the floating gate electrode and from there into the nitride layer of the insulation between the floating gate electrode and the control gate electrode for time recording or for realizing a time standard, the charge center of gravity following such an injection charges injected into the nitride layer are located at the interface between the oxide layer facing the floating gate electrode and the nitride layer of the ON structure or the ONO structure between the floating gate electrode and control gate electrode.
- the shift in the center of gravity of these injected charges away from the interface is used for time measurement, this shift having an influence on the transmission behavior of the channel area of the memory cell.
- electrons or holes can be injected into the ON layer sequence or the ONO layer sequence, with the charge carriers initially being located near their injection, ie in the nitride layer at the interface between that of the floating and Gate electrode facing oxide layer and the nitride layer.
- These charge carriers later begin to migrate through the nitride through a trap-assisted line mechanism, which is referred to as a double line, so that the center of gravity of the charge is shifted.
- This shift in the center of charge can now be detected by a suitable method, namely based on changes in the transmission behavior of the channel region of the memory cell, so that the desired time standard is created.
- an EEPROM memory cell as used according to the invention for time measurement, charges for storing information are injected into the floating gate electrode during normal operation, the charge injection into the ON insulation layer sequence or the ONO insulation layer sequence being merely an undesirable side effect , According to the invention, this side effect is used for time measurement, this side effect occurring in proportionally increased fashion when more charges are injected into the EEPROM memory cell.
- This effect can be used for time recording by injecting a larger number of charges into a time measuring cell and injecting a smaller number of charges into a reference cell, whereby the amount of charge that is injected into the time measuring cell must be sufficient to achieve one To effect injection of charges into the nitride layer.
- the elapse of a predetermined elapsed time can be detected in that the threshold voltage of the reference cell and the time measuring cell have a predetermined relationship to one another after the corresponding charge carrier injections, for example have dropped to the same value, the threshold voltage to the control Gate voltage to be applied is understood, which is required to cause a predetermined current flow through the channel region of the respective cell.
- FIG. 1 schematically shows the structure of an EEPROM memory cell
- Fig. 2 is a diagram showing the threshold voltage V E over time for different levels of ection voltage; and 3 shows a schematic illustration of an exemplary embodiment of a time recording device according to the invention.
- FIG. 1 shows a schematic cross-sectional view of such an EEPROM memory cell, in which source / drain regions 2 are provided by corresponding implantations in the doped well 4 of a semiconductor substrate 6.
- a gate oxide 10 is provided above the channel region 8 of the memory cell which is arranged between the source / drain regions and over which a floating gate electrode 12 is arranged.
- An ONO layer sequence consisting of a lower oxide layer 16, a nitride layer 18 and an upper oxide layer 20 is provided between the floating gate electrode 12 and a control gate electrode 14.
- the gate oxide 10, or the gate oxide layer has a region 22 of small thickness, which represents a tunnel window.
- An injection implantation 24 is provided in the doped trough 4 below the tunnel window 22.
- the source / drain regions are provided with respective source / drain connections 26 and the control gate electrode is provided with a control gate connection 28.
- FLOTOX FLOTOX
- other transistor structures which have a floating gate for example known flash cells in which electrons are applied to the floating gate by injection of hot electrons, can be used.
- the logical state of the EEPROM memory cell shown in FIG. 1 when it is used as memory is determined by the charge state of the floating gate 12.
- a suitable injection voltage is used applied to the control gate connection 28, whereby a Fowler-Nordheim tunnel of charge carriers takes place through the tunnel window 22 onto the floating gate electrode 12.
- the charges thus applied to the floating gate electrode 12 influence the transmission behavior of the channel region 8, so that the threshold voltage V E changes, that is to say the voltage required at the control gate connection 28, in order to provide a predetermined channel current between the source / drain Areas 2 that can be tapped via the connections 26. If the dopings and voltages used are such that electrons are injected onto the floating gate electrode 12, the threshold voltage shifts with increasing
- the logical state of the cell is usually a predetermined one
- Voltage is applied to the control gate electrode 28, the channel current then being a criterion for the logic state of the cell.
- the reading level that is to say the voltages to be applied to the control gate electrode for reading out the cell, must be selected in such a way that “programming” of the cell is excluded even after a large number of read accesses.
- charge carriers are thus injected onto the floating gate electrode of the memory cell in normal operation. In addition to this injection of charge carriers into the floating gate electrode, however, if the injection voltage is sufficiently high or if a sufficiently large number of voltage pulses are used, charge carriers are also injected into the nitride layer 18 via a tunnel effect through the lower oxide layer 16.
- the charge carriers injected in this way into the nitride layer 18 are initially localized in the vicinity of their injection, ie at the interface between the lower oxide layer 16 and the nitride layer 18. After the completion of the charge carrier injection and without applying an external voltage, this charge center of gravity shifts in the direction of the control gate electrode 14, this charge center of gravity being brought about essentially by hopping mechanisms (Poole-Frenkel electron hopping). This shifting mechanism is indicated by arrows in the nitride layer 18 in FIG. 1 and continues until no more charge carriers or electrons can be moved by the resulting total field. The majority of the charges injected into the nitride are then located at the interface between the nitride layer 18 and the upper oxide layer 20.
- the charge injected into the nitride layer 18 has an influence on the channel behavior of the cell.
- the proximity of the charges to the channel therefore has a direct influence on the threshold voltage of the transistor or the memory cell.
- This threshold voltage is therefore dependent on the local position of the center of gravity of the charges in the nitride. The closer this center of gravity is to the control gate electrode 14, the higher the threshold voltage of the cell. Since the charge shift described above takes place in the nitride layer 18 as a function of time, it can be used for time recording or for realizing a time standard by monitoring the charge shift by observing the threshold voltage of the cell.
- FIG. 2 shows the threshold voltages V E of an EEPROM cell as described above over time, curve 40 showing the threshold voltage for injection voltages with a large pulse height, while curve 42 representing the threshold voltage for injection voltages with a smaller pulse height , Typical injection voltages that lead to a curve 40 in typical EEPROM cells have, for example, a pulse height of 17 V, while injection voltages that lead to the curve 42 have a pulse height of 14 V, for example.
- Curves 40 and 42 were obtained using an EEPROM cell, whose lower oxide layer 16 had a thickness of 5 nm and whose nitride layer 18 had a thickness of 20 nm.
- the curves 40 and 42 shown in FIG. 2 show a threshold voltage which decreases with time, the loss of threshold voltage being divided into two phases.
- the first phase shows a rapid decrease in the threshold voltage, while thereafter a continuous drop in the threshold voltage is visible, the first phase ending in the region of the dashed line 44 shown in FIG. 2.
- the rapid drop in the first phase is caused by the charge shift in the nitride layer 16 described above, while leakage currents are responsible for the continuous drop in the second phase.
- the rapid drop in the threshold voltage is used in the first phase of the posture curves 40 and 42 for time recording. It can be seen from FIGS. 40 and 42 in FIG. 2 that this effect of the drop in the threshold voltage increases proportionally with increasing pulse height of the injection voltage. apparition occurs.
- the pulse height of the injection voltage used changes the ratio between the charge that is injected onto the floating gate and the charge that is injected into the nitride layer.
- the greater the pulse height the greater the proportion of the charge that is injected into the nitride layer.
- the influence of the charge shift described in the nitride layer on the course of the threshold voltage, as shown for example in FIG. 2 increases.
- injection voltages must be used according to the invention which, in addition to charge carrier tunneling through the tunnel window 22, also cause tunneling through the lower oxide layer 16 into the nitride layer 18.
- the level of the injection voltages to be used in practice depends on the particular design of the memory cell.
- time recording can be carried out without further ado based on the change in the operating voltage, which is caused by the charge shift described.
- An exemplary embodiment of how the expiration of a predetermined time can be detected according to the invention is described below with reference to FIG. 3.
- a time scale cell 50 and a reference cell 52 are used, both of which, for example, have the above-described construction of a floating gate cell with an ONO structure as an interpolydielectric, i. H. as a dielectric between the floating gate and control gate.
- the time recording device includes one
- Control device 54 which on the one hand has a charge carrier injection device 56 and on the other hand a device 58 for detecting a time which has elapsed since the injection of charges into such a floating gate cell.
- the control device 54 is connected in a suitable form to the time scale cell 50 and the reference cell 52.
- the floating gate cells of both cells 50 and 52 are negatively charged by a positive voltage pulse, which may have a height of 17 V, for example, at the control gate, so that the threshold voltage of the cells is positive, ie a value of 4, for example V own.
- the floating gate of the time scale cell is then further negatively charged by one or more further voltage pulses, for example to a threshold voltage of 5 V.
- the stronger center of gravity in the time scale cell 50 shifts its center of charge in the nitride layer so that the threshold voltage of the cell drops.
- the use of further voltage pulses has a comparable effect to the use of higher voltage pulses with regard to the charge distribution between the floating gate and the nitride layer, so that the change in charge-induced voltage changes in the time scale cell is greater than in the reference cell.
- the time until the threshold voltage of the time scale cell again corresponds to that of the reference cell can be used as the time standard, this being possible by comparing the threshold voltages of the two cells, which is carried out in the device 58.
- the chip can only be operated again, for example, when such a match of the threshold voltages or a predetermined ratio of the threshold voltages to one another is determined.
- a charge shift in an ON layer or an ONO layer is thus used as the time standard, in contrast to known methods, for example that described in US Pat. No. 5,760,644, in which natural volatilization of charges in the storage dielectric of a SONOS cell is used for time recording.
- the present invention thus enables improved resolution compared to known methods, since, as described above, the use of suitable injection voltage pulse a proportionally increased threshold voltage drop, which is caused by the charge shift described, can be achieved.
- the present invention enables a time measurement that is largely temperature-independent and cannot be influenced from the outside.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Measurement Of Unknown Time Intervals (AREA)
- Burglar Alarm Systems (AREA)
- Electrochromic Elements, Electrophoresis, Or Variable Reflection Or Absorption Elements (AREA)
- Recording Measured Values (AREA)
- Electrotherapy Devices (AREA)
- Branch Pipes, Bends, And The Like (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2002233313A AU2002233313A1 (en) | 2001-02-23 | 2002-01-31 | Time-detection device and time- detection method by using a semi-conductor element |
EP02700209A EP1362332B1 (de) | 2001-02-23 | 2002-01-31 | Zeiterfassungsvorrichtung und zeiterfassungsverfahren unter verwendung eines halbleiterelements |
DE50202374T DE50202374D1 (de) | 2001-02-23 | 2002-01-31 | Zeiterfassungsvorrichtung und zeiterfassungsverfahren unter verwendung eines halbleiterelements |
JP2002568323A JP3868906B2 (ja) | 2001-02-23 | 2002-01-31 | 半導体素子を用いた時間検出装置および時間検出方法 |
AT02700209T ATE290243T1 (de) | 2001-02-23 | 2002-01-31 | Zeiterfassungsvorrichtung und zeiterfassungsverfahren unter verwendung eines halbleiterelements |
US10/638,598 US6909294B2 (en) | 2001-02-23 | 2003-08-11 | Time recording device and a time recording method employing a semiconductor element |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10108913.9 | 2001-02-23 | ||
DE10108913A DE10108913A1 (de) | 2001-02-23 | 2001-02-23 | Zeiterfassungsvorrichtung und Zeiterfassungsverfahren unter Verwendung eines Halbleiterelements |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/638,598 Continuation US6909294B2 (en) | 2001-02-23 | 2003-08-11 | Time recording device and a time recording method employing a semiconductor element |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2002069284A1 true WO2002069284A1 (de) | 2002-09-06 |
WO2002069284A8 WO2002069284A8 (de) | 2002-11-14 |
Family
ID=7675344
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2002/001013 WO2002069284A1 (de) | 2001-02-23 | 2002-01-31 | Zeiterfassungsvorrichtung und zeiterfassungsverfahren unter verwendung eines halbleiterelements |
Country Status (9)
Country | Link |
---|---|
US (1) | US6909294B2 (de) |
EP (1) | EP1362332B1 (de) |
JP (1) | JP3868906B2 (de) |
CN (1) | CN1228739C (de) |
AT (1) | ATE290243T1 (de) |
AU (1) | AU2002233313A1 (de) |
DE (2) | DE10108913A1 (de) |
TW (1) | TW580611B (de) |
WO (1) | WO2002069284A1 (de) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009087335A1 (fr) | 2008-01-11 | 2009-07-16 | Stmicroelectronics (Rousset) Sas | Cellule eeprom a perte de charges |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7075284B2 (en) * | 2002-07-08 | 2006-07-11 | Kabushiki Kaisha Toshiba | Time limit function utilization |
KR100885910B1 (ko) * | 2003-04-30 | 2009-02-26 | 삼성전자주식회사 | 게이트 적층물에 oha막을 구비하는 비 휘발성 반도체메모리 장치 및 그 제조방법 |
JP4239944B2 (ja) * | 2004-09-28 | 2009-03-18 | セイコーエプソン株式会社 | プロジェクタ、及びプロジェクタ等に用いられる偏光部材 |
KR100731058B1 (ko) * | 2005-12-26 | 2007-06-22 | 동부일렉트로닉스 주식회사 | 이중 터널 산화막을 포함하는 플래시 메모리 셀 및 그 제조방법 |
FR2900479B1 (fr) * | 2006-04-27 | 2008-10-17 | St Microelectronics Crolles 2 | Circuit d'horloge pour circuit integre et procede d'elaboration d'une valeur de comptage d'un tel circuit d'horloge |
FR2904464A1 (fr) * | 2006-07-27 | 2008-02-01 | St Microelectronics Sa | Circuit eeprom de retention de charges pour mesure temporelle |
DE102006055618B4 (de) * | 2006-11-24 | 2011-05-12 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Mobiler elektrostatischer Trägerwafer mit elektrisch isoliertem Ladungsspeicher, Anordnung zur Halterung und Verfahren zum Halten und Lösen eines scheibenförmigen Bauteils |
JP4469877B2 (ja) * | 2007-07-12 | 2010-06-02 | 株式会社東芝 | 電子装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04294292A (ja) * | 1991-03-22 | 1992-10-19 | Citizen Watch Co Ltd | 時間測定回路および時間測定方法 |
US5760644A (en) * | 1995-10-25 | 1998-06-02 | Nvx Corporation | Integrated circuit timer function using natural decay of charge stored in a dielectric |
WO2001017025A2 (de) * | 1999-09-01 | 2001-03-08 | Infineon Technologies Ag | Halbleiterbauelement als verzögerungselement und verwendung eines halbleiterbauelementes |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2877642B2 (ja) * | 1992-12-25 | 1999-03-31 | ローム株式会社 | 半導体記憶装置およびその駆動方式 |
US6006304A (en) * | 1993-06-25 | 1999-12-21 | Hitachi, Ltd. | Apparatus and method for calculating an erasure time for data stored in a flash memory |
JP3710507B2 (ja) * | 1994-01-18 | 2005-10-26 | ローム株式会社 | 不揮発性メモリ |
US6087885A (en) * | 1997-09-11 | 2000-07-11 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device allowing fast and stable transmission of signals |
US6040996A (en) * | 1998-11-16 | 2000-03-21 | Chartered Semiconductor Manufacturing, Ltd. | Constant current programming waveforms for non-volatile memories |
-
2001
- 2001-02-23 DE DE10108913A patent/DE10108913A1/de not_active Withdrawn
-
2002
- 2002-01-31 AT AT02700209T patent/ATE290243T1/de active
- 2002-01-31 CN CNB028047923A patent/CN1228739C/zh not_active Expired - Fee Related
- 2002-01-31 JP JP2002568323A patent/JP3868906B2/ja not_active Expired - Fee Related
- 2002-01-31 AU AU2002233313A patent/AU2002233313A1/en not_active Abandoned
- 2002-01-31 EP EP02700209A patent/EP1362332B1/de not_active Expired - Lifetime
- 2002-01-31 DE DE50202374T patent/DE50202374D1/de not_active Expired - Lifetime
- 2002-01-31 WO PCT/EP2002/001013 patent/WO2002069284A1/de active IP Right Grant
- 2002-02-20 TW TW091102910A patent/TW580611B/zh active
-
2003
- 2003-08-11 US US10/638,598 patent/US6909294B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04294292A (ja) * | 1991-03-22 | 1992-10-19 | Citizen Watch Co Ltd | 時間測定回路および時間測定方法 |
US5760644A (en) * | 1995-10-25 | 1998-06-02 | Nvx Corporation | Integrated circuit timer function using natural decay of charge stored in a dielectric |
WO2001017025A2 (de) * | 1999-09-01 | 2001-03-08 | Infineon Technologies Ag | Halbleiterbauelement als verzögerungselement und verwendung eines halbleiterbauelementes |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN vol. 017, no. 105 (P - 1495) 3 March 1993 (1993-03-03) * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2009087335A1 (fr) | 2008-01-11 | 2009-07-16 | Stmicroelectronics (Rousset) Sas | Cellule eeprom a perte de charges |
FR2926400A1 (fr) * | 2008-01-11 | 2009-07-17 | St Microelectronics Rousset | Cellule eeprom a perte de charges |
Also Published As
Publication number | Publication date |
---|---|
DE10108913A1 (de) | 2002-09-12 |
EP1362332B1 (de) | 2005-03-02 |
CN1491406A (zh) | 2004-04-21 |
JP2004534938A (ja) | 2004-11-18 |
DE50202374D1 (de) | 2005-04-07 |
JP3868906B2 (ja) | 2007-01-17 |
US6909294B2 (en) | 2005-06-21 |
TW580611B (en) | 2004-03-21 |
CN1228739C (zh) | 2005-11-23 |
US20040032244A1 (en) | 2004-02-19 |
AU2002233313A1 (en) | 2002-09-12 |
WO2002069284A8 (de) | 2002-11-14 |
ATE290243T1 (de) | 2005-03-15 |
EP1362332A1 (de) | 2003-11-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3121753C2 (de) | ||
EP0916138B1 (de) | Verfahren zum betrieb einer speicherzellenanordnung | |
DE4000787C2 (de) | Elektrisch loesch- und programmierbare halbleiterspeichervorrichtung | |
DE4311358C2 (de) | Nicht-flüchtige Halbleiterspeichereinrichtung und Betriebsverfahren für eine nicht-flüchtige Halbleiterspeichereinrichtung und Verfahren zum Programmieren von Information in eine nicht-flüchtige Halbleiterspeichereinrichtung | |
DE3117719C2 (de) | ||
DE2828855C2 (de) | Wortweise elektrisch umprogrammierbarer, nichtflüchtiger Speicher sowie Verfahren zum Löschen bzw. Einschreiben eines bzw. in einen solchen Speicher(s) | |
DE112005001595B4 (de) | Verfahren zum Verbessern der Löschspannungsverteilung für ein Flash-Speicher-Array mit Platzhalterwortleitungen | |
DE19704999C2 (de) | Verfahren zum Programmieren eines nichtflüchtigen Speichers | |
DE3103160A1 (de) | Nichtfluechtiger eprom mit erhoehtem wirkungsgrad | |
DE19724221A1 (de) | Nichtflüchtiger Speicher | |
DE112004000703B4 (de) | Verfahren zum Betrieb einer Doppelzellenspeichereinrichtung mit einer verbesserten Lesebereichsspanne über die Lebensdauer hinweg | |
DE19743555C2 (de) | Nichtflüchtiges Speicherbauteil | |
WO1998006140A1 (de) | Verfahren zum betrieb einer speicherzellenanordnung | |
EP1362332B1 (de) | Zeiterfassungsvorrichtung und zeiterfassungsverfahren unter verwendung eines halbleiterelements | |
DE112004002678B4 (de) | Elektrisch programmierbares 2-Transistoren-Sicherungselement mit einfacher Polysiliziumschicht und elektrisch programmierbare Transistor-Sicherungszelle | |
DE10158019C2 (de) | Floatinggate-Feldeffekttransistor | |
DE2614698A1 (de) | Halbleiterspeicher | |
DE112004000658B4 (de) | Verfahren zum Programmieren einer Doppelzellenspeichereinrichtung zur Speicherung von Mehrfach-Datenzuständen pro Zelle | |
DE19947117B4 (de) | Ferroelektrischer Transistor und dessen Verwendung in einer Speicherzellenanordnung | |
DE69730306T2 (de) | Dateneinschreibschaltung für nichtflüchtigen Halbleiterspeicher | |
DE602004010055T2 (de) | Nichtflüchtige Halbleiterspeicherzelle und dessen Betriebsverfahren | |
EP0946991B1 (de) | Nichtflüchtige speicherzelle | |
DE10323400B4 (de) | Verfahren zum Löschen eines nichtflüchtigen Speichers unter Verwendung sowohl des Sourcebereichs als auch des Kanalbereichs einer Speicherzelle | |
DE19941684B4 (de) | Halbleiterbauelement als Verzögerungselement | |
DE10304654A1 (de) | Speicherzelle, Speicherzellen-Anordnung und Verfahren zum Herstellen einer Speicherzelle |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: C1 Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SD SE SG SI SK SL TJ TM TN TR TT TZ UA UG US UZ VN YU ZA ZM ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: C1 Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG |
|
CFP | Corrected version of a pamphlet front page | ||
CR1 | Correction of entry in section i |
Free format text: PAT. BUL. 36/2002 UNDER (51) REPLACE "G07F 1/00" BY "G04F 1/00" |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002700209 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 920/KOLNP/2003 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2002568323 Country of ref document: JP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 10638598 Country of ref document: US Ref document number: 028047923 Country of ref document: CN |
|
WWP | Wipo information: published in national office |
Ref document number: 2002700209 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
WWG | Wipo information: grant in national office |
Ref document number: 2002700209 Country of ref document: EP |