Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
  • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
  • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
  • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part

Definitions

• the present invention relates to providing increased data access speed in computer memories without increasing the basic clock rate of the memory. DESCRIPTION RELATIVE TO THE PRIOR ART TERMINOLOGY Throughout this description the following terms are used:
• DIMM Dual In line Memory Module
• SDRAM Synchronous Dynamic Random Access Memory.
• DDR Double Data Rate. Data bit duration equals one half the period of the clock frequency. Two bits of data are used in one period of the base clock. See
• SDR Single Data Rate.
• DBF Data Bit Frequency. The number of bits per second per pin. Referred to as xx bit/sec/pin.
• the Data Bit duration equal to one period of the base clock.
• Double Bus Rate means that the Data Rate out of and into a BUS system will be double of what each individual chip connected to the BUS delivers at its operating clock frequency.
• a memory chip of the single data rate type SDR operating at a certain base frequency will produce data rate DR of one period of the base frequency.
• a DR of 100 MHz means that the duration of each data bit will be equal to one period of the 100 MHz frequency which is equal to 10 nanoseconds.
• the data bit pulse- width coming out of the DRAM chip will be one period of the base clock. Therefore, as shown in figure 1 A, the actual frequency [MPW1] of any data bit alternating between 1 and 0 when the base clock is 100 MHz is 50 MHz.
• a cluster of memory chips such as SDRAMs
• SDRAMs are assembled together on a printed circuit board.
• the smallest bus-width is the actual number of bits coming out of a single SDRAM chip in a cluster of one).
• These boards are configured in several forms, known as SIMMs, DIMMs, SODIMMs, RIMMs, etc.
• SIMMs SIMMs
• DIMMs DIMMs
• SODIMMs SODIMMs
• RIMMs etc.
• DIMM will be used hereinafter to refer to any or all of these different types.
• the prior art DIMM module of 168 pins (the design applies to any DIMM of any other pin count, or any other package known by any other name), currently uses (as defined by the JEDEC 1 Committee) 72 Data bits bus, Control lines, Address lines, Power and Clocks.
• the present modules as defined by the JEDEC standard can accommodate up to two Banks or Rows of SDRAM chips. Other configurations of banks are also used depending on the system architecture. The selection of the Banks is controlled by a single Chip Select (CS) line or a combination of the Chip Selects and other control lines.
• the DIMM module is either a Register or Non-Register configuration. In a Register configuration all the Address and Control lines are latched into a Register first before they are presented to the devices to be selected for operation.
• Non-Register[MPW2] configuration the Address and Control lines are wired directly from the input tabs of the DIMM to the devices.
• Either configuration can have a Phase Locked Loop (PLL) for clock synchronization or utilize the clock presented to the DIMM by the system.
• PLL Phase Locked Loop
• the module can only produce a maximum DR of 100 MHz. If the clock frequency is raised to 133 MHz, and the SDRAM devices on the DIMM operate at 133 MHz, the maximum DR is increased to 133 MHz. In order to achieve 200 MHz DR, the SDRAM chips must operate at the base frequency of 200 MHz.
• the data bit at pin D 102,107 will either come from chip A or chip B.
• the clock which appears at the input pin of chip A 104 and chip B 105 has a 100 MHZ frequency.
• a typical clock cycle begins at tl with an positive-going signal, and ends at t2, 10 nanoseconds later.
• a typical data signal, shown as Figure 2C is synchronized with the data signal, so that a data "one" condition begins at tl, and ends at t2, while the following data "zero" begins at t2 and ends at t3. It should be noted that the highest bandwidth data signal which be processed by this system is one with alternating ones and zeros.
• the JEDEC group has developed an architecture wherein one bit of data has duration of validity equal to one half the period of the base clock frequency. This scheme is Called DDR for (Double Data Rate).
• a DIMM designed with such SDRAM devices is called DDR DIMM.
• DDR DIMM Although such DDR memories are currently in existence, they require memory chips operating at twice the clock frequency. Such high speed memory chips are expensive and difficult to produce.
• Figure 1 A through IC the rates of the various signals described herein are shown. Referring now to the first such waveform, a 100 MHz clock is shown Fig 1 A, together with a typical data bus signal (a single bit only is shown for illustrative purposes) of the prior art DIMM, in Fig IB. Each data bit begins in synchronism with a positive-going edge tlof the clock signal. This waveform is typical of the SDR configuration of the prior art.
• each data bit of the DDR data signal begins with either the positive-going edge tl of the clock signal, or the negative-going edge tl2 of the clock signal.
• the devices used incorporate a 100 MHz base clock frequency, and a
• DDR Double Data Rate / Double Bus Rate
• a computer memory system with a data bus includes a first bank memory bank with data lines; a second memory bank having data lines; and a clock signal having a multiplicity of cycles, each having a start, and a period p;
• the system includes a first switching means to connect the data lines of the first memory bank with the data bus beginning at the start of each cycle, and lasting for a time p/2 , and a second switching means to connect the data lines of the second memory bank with the data bus beginning at p/2 after the start of each cycle, and lasting for a time p/2 thereafter.
• the computer memory system also includes a delayed clock signal at a phase 180 degrees relative to the clock signal, with the second switching means synchronized with the delayed clock signal.
• the system includes a motherboard, and the means to generate the delayed clock signal, the first memory bank, the second memory bank, the first switching means, and the second switching means are all located on the motherboard.
• the system includes one or more DIMM boards, and the means to generate the delayed clock signal, the first memory bank, the second memory bank, the first switching means, and the second switching means are located on the DIMM boards.
• the first switching means includes first FET switch
• the second switching means includes a second FET switch.
• the first FET switch includes a control input, a first side connected with the data bus, and a second side connected to the data lines of the first memory bank.
• the second FET switch further includes a control input, with a first side connected with the data bus, and a second side connected to the data lines of the second memory bank.
• the first switching means includes a first data enable signal operating on a first memory chip
• the second switching means includes a second data enable signal operating on a second memory chip.
• the system also includes a circuit having an input and an output, with the input connected to the clock signal, and the delayed clock signal the output, selected from the group which consists of wire length delay circuits, skewed output driver delay circuits, cascaded PLLs delay circuits, skewed output PLL delay circuits, external to PLL delay circuits, passive element delay circuits, and programmed delay lines.
• a computer memory system having a data bus includes a first bank memory bank having data lines, a second memory bank having data lines, and a clock signal having a multiplicity of cycles, each having a start, and a period p. It also has a first switching means to connect the data lines of the first memory bank with the data bus beginning at the start of each cycle, and lasting for a time p/4 , and starting again at p/2 after the start of each cycle, and lasting for a time p/4.
• Figure 1 A depicts a system clock waveform.
• Figure IB depicts a typical SDR data stream.
• Figure 1 (c ) depicts a typical DDR data stream.
• Figure ID depicts a delayed clock 90 degrees out of phase with the system clock.
• Figure IE depicts a typical quadruple data rate data stream output from one memory bank of the current invention.
• Figure IF depicts a typical quadruple data rate data stream output from the other memory bank of the current invention.
• Figure 2A depicts the simplest embodiment of the current invention.
• Figure 2B depicts a typical system clock used in the SDR memory system.
• Figure 2(c ) depicts the SDR output onto the data bus of the prior art.
• Figure 3 A depicts a circuit diagram of the preferred embodiment of the present invention.
• Figure 3B depicts a DDR data stream of the preferred embodiment.
• Figure 3C depicts a system clock used in the preferred embodiment.
• Figure 3D depicts the output of memory bank A of the preferred embodiment.
• Figure 3E shows the delayed clock used in the preferred embodiment.
• Figure 3F depicts the output of memory bank B of the preferred embodiment.
• Figure 4A depicts a circuit diagram of an alternate embodiment of the present invention.
• Figure 4B depicts the system clock used in the alternative embodiment of the present invention.
• Figure 4C depicts the delayed clock used in the alternative embodiment of the present invention.
• Figure 4D depicts the data stream output from bank A of the alternate embodiment.
• Figure 4E depicts the data stream output from bank B of the alternate embodiment.
• Figure 5A depicts a system clock for reference in the modified DBR embodiment.
• Figure 5B depicts a DBR output.
• Figure 5(c ) depicts the output of DBR memory bank A in the modified DBR embodiment.
• Figure 5D depicts the output of DBR memory bank B in the modified DBR embodiment.
• Figure 5E depicts the data bus data stream resulting from the modified DBR embodiment.
• Figure 6 depicts a phase-locked loop (PLL).
• Figure 7 depicts a skewed PLL.
• Figure 8 depicts an embodiment utilizing currently-available DIMMs as memory banks. -
• a single bit of memory is shown * with the understanding that a typical computer memory may have 64 or 72 bits.
• the operation of the single bit may be extrapolated to include the 64 or 72 bits which make up a single memory read or write.
• a single memory chip will have 8 bits or ( more, and 8 or 9 memory chips will be required to form a single memory word. But for simplicity and clarity of the description following, a single chip, with a single bit output, will be used.
• memory chips A 100 and B 102 are enabled and they are allowed to operate with their respective clocks, clock A 104, and clock B 106, both operating at 100 MHZ.
• Clock B in this example is shifted or delayed from the other by one half period, as seen in Figure 3C.
• FET switch A 110 corresponds to memory chip A
• FET switch B i l l corresponds to memory chip B.
• the output 108 of memory chip A is connected to the input of FET switch A 110.
• FET switch A is controlled by enable signal A 112.
• the output of memory chip B is similarly switched by FET switch B 113.
• the outputs of FET switch A 116 is connected to the output of FET switch B 114.
• the two outputs are connected to a tab of the DIMM, which tab can be part of a wider Data Bus.
• a FET switch When a FET switch is enabled, the data path through the switch presents very negligible delay to the signal. When the switch is disabled, the data path is high impedance and no signal can travel through it.
• the data stream on the data bus is shown as Figure 3B.
• the clock shown in Figure 3C, has a period p equal to t3 - tl .
• FIG. 3D which shows the output of FET switch A
• FET switch A 110 is enabled at tl, and allowed to stay enabled for one half period, until t2, and then switched off until t3, the output of memory chip 1 will be connected to the data bus 114, 116 for only one-half period.
• Figure 3F which shows the output of FET switch B
• FET switch B when, at the next half period and beginning at t2, FET switch B is enabled, and allowed to remain enabled for one-half a period until t3, and then switched off for a half-period, the output of memory chip B will then be connected to the data bus 114, 116 for the other half- period.
• the data bus is connected alternately between memory chip A and memory chip B, resulting in two data bits on the data bus in each clock period p.
• the result is in accordance with the DDR standard, that is, the data rate on the bus is twice the data rate of the standard, SDR system.
• memory chips A and B operate by design at DDR speed, each producing output data at a rate equal to the basic clock rate, then by applying a clock to chip B further by X ⁇ period and applying the FET switching which maintains the data to the data bus valid for one-quarter a clock period, four data bits are passed to the data bus within one period of the clock.
• the outputs of the FET switches in this embodiment are shown in figures 1 E and IF
• Figure 1 A the system clock has a period p equal to t2-tl
• the 90 degree-phase-shifted clock applied to chip B is shown in Figure ID.
• Figure IE depicts the data output onto the data bus 114, 116 by memory chip A.
• the output 106 of memory chip A is connected to the data bus for half the period tl2-tl, while the output 107 of memory chip B is connected to the data bus starting at time tl 12, and is valid for the same half- period as the output of memory chip A.
• the interval t2-tl will be referred to as p (the period of the waveform), and the interval directly following tl, marked “1" in the figure to indicate a TRUE state of the signal, will be referred to as ⁇ t .
• the interval tl2-tl will be referred to as p/2.
• Each data bit valid duration is useful only for the required set-up and hold times of the device that receives the data. . As the silicon technology speed increases, the set up and hold times required for the data bit to be valid is decreasing. Therefore, utilizing only a portion of the data bit valid duration does not affect the reliability of the operation, but allows the enhancing of the speed significantly.
• Control lines such as RAS (Row Address Select), CAS (Column Address Select), WE (Write Enable), and CS (Chip Select) are normally[MPW5] used for operation of devices such as memory chips.
• the signals on these Control lines are normally clocked into the device by the rising edge of the 100 MHz clock. According to the first preferred embodiment of this invention, the data at the output each device is referenced to the rising edge of the clock which controls that device. [MPW6]
• a single FET is used to multiplex the output of two memory modules, rather than employing two FET switches.
• the FET switch has two inputs, each one connected to a separate memory chip output, and a single FET output connected to the data bus.
• the switching of the memory chip outputs is done by the memory chips themselves, and without the use of FET switches.
• the two SDRAM memory chips have their data output pins connected together to the DIMM board tab 130, as shown in figure 4 A. This connection can be either on a motherboard, or on a DIMM.
• Chip B 102 has its clock, shown in Figure 4(c ), shifted by one half period relative to the base clock shown in figure 4B.
• each SDRAM memory chip holds a data bit valid at the output pin 106, 107 when enabled by the corresponding output enable signals 124, 126, and revert to high impedance when not enabled.
• This type of device is referred to as a tri-state device, having an output which may be a logic one, a logic zero, and a high impedance state.
• each memory chip could be controlled to be active either at the first half of the clock cycle, or the second half, in accordance to an additional control signal.
• the outputs of both memory chips could be reduced in duration to one quarter of the period and be grouped together to be active either at the first or second half of the period as shown in figures IE and IF.
• This increase in data frequency can be accomplished internally in each SDRAM chip.
• the connection of the output of the SDRAM with the data bus is either controlled by circuitry internal to the SDRAM, or by an external output enable (OE) control line.
• OE output enable
• the SDRAM chip internal arrangement can be such that the four data bits are produced internally instead of using outside controls and connections.
• the waveform of figure 5B shows two bits from the output of a DDR chip not modified, the first data bit between tl and t2, and the second data bit between t2 and t3.
• the waveform of figure 5C shows that the two data bits are modified in duration to one quarter of the base clock period, the first data bits occurring between tl and tl2, and the second between tl2 and t2. These data bits are valid at the first half of the period only .
• the waveform of Figure 5D shows that the two DDR modified data bits are valid for the second half of the base clock period, t2:t3.
• each SDRAM memory chip Internal to each SDRAM memory chip is a controller which contains a data receiver. When data is transmitted into this receiver, it must be synchronized with the basic system clock, as in Figure 5 A. In order to accomplish the clocking of the data into a receiver of the controller, several methods can be employed. If the data stream of the waveform of Figure 5E is generated by the SDRAMs, a clock of the same waveform can be produced internal to the SDRAMs. This clock can be used by the controller of each SDRAM to latch up the data into its own registers for processing.
• the first memory bank will be made up of an array of memory chips which constitute the first bank
• the second memory bank will be made up of an array of memory chips which constitute the second bank.
• memory banks A and B are both DDR memories.
• the same basic clock signal is used to synchronize both memory bank A and memory bank B.
• memory bank A produces a first internal output which is valid for a duration p/4 of the basic clock cycle, and a second internal output at p/2 after the beginning of the cycle, again lasting for a duration p/4.
• Memory bank B produces a third internal output, beginning at p/4 after the beginning of the cycle, which is valid for a duration p/4 of the basic clock cycle, and a fourth internal output, again at
• the first and second internal outputs are exchanged, and the third and fourth internal outputs are exchanged.
• the data on the data bus will contain the data bits from memory chip A during the first half of the clock period, and from memory chip B during the second half of the clock period.
• the main clock feeding the memory module is phase shifted or delayed by one half period, 180 degrees, or one quarter period, 90 degrees, depending upon the specific embodiment.
• one method of generating the delayed clock signal is the use of a clock driver or Phase Locked Loop (PLL) with multiple outputs of the same phase in order to drive several SDRAM chips with small capacitive loading.
• PLL Phase Locked Loop
• the PLL has an input 140, and output 148, with a time delay dtl inherent between the output of the PLL and the load (not shown).
• a feedback signal 146 has the identical delay dtl . As a result, the output will be phase locked to the signal as seen at the load.
• Skewed drivers are defined as those with a single input, and two or more outputs, with each output having a different phase angle, or delay, relative to the input.
• a variation of the PLL is the skewed PLL, shown in Figure 7.
• the skewed PLL has input 152, and two separate outputs 156 and 158.
• the skewed PLL has a phase delay between the outputs 156 and 158, which may be used to drive multiple clocks required by this invention. Because of the ability to phase synchronize the incoming clock with the PLL outputs, any PLL output can be used to generate the delayed clock or phase shifted clock.
• phase shift, or delay of the PLL may be created in a number of ways.
• the PLL may contain a delay internal to the PLL, so that the output will be automatically delayed relative to the input. Or, alternatively, a delay line or circuit may be inserted in series between two PLL circuits, creating a cascaded PLL delay circuit.
• One proposed method is to use the clock generated by the DIMM to drive the first bank of SDRAMs . If the clock delay is done on the DIMM, a printed wire length is incorporated to accurately give the required delay to generate a shifted clock. This shifted clock is then used to drive a second PLL.
• the output of the second PLL is the delayed clock used to drive the second of the two banks of SDRAMs.
• the wire length required is determined via simulation, theoretical, and trial and error methods.
• the DIMM uses a delayed clock also located on the motherboard, to drive the PLL, located on the DIMM.
• the outputs of the PLL will drive the SDRAM chips of the bank.
• the techniques just described may be used to increase the memory speed using existing DIMMs.
• the system may be understood by referring now to Figure 8.
• all of the components shown are mounted on the motherboard, with DIMM modules inserted into DIMM connectors 166, 168, 182, and 184.
• the DIMM modules themselves become memory banks.
• the DIMMs inserted into DIMM connector 166 and 168 form the equivalent of a first and second memory bank, respectively.
• the data 172 to and from the first DIMM, in connector 166 is switched on and off the data bus by FET switch 160.
• the data 170 is switched to and from the second DIMM, mounted in DIMM connector 168, by the same FET switch 160.
• the Phase Locked Loop Phase shift doubler produces clock signals 174 and 176, which are in quadrature with respect to each other, to enable the first DIMM, and then the second DIMM.
• Enable signal 180 generated by the PLL circuit 164, generates signals analogous to FET EN A 112 and FET EN B 113 of Figure 3 A, alternately enabling the first DIMM and the second DIMM in the current embodiment.
• Figure 8 also shows a second set of DIMM connectors 182, 184, in which a third and fourth memory bank is created by the insertion of two more DIMMs.
• These two additional DIMMs operated in exactly the same manner as the first and second DIMMs, having their own FET switch 178, quadrature clock signals 190 and 192, etc.
• DDR DIMM serving the function of the DDR data bank in the previous embodiments.
• This embodiment has the advantage of using DIMMs in their currently available forms, thus requiring only the manufacture of a motherboard to enjoy the advantages in speed and access time of the current invention.

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• 2000
  • 2000-05-17 US US09/572,641 patent/US6446158B1/en not_active Expired - Lifetime
• 2001
  • 2001-05-15 WO PCT/US2001/015592 patent/WO2001088714A1/en not_active Ceased
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