WO2001065601A2 - Vorrichtung zum verpacken elektronischer bauteile mittels spritzgusstechnik - Google Patents
Vorrichtung zum verpacken elektronischer bauteile mittels spritzgusstechnik Download PDFInfo
- Publication number
- WO2001065601A2 WO2001065601A2 PCT/DE2001/000778 DE0100778W WO0165601A2 WO 2001065601 A2 WO2001065601 A2 WO 2001065601A2 DE 0100778 W DE0100778 W DE 0100778W WO 0165601 A2 WO0165601 A2 WO 0165601A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- ceramic substrate
- ceramic
- metal layer
- ductile
- substrate
- Prior art date
Links
- 238000001746 injection moulding Methods 0.000 title claims abstract description 41
- 238000005516 engineering process Methods 0.000 title claims abstract description 11
- 238000012856 packing Methods 0.000 title abstract 2
- 239000000919 ceramic Substances 0.000 claims abstract description 123
- 239000000758 substrate Substances 0.000 claims abstract description 120
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 55
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 238000004806 packaging method and process Methods 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 13
- 150000001875 compounds Chemical class 0.000 claims description 12
- 229910000679 solder Inorganic materials 0.000 claims description 9
- 239000006112 glass ceramic composition Substances 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000010137 moulding (plastic) Methods 0.000 claims description 6
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 5
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 239000002245 particle Substances 0.000 claims description 5
- 229910052839 forsterite Inorganic materials 0.000 claims description 4
- HCWCAKKEBCNQJP-UHFFFAOYSA-N magnesium orthosilicate Chemical compound [Mg+2].[Mg+2].[O-][Si]([O-])([O-])[O-] HCWCAKKEBCNQJP-UHFFFAOYSA-N 0.000 claims description 4
- 238000005476 soldering Methods 0.000 claims description 4
- 229910000838 Al alloy Inorganic materials 0.000 claims description 3
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims description 2
- 238000003825 pressing Methods 0.000 claims description 2
- 238000007792 addition Methods 0.000 claims 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 2
- 229910001141 Ductile iron Inorganic materials 0.000 claims 1
- 229910052593 corundum Inorganic materials 0.000 claims 1
- 229910001845 yogo sapphire Inorganic materials 0.000 claims 1
- 230000008569 process Effects 0.000 description 19
- 230000008901 benefit Effects 0.000 description 12
- 239000004033 plastic Substances 0.000 description 12
- 238000005266 casting Methods 0.000 description 8
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical class O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 238000007789 sealing Methods 0.000 description 4
- 239000004593 Epoxy Substances 0.000 description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N Magnesium oxide Chemical compound [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 3
- 239000003365 glass fiber Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- ANVAOWXLWRTKGA-NTXLUARGSA-N (6'R)-beta,epsilon-carotene Chemical compound CC=1CCCC(C)(C)C=1\C=C\C(\C)=C\C=C\C(\C)=C\C=C\C=C(/C)\C=C\C=C(/C)\C=C\[C@H]1C(C)=CCCC1(C)C ANVAOWXLWRTKGA-NTXLUARGSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 235000002017 Zea mays subsp mays Nutrition 0.000 description 2
- 241000482268 Zea mays subsp. mays Species 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- RKTYLMNFRDHKIL-UHFFFAOYSA-N copper;5,10,15,20-tetraphenylporphyrin-22,24-diide Chemical compound [Cu+2].C1=CC(C(=C2C=CC([N-]2)=C(C=2C=CC=CC=2)C=2C=CC(N=2)=C(C=2C=CC=CC=2)C2=CC=C3[N-]2)C=2C=CC=CC=2)=NC1=C3C1=CC=CC=C1 RKTYLMNFRDHKIL-UHFFFAOYSA-N 0.000 description 2
- 239000002241 glass-ceramic Substances 0.000 description 2
- 239000000395 magnesium oxide Substances 0.000 description 2
- 229910052574 oxide ceramic Inorganic materials 0.000 description 2
- 239000011224 oxide ceramic Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- XRWSZZJLZRKHHD-WVWIJVSJSA-N asunaprevir Chemical compound O=C([C@@H]1C[C@H](CN1C(=O)[C@@H](NC(=O)OC(C)(C)C)C(C)(C)C)OC1=NC=C(C2=CC=C(Cl)C=C21)OC)N[C@]1(C(=O)NS(=O)(=O)C2CC2)C[C@H]1C=C XRWSZZJLZRKHHD-WVWIJVSJSA-N 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229940125961 compound 24 Drugs 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000003966 growth inhibitor Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000004413 injection moulding compound Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000004816 latex Substances 0.000 description 1
- 229920000126 latex Polymers 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000010327 methods by industry Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/4809—Loop shape
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- H01L2224/732—Location after the connecting process
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Definitions
- the invention relates to a device for packaging electronic components by means of injection molding technology and a method for packaging electronic components using this device.
- Devices of this type for packaging electronic components are used in CSP technology (chip size packaging) in order to cast a large number of electronic components on a first side of an intermediate carrier with a plastic casting compound.
- the multiplicity of components are arranged on a first side of an intermediate carrier in predetermined positions, and the intermediate carrier has conductor tracks, contact connection surfaces for connecting to microscopic contact surfaces of the electronic components and through contacts which are connected to conductor tracks on a second side of the intermediate carrier, wherein on this second side at predetermined locations contact outer connection surfaces or contact stools are attached.
- the second side is arranged opposite the first side of the intermediate carrier.
- the intermediate carrier is made of a glass fiber-reinforced epoxy substrate if these components are designed for high-frequency or logic applications.
- the entire device is sealed with plastic by means of an injection molding process.
- This injection molding process is standardized as the "transfer molding process”.
- the intermediate carrier must withstand high loads because an injection mold and the intermediate Carrier of the device for sealing the joint between the injection mold and the intermediate carrier are clamped together. A high contact pressure acts on the edges of the intermediate carrier so that no plastic casting compound emerges between the intermediate carrier and the injection molding tool.
- the object of the invention is to provide a device which overcomes the disadvantages in the prior art and makes it possible to package electronic components mounted on intermediate carriers made of ceramic using a highly automated injection molding process. It is also an object of the invention to provide a method for packaging electronic components using an appropriate device.
- the intermediate carrier is a ceramic substrate which, in its edge regions on the first side, on which the electronic components are also arranged, has a ductile, annularly arranged metal layer.
- a ductile metal layer it is achieved that an injection molding tool can be incorporated into the edge regions of the ceramic substrate and can seal the edge regions, unevenness of the ceramic substrate being compensated for.
- the edge area with the ductile metal layer can advantageously be easily canceled after the injection molding when the device for packaging electronic components is separated.
- the plastic casting compound is injected at a high temperature of approximately 180 ° C. and at a high pressure of approximately 8 MPa m into a cavity placed on the intermediate carrier of the device.
- the injection molding tool with the cavity forming a plastic housing must be placed on the intermediate carrier with great force in order to compensate for deflections and small amounts of the intermediate carrier which would lead to leaks or an escape of the plastic molding compound from the cavity.
- Due to the ductile metal layer the high stresses that occur can no longer lead to the breakage of the typically brittle ceramic, since the ductile metal plastically deforms and the stresses are relieved.
- the popcorn effect is avoided by using a ceramic substrate. Although ceramic substrate materials have great hardness and rigidity, the ductile metal layer prevents high wear on the injection molding tools, which makes the highly automated standard process cheaper.
- the metallic caps used in the case of ceramic substrates to protect the electronic components or liquid epoxy resin materials in a casting mold, which is individual for each component or for component groups are used, are dispensed with and CSP and MCP components (multichip package) with ceramic substrates are cast economically in plastic.
- the device provides the advantage that higher structural densities can be achieved with the intermediate carrier made of a ceramic substrate by means of narrower conductor tracks, smaller contacts and improved electrical designs.
- the "popcorn effect" is completely avoided, and there is no damage caused by evaporation of adsorbed water molecules in porous plastic substrates, for example when later attaching contact outer connection surfaces or soldering in contact stools.
- the ceramic substrate has the advantage of improved heat dissipation through the substrate for the electronic components, so that additional cooling devices can be saved.
- the ceramic substrate provides the possibility of realizing multilayer components with integrated passive structures such as resistors, inductors and capacitors in the ceramic substrate between appropriately prepared ceramic layers.
- the ring-shaped metal layer forms a closed metal ring.
- the advantage of this closed metal ring is the reliability with which an annular seal between the Ceramic substrate and injection molding tool can be achieved while injecting the plastic molding compound.
- the ring-shaped metal layer has interruptions.
- interruptions are so narrow that when the plastic compound is injected, it solidifies within the interruptions. This has the advantage that a more favorable distribution of the stresses caused by different expansion of the substrate and metal layer can be achieved.
- the interruptions can be arranged in such a way that the ring-shaped metal layer consists of a plurality of directly lined-up metal strips which are aligned transversely to the ring-shaped arrangement.
- the contact stools protruding from the second side of the ceramic substrate are made from solder balls, these solder balls being applied to the second side of the ceramic substrate only after the electronic components have been injection-molded in m positions.
- the ceramic substrate is a multilayer substrate, the layers of which have different coefficients of thermal expansion, a central inner ceramic layer having a higher coefficient of thermal expansion than the adjacent outer layers.
- the ductile metal layer according to the invention is arranged in the mounting area of an injection molding tool defining the housing shape, so that the injection molding tool advantageously does not directly touch the hard ceramic substrate and thus wears less than in the case of conventional ceramic substrates, since it does not work with the ceramic substrate , but is only in contact with the ductile metal layer, which is associated with a longer service life of the injection molding tool.
- a ductile metal layer which is also supposed to have a sealing effect, must be dimensioned sufficiently thick. However, this entails the risk that the ceramic substrate will be distorted when the metal layer is applied.
- the ceramic substrate is additionally provided with a ductile, closed metal layer arranged in a ring in its edge regions on the second side.
- the ceramic substrate can additionally have an annularly arranged groove in its edge regions on the second side. This groove lies within the attachment area of the injection molding tool and thus advantageously reduces the stresses in the inner area of the active electronic semiconductor structures. Although the local stresses in the area of the groove itself increase, the groove ensures that stress cracks in the ceramic occur only in the edge area and not in the usable area for the electronic components.
- a fine-grained A1 2 0 3 with a purity> 96% is used as the material for the ceramic substrate.
- This aluminum oxide is because of the combination of good electrical and mechanical properties as well as its relatively cheap Price and its availability, the most suitable ceramic substrate material for the device for packaging electronic components according to the invention.
- the Al 2 0 3 is available relatively inexpensively in the standard dimensions that are also used for thin-film technology.
- the modulus of elasticity of the A1 2 0 3 is relatively high, as a result of which high stresses are induced in the ceramic substrate during injection molding, this can be accepted because of the high strength of the material.
- voltage peaks can be reduced further, as mentioned above, by appropriate multilayering of the substrate and in particular by the groove preferably provided on the second side of the ceramic substrate.
- the fine grain of the ceramic can be improved by adding MgO to the A1 2 0 3 , since magnesium oxide acts as a grain growth inhibitor in Al 2 0 3 ceramics and thus it is avoided that the grain growth is too large and the inhomogeneities in the ceramic substrate are too large due to abnormal grain growth form.
- the mechanism known and typical for partially stabilized Zr0 2 ceramics can also be transferred to aluminum oxide ceramics.
- the microstructure of the Zr0 2 particles is adjusted by suitable process engineering measures so that they take on a metastable tetragonal phase not only monoclinically, but also at room temperature. This tetragonal phase of the Zr0 2 only changes under the influence of stress fields in the vicinity of a crack tip into the stable monoclinic phase. This is associated with an increase in volume, which generates compressive stress, which locally prevents the tensile stress field responsible for crack propagation and thus prevents crack propagation in an aluminum oxide ceramic with embedded Zr0 2 particles.
- the ceramic substrate is made from fine-grained steatite and / or forsterite. Due to the molecular structure of steatites and Forsterite's thermal conductivity is lower than that of aluminum oxide, but at the same time its modulus of elasticity is low, so that these materials seem perfectly suitable for the injection molding of housings in the highly automated process.
- Fine-grained aluminum nitride can also be used as the ceramic substrate, especially since aluminum nitride achieves a high thermal conductivity and the mechanical properties are comparable to those of aluminum oxide.
- the low thermal expansion coefficient which is closer to semiconductor silicon for aluminum nitride, can be an additional advantage for some applications.
- the coefficient of thermal expansion of the ceramic substrate was of the order of magnitude
- Plastic injection molding compound is used to minimize warping and warping of the ceramic substrate.
- glass ceramic materials as the ceramic substrate.
- glass ceramic materials In addition to a ceramic component, for example made of aluminum oxide, such glass ceramic materials have a glass component.
- the proportion of glass in low-temperature glass ceramic materials is higher than in high-temperature glass ceramic materials.
- Such low-temperature glass ceramic materials can be sintered between 850 and 1000 ° C because of the larger glass content at correspondingly lower temperatures.
- these material systems based on glass ceramic materials offer the advantage that the substrate properties can be tailored for the device for packaging electronic components by the optimized composition from the mixing ratio of the glass and ceramic components.
- the coefficient of expansion of the glass ceramic can be matched to the coefficient of expansion of the plastic casting compound, which means greater resistance to cyclic ones Temperature changes compared to pure Al 2 0 ceramics can be achieved.
- a ceramic substrate with conductor tracks, contact connection areas and through contacts for attaching contact stools at predetermined positions which has a ductile metal layer in its edge regions and carries electronic components within the ductile metal layer, providing a housing mold-forming injection molding tool, sealingly pressing the injection mold onto the ductile elements ring-shaped metal layer in the edge area of the ceramic substrate, injection of a plastic molding compound into the cavity between the injection mold and a component-carrying first side of the ceramic substrate,
- This method has the advantage that now may be encapsulated by means of a highly automated standard process, namely the sogenann ⁇ th Transfermoldens, electronic components on ceramic miksubstraten with an injection molding mass.
- This makes it possible, compared to the previous technology, in which only glass fiber reinforced epoxy or polyamide substrate materials are used due to the high temperature and pressure load of the substrates, now due to the structuring according to the invention of the ceramic substrate, in particular with a ductile metal layer in the edge regions of the substrate, an injection molding tool sealing on ceramic sub- ⁇ ⁇ rO IV ) I - 1 P 1
- the high process pressures in the injection molding process is reduced, since compressive stresses are induced in the adjacent outer layers when the ceramic substrates cool after sintering, so that the risk of cracking under tensile stresses during the injection process and the further thermal aftertreatments is reduced.
- a multilayer substrate is used as the ceramic substrate, the layers of which have different moduli of elasticity, a central inner ceramic layer having a higher modulus of elasticity than the adjacent outer layers.
- a similar effect can be achieved by incorporating structured metal layers when the ceramic substrate is built up, so that the metal layers contribute to the reduction of internal stresses.
- Ceramic substrates which are multilayered can also be used for the method according to the invention, wherein in addition to the ceramic layers there are structured metal layers in the substrate which take on the conductor track functions and functions of passive components.
- through-contacts are selectively provided in the different ceramic layers in this multi-layer ceramic substrate, glass ceramics also being used as the ceramic substrate or ceramic layers.
- a plating technique is used in which the ductile material is applied in the form of a strip.
- Other preferred metal coating processes are the screen printing process and the stencil printing process, which have the advantage that a high number of ceramic substrates can be covered with metal layers in an automated process.
- a ductile copper alloy is used for the ductile ring-shaped metal layer, a direct one can be used
- DCB process Copper bonds are used (DCB process), which is particularly applicable for aluminum oxide substrates.
- a ductile aluminum alloy is used as the ductile, closed metal layer, which has the advantage that particularly soft metal layers can be realized with it.
- Iron / nickel alloys can also be used as the ductile, closed, metal layer, which has the particular advantage that no metal residues accumulate on the injection molding tool, as could possibly occur with very soft aluminum alloys.
- Another process variant for applying the ductile metal layer is active soldering, in which a lamination with an additive that reacts with the ceramic is soldered on.
- Another exemplary embodiment of the method according to the invention consists in that an additional ductile ring-shaped metal layer is applied to the ceramic substrate in its edge regions on the second side.
- This method step advantageously compensates for any distortion of the first side by the ductile metal layer arranged there in a ring.
- an annularly closed groove can be worked into the edge areas of the ceramic substrate on the second side.
- This method step ensures that a predetermined breaking point is created in the edge area, which prevents cracks from continuing from the edge area into the central central area of a ceramic substrate.
- Materials for the ceramic substrate have already been discussed in detail above, and the advantages associated therewith are also transferable to the corresponding method steps, so that they are not discussed further here.
- FIG. 2 shows a section of a partially cross-sectional view of a device according to an embodiment of the invention with an injection molding tool attached.
- FIG. 3 shows a further embodiment of the invention with an injection molding tool attached.
- FIG. 4 shows a separation of an edge area after the packaging of the electronic components and the melting of solder balls into contact stools in predetermined positions on a ceramic substrate.
- FIG. 1 a shows a perspective view of an apparatus for packaging electronic components 1 by means of latex casting technology in accordance with an embodiment of the invention.
- a large number of components 1 are arranged on a first side 2 of a ceramic substrate 11 in predetermined positions 4.
- the ceramic substrate 11 has the conductor tracks 5, contact areas 6 and through contacts 8 shown in FIG. 4, wherein in this embodiment of the invention m the edge regions 12 of the ceramic substrate 11 on the first side 2 a ductile metal layer 13 arranged in a ring and on the second side 10, an opposite ductile metal layer 21 are arranged.
- N 02 d rt od P- ⁇ PJ d Ph ⁇ P- rt PJ: ⁇ P- X P- C ⁇ PJ d ⁇ ⁇ ⁇ zd ⁇ dd tr 3 rt P- d £ C ⁇ P>: P ) O P- cn ⁇ P- O P- cn O ⁇ dd rt £ d
- FIG. 4 shows the separation by means of a saw blade 28 of the width b of the edge area 12 after the packaging of the electronic components 1 and the melting of solder balls 30 into contact stools 9 m in the predetermined positions.
- the injection molding tool has already been removed in this illustration of FIG. 4 and the plastic molding compound 24 has cooled and solidified, so that it forms a protective housing for the electronic component 1.
- the plastic molding compound penetrates all cavities during the injection molding process and forms an insulating layer between conductive components. As FIG.
- the integrated circuit (not shown) of a semiconductor chip of the electronic component 1 is, via the contact area 7 on the semiconductor chip, a bond wire connection 27 and a contact connection area 6 on the ceramic substrate and a conductor track 2 on the first side of the ceramic substrate via a via 8 is connected to the conductor track 6 on the second side 10 of the intermediate carrier 3 or the ceramic substrate for rewiring, a solder contact area in the end region 31 of the conductor track 6 receiving a contact stool on the second side 10 of the ceramic substrate 11.
- This contact stool 9 is formed by melting a solder ball 30 on the solder contact surface 29.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01919152A EP1259986A2 (de) | 2000-03-03 | 2001-03-02 | Vorrichtung zum verpacken elektronischer bauteile mittels spritzgusstechnik |
JP2001564393A JP3847166B2 (ja) | 2000-03-03 | 2001-03-02 | 射出成形技術を用いて電子部品をパッケージングするデバイス |
US10/220,752 US7215010B2 (en) | 2000-03-03 | 2001-03-02 | Device for packing electronic components using injection molding technology |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10010461.4 | 2000-03-03 | ||
DE2000110461 DE10010461A1 (de) | 2000-03-03 | 2000-03-03 | Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2001065601A2 true WO2001065601A2 (de) | 2001-09-07 |
WO2001065601A3 WO2001065601A3 (de) | 2002-06-20 |
Family
ID=7633423
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/DE2001/000778 WO2001065601A2 (de) | 2000-03-03 | 2001-03-02 | Vorrichtung zum verpacken elektronischer bauteile mittels spritzgusstechnik |
Country Status (5)
Country | Link |
---|---|
US (1) | US7215010B2 (de) |
EP (1) | EP1259986A2 (de) |
JP (2) | JP3847166B2 (de) |
DE (1) | DE10010461A1 (de) |
WO (1) | WO2001065601A2 (de) |
Families Citing this family (14)
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DE10317596A1 (de) * | 2003-04-16 | 2004-11-11 | Epcos Ag | Verfahren zur Erzeugung von Lotkugeln auf einem elektrischen Bauelement |
US20060043635A1 (en) * | 2003-10-31 | 2006-03-02 | Groth Lauren A | Singular and co-molded pre-forms |
US7224040B2 (en) * | 2003-11-28 | 2007-05-29 | Gennum Corporation | Multi-level thin film capacitor on a ceramic substrate |
DE102007017855A1 (de) | 2007-04-16 | 2008-10-23 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines optoelektronischen Bauelementes und optoelektronisches Bauelement |
US20090126967A1 (en) * | 2007-11-16 | 2009-05-21 | Continental Automotive Systems Us, Inc. | Thermal packaging of transmission controller using carbon composite printed circuit board material |
JP5481854B2 (ja) * | 2008-12-16 | 2014-04-23 | Tdk株式会社 | 電子部品 |
JP5514559B2 (ja) * | 2010-01-12 | 2014-06-04 | 新光電気工業株式会社 | 配線基板及びその製造方法並びに半導体パッケージ |
JP5469546B2 (ja) | 2010-06-22 | 2014-04-16 | 株式会社ジェイデバイス | 半導体装置の製造方法 |
JP5606243B2 (ja) | 2010-09-24 | 2014-10-15 | 株式会社ジェイデバイス | 半導体装置の製造方法 |
CN104123179A (zh) | 2013-04-29 | 2014-10-29 | 敦南科技股份有限公司 | 中断控制方法及其电子系统 |
EP2799964A3 (de) * | 2013-04-29 | 2017-04-26 | Dyna Image Corporation | Bewegungssensor und Verpackungsverfahren dafür |
JP6365360B2 (ja) * | 2015-03-12 | 2018-08-01 | 株式会社デンソー | 電子装置及びその製造方法 |
EP3588547A4 (de) * | 2017-02-20 | 2020-08-19 | Shindengen Electric Manufacturing Co. Ltd. | Elektronische vorrichtung |
WO2020121680A1 (ja) * | 2018-12-10 | 2020-06-18 | 富士電機株式会社 | 半導体装置 |
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Also Published As
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---|---|
US7215010B2 (en) | 2007-05-08 |
JP2003526208A (ja) | 2003-09-02 |
WO2001065601A3 (de) | 2002-06-20 |
EP1259986A2 (de) | 2002-11-27 |
US20030178747A1 (en) | 2003-09-25 |
DE10010461A1 (de) | 2001-09-13 |
JP2005354095A (ja) | 2005-12-22 |
JP3847166B2 (ja) | 2006-11-15 |
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