WO2001014972A1 - Appareil destine a surveiller un dispositif a memoire lsi - Google Patents

Appareil destine a surveiller un dispositif a memoire lsi Download PDF

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Publication number
WO2001014972A1
WO2001014972A1 PCT/JP1999/004484 JP9904484W WO0114972A1 WO 2001014972 A1 WO2001014972 A1 WO 2001014972A1 JP 9904484 W JP9904484 W JP 9904484W WO 0114972 A1 WO0114972 A1 WO 0114972A1
Authority
WO
WIPO (PCT)
Prior art keywords
storage element
additional information
internal block
access
cpu
Prior art date
Application number
PCT/JP1999/004484
Other languages
English (en)
Japanese (ja)
Inventor
Yasushi Imamura
Takao Inoue
Original Assignee
Matsushita Electric Industrial Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP10043226A priority Critical patent/JPH11242637A/ja
Application filed by Matsushita Electric Industrial Co., Ltd. filed Critical Matsushita Electric Industrial Co., Ltd.
Priority to KR1020017004768A priority patent/KR20010106519A/ko
Priority to PCT/JP1999/004484 priority patent/WO2001014972A1/fr
Publication of WO2001014972A1 publication Critical patent/WO2001014972A1/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details

Definitions

  • the present invention relates to a monitoring device for a storage element in a system (hereinafter, referred to as LSI) constituted by large-scale integrated circuits.
  • LSI monitoring device for a storage element in a system
  • FIG. 4 shows a block diagram of a conventional LSI storage element monitoring device 400.
  • the access request is arbitrated by the bus arbiter 42 and the access to the storage element 41 is performed.
  • the internal block groups 43, 44, 45 or the CPU 46 outputs an access request for reading data or an access request for writing data to the storage element 41 to the path arbiter 42.
  • the bus arbiter 42 arbitrates an access request to the storage element 41 from the internal block group 43, 44, 45 or the CPU 46, and, based on the priority order for the access request, any one of the internal block groups 43, 44, 45 or the CPU 46. Accept the access request.
  • the bus arbiter 42 accesses the storage element 41 according to the received access request.
  • the storage element 41 is inside or outside the LSI 40 and is accessed by the bus arbiter 42.
  • the CPU 46 outputs a data read access request to the storage element 41 to the path arbiter 42, and the data of the storage element 41 is read by the bus arbiter 42, whereby the storage element 41 is read. It is possible to observe the contents stored in the CPU 46 from the CPU 46.
  • the contents stored in the storage element 41 can be observed from the CPU 46 in system debugging when the actual system including the target LSI 40 malfunctions.
  • an object of the present invention is to store the additional information at the time of accessing a storage element, so that the history of the target LSI accessing the storage element can be observed from a CPU in system debugging. . Disclosure of the invention
  • An LSI storage element monitoring device includes a storage element, a bus arbiter connected to the storage element, a CPU capable of accessing the storage element via the bus arbiter, and an access to the storage element via the bus arbiter.
  • the CPU stores the additional information stored in the additional information dedicated area in response to the trigger signal. Observation, thereby achieving the above objectives.
  • the additional information may include information indicating a write Z read attribute to the storage element and information specifying the internal block circuit that has accessed the storage element last.
  • the additional information may include count information that is incremented each time the internal block circuit accesses the storage element.
  • the additional information may include time information indicating a time when the internal block circuit accesses the storage element.
  • the additional information of the access history is stored on the storage element in the integrated circuit.
  • system debugging may cause the malfunction. This makes it easier to find unexpected accesses to the same storage device, making system debugging easier.
  • the number of times of access to the storage element and the access point can be measured, and the access performance evaluation during debugging is facilitated.
  • FIG. 1 is a block diagram of an LSI storage element monitoring device according to an embodiment of the present invention.
  • FIG. 2 is a diagram schematically showing the internal configuration of the storage element of the LSI storage element monitoring device according to the embodiment of the present invention.
  • FIG. 3 is a diagram for explaining a data configuration of additional information in the storage element of the LSI storage element monitoring device according to the embodiment of the present invention.
  • FIG. 4 is a block diagram of a conventional LSI storage element monitoring device. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a block diagram of the LSI storage element monitoring device 100 according to the present invention
  • FIG. 2 is an internal configuration diagram of the storage element 11 according to the present invention.
  • the basic access method in the present invention is the same as the conventional one, When an access request to the storage element 11 is issued from 14, 15 or the CPU 16, the access request is arbitrated by the bus arbiter 12, and the storage element 11 is accessed.
  • the storage element 11 is, for example, a storage element such as a DRAM, which is inside or outside the LSI 10.
  • the LSI 10 differs from the conventional configuration in that an additional information dedicated area 11 A is provided inside the storage element 11, an additional information generation unit 17 for generating operation information of the storage element 11, and a storage element 1. The point is that a trigger generator 18 for stopping access to 1 is provided.
  • the storage element 11 has a conventional area 11B (shaded area) required by the LSI 10 for actual operation, and an area dedicated to additional information of m bits per m bits. It has an internal structure with 1 1 A.
  • the internal block groups 13, 14, 15 or the CPU 16 outputs an access request for reading data or an access request for writing data to the storage element 11 to the bus arbiter 12.
  • the bus arbiter 12 arbitrates an access request to the storage element 11 from the internal block group 13, 14, 15 or the CPU 16 and, based on the priority for the access request, any one of the internal block groups 13, 14, 15 Or, the access request of CPU 16 is accepted.
  • Bus arbiter 12 accesses storage element 11 according to the received access request.
  • the additional information generation unit 17 switches the content of the additional information to be stored from the outside or from the CPU 16 or performs the ⁇ NZOFF control of writing according to the control signal 19 from the outside or the control signal 20 from the CPU 16.
  • the trigger generation unit 18 When the event signal 21, the internal event signal 22, or the external event signal 23 from the CPU 16 is generated, the trigger generation unit 18 generates a control signal 24 for stopping the access request of the internal block groups 13, 14, 15.
  • the LSI storage element monitoring apparatus 100 having such a configuration, since the additional information can be stored in the storage element 11, the event signal 21, the internal event signal 22, or the external event signal 23 from the CPU 16 is generated. Trigger The access to the storage element 11 by the internal block groups 13, 14, 15 can be stopped by the section 18, and the contents stored in the storage element 11 can be observed from the CPU 16. According to the conventional configuration, the content of the storage element 11 observed from the CPU 16 is only n-bit data, but according to the configuration of the present invention, it is n-bit data. In addition, m bits of additional information can be observed.
  • the read Z write attribute is stored in bit 0 of the 4-bit additional information. That is, 0 is stored when a read access occurs, and 1 is stored when a write access occurs.
  • Bits 1 to 3 store the code representing the last accessed CPU or internal block. In other words, if the CPU 16 accesses and stores it, it stores 0000, if the internal block (1) accesses it, stores 001, and if the internal block (7) accesses it, it stores 1 1 1 Will be.
  • system debugging can be efficiently performed by the following procedure.
  • the bus arbiter 12 stores the read Z write attribute and the last accessed block shown in FIG. 3 in the storage element 11 as additional information.
  • a debug operation is started by an event signal indicating that a predetermined address of the storage element 11 is accessed by a predetermined internal block.
  • the access to the storage element 11 by the internal block groups 13, 14, and 15 is stopped by the trigger generator 18, and the data is stored in the storage element 11 immediately before the event occurs.
  • the additional information can be observed from the CPU 16. By observing the additional information from CPU 16, the maximum This has the effect of knowing the block to which read or write access was performed later and determining the validity of the access.
  • the pass virter 12 accesses the storage element 11 and at the same time, adds a coded numerical value from the counter value incremented for each access or time information
  • the information is stored in the storage element 11 as information.
  • the numerical value coded from the time information is, for example, a numerical value obtained by coding the time as 1 3 5 8 3 2 if the time is 1:58:32 pm . Then, as described above, the debugging operation is started.
  • the access order to the storage element 11 is known by comparing the value of the additional information stored in the storage element 11 from the CPU 16. be able to. By knowing the access order that contributes to the access speed to the storage element 11, the access performance to the storage element 11 can be evaluated. For example, when a DRAM having a page mode is used as the storage element 11, access to the same page can be efficiently continued to confirm whether or not the speed has been improved. You can see the 2 priority arbitration function.
  • the path arbiter 12 accesses the storage element 11 and simultaneously increments the number of accesses stored in the additional information of the corresponding address with a new value. It is stored in the storage element 11 as additional information. Then, during the debug operation, during the debug operation, the number of accesses of each address stored in the memory element 11 can be observed from the CPU 16, so that a redundant access that degrades the access performance to the memory element 11 is found. To the storage element 11 from the CPU 16 which is difficult to measure from the program procedure of the CPU 16 The number of accesses can be measured.
  • the target LSI accesses the storage element during system debugging when the actual system including the target LSI malfunctions, by simply adding a simple circuit configuration.
  • the CPU can monitor the history of data storage and the history of access to storage elements by a specific internal block in the target LSI, and can detect unexpected accesses to memory elements that can cause malfunctions. This has the effect of facilitating system debugging.

Landscapes

  • Debugging And Monitoring (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

L'invention concerne un moniteur de stockage à intégration à grande échelle (LSI), qui comporte une mémoire, un arbitre de bus relié à la mémoire, une UC capable d'accéder à la mémoire par l'intermédiaire de l'arbitre de bus, plusieurs circuits blocs internes capables d'accéder à la mémoire par l'intermédiaire de l'arbitre de bus, des moyens de génération d'informations conçus pour générer des informations additionnelles, et des moyens de génération de déclenchement conçus pour générer un signal de déclenchement destiné à empêcher les circuits blocs internes d'accéder à la mémoire, sur la base d'un état de déclenchement prédéterminé. La mémoire comporte une zone consacrée au stockage d'informations additionnelles. L'arbitre de bus permet que des informations additionnelles soient stockées dans ladite zone consacrée. En réponse au signal de déclenchement, l'UC conserve les informations additionnelles stockées dans ladite zone consacrée.
PCT/JP1999/004484 1998-02-25 1999-08-20 Appareil destine a surveiller un dispositif a memoire lsi WO2001014972A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP10043226A JPH11242637A (ja) 1998-02-25 1998-02-25 Ｌｓｉ記憶素子監視装置
KR1020017004768A KR20010106519A (ko) 1999-08-20 1999-08-20 Ｌｓｉ 기억 장치 모니터링 장치
PCT/JP1999/004484 WO2001014972A1 (fr) 1998-02-25 1999-08-20 Appareil destine a surveiller un dispositif a memoire lsi

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10043226A JPH11242637A (ja) 1998-02-25 1998-02-25 Ｌｓｉ記憶素子監視装置
PCT/JP1999/004484 WO2001014972A1 (fr) 1998-02-25 1999-08-20 Appareil destine a surveiller un dispositif a memoire lsi

Publications (1)

Publication Number Publication Date
WO2001014972A1 true WO2001014972A1 (fr) 2001-03-01

Family

ID=26382976

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1999/004484 WO2001014972A1 (fr) 1998-02-25 1999-08-20 Appareil destine a surveiller un dispositif a memoire lsi

Country Status (2)

Country Link
JP (1) JPH11242637A (fr)
WO (1) WO2001014972A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3202700B2 (ja) * 1998-10-20 2001-08-27 松下電器産業株式会社 信号処理装置
JP5850724B2 (ja) * 2011-12-02 2016-02-03 キヤノン株式会社 データ処理装置およびその制御方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045853A (ja) * 1983-08-22 1985-03-12 Fujitsu Ltd 履歴診断方式
JPS63229559A (ja) * 1987-03-19 1988-09-26 Matsushita Electric Ind Co Ltd 共有メモリのロギング装置
JPH07295858A (ja) * 1994-04-28 1995-11-10 Sony Corp 画像処理装置及び並列コンピュータのデバッグ処理方法
JPH1040217A (ja) * 1996-07-24 1998-02-13 Nec Corp バス監視システム

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045853A (ja) * 1983-08-22 1985-03-12 Fujitsu Ltd 履歴診断方式
JPS63229559A (ja) * 1987-03-19 1988-09-26 Matsushita Electric Ind Co Ltd 共有メモリのロギング装置
JPH07295858A (ja) * 1994-04-28 1995-11-10 Sony Corp 画像処理装置及び並列コンピュータのデバッグ処理方法
JPH1040217A (ja) * 1996-07-24 1998-02-13 Nec Corp バス監視システム

Also Published As

Publication number Publication date
JPH11242637A (ja) 1999-09-07

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