WO2001011668A1 - Procede de fabrication d'un dispositif semi-conducteur - Google Patents

Procede de fabrication d'un dispositif semi-conducteur Download PDF

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Publication number
WO2001011668A1
WO2001011668A1 PCT/JP2000/005107 JP0005107W WO0111668A1 WO 2001011668 A1 WO2001011668 A1 WO 2001011668A1 JP 0005107 W JP0005107 W JP 0005107W WO 0111668 A1 WO0111668 A1 WO 0111668A1
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Prior art keywords
silicon
germanium
mixed crystal
crystal semiconductor
semiconductor
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PCT/JP2000/005107
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English (en)
Japanese (ja)
Inventor
Takashi Uchino
Akihiro Miyauchi
Takeo Shiba
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Hitachi, Ltd.
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Publication of WO2001011668A1 publication Critical patent/WO2001011668A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures

Definitions

  • the present invention relates to a semiconductor device including a MOS transistor or a bipolar transistor having a shallow junction, or a semiconductor device including a capacitor, and a method of manufacturing the same.
  • the present invention relates to a logic system LSI, a DRAM / CMOS mixed system LSI
  • the present invention relates to a semiconductor device used in a flash integrated CMOS embedded system LSI. Background art
  • the International Conference on Electronic Devices (1992) Proceedings, pp. 885 to 888 (IEDM Technical Digest, pp. 885-888 (1992)) states that the source and drain diffusion depths are based on the stacked source 'drain structure. It is reported that the shallower (xj) improved the short channel effect and the hot carrier effect.
  • the current selective epitaxial growth technology has caused variations in the thickness of the stacked layers. Therefore, it is difficult to control xj, and there is a problem that the transistor characteristics vary.
  • the gate electrode is stacked via the insulating film on the side wall of the gate and is in contact with the source / drain layers, so that there is a problem that the gate capacitance increases.
  • a silicon-germanium layer containing boron is formed on a silicon substrate, and boron in the silicon-germanium layer is solid-phase diffused by heat treatment to form a shallow junction source / drain. After that, the silicon-germanium layer containing boron is removed with a mixed solution of hydrofluoric acid and nitric acid.
  • Japanese Patent Application Laid-Open No. 9-162174 discloses the following shallow junction forming method.
  • FIG. 3B is a cross-sectional view of a semiconductor device manufactured by the manufacturing method disclosed in the above publication.
  • a gate electrode 8 and a silicon nitride film side wall 19 are formed on a semiconductor substrate 10 with a gate oxide film 7 interposed therebetween.
  • cover the entire surface with silicon A film layer is formed and BF 2 ions are implanted.
  • the silicon 'germanium layer is etched back to form sidewalls 51 of the silicon-germanium layer containing boron, and further implanted with BF 2 ions, and then heat-treated to form a shallow diffusion layer 5 and a deep diffusion layer 1 2.
  • the method of manufacturing a semiconductor device described in the above-mentioned Japanese Patent Application Laid-Open No. Hei 9-161 174 does not provide a gate capacitance because the silicon germanium layer exists on the side wall of the gate electrode via the silicon nitride film side wall 19. There is a problem that increases. Further, as shown in FIG. 3 (b), since the silicon nitride film side wall 19 is present, the lateral diffusion distance d L immediately below the gate electrode is reduced, and there is a problem that the current driving capability is reduced. Furthermore, no mention was made of the formation of a CMOS transistor.
  • Japanese Patent Application Laid-Open No. 3-110122 discloses the following shallow junction forming method.
  • FIG. 3A is a cross-sectional view of a semiconductor device in which a shallow junction 5 is formed by using conventional ion implantation.
  • the activation rate of impurities is reduced, and the resistance of the source / drain diffusion layers is increased. Furthermore, in ion implantation, the diffusion distance in the lateral direction is smaller than the depth of the driving, so when a shallow junction of 30 niaerf is formed, the lateral diffusion distance d L immediately below the Gout electrode becomes as small as 10 nm or less. There is a problem that current driving capability is reduced.
  • FIG. 3B is a cross-sectional view of a semiconductor device manufactured by the manufacturing method disclosed in the above-mentioned Japanese Patent Application Laid-Open No. Hei 9-161624.
  • FIG. 3 (b) shows that the gut capacitance is increased due to the presence of the silicon * game layer 51 containing polon on the gate electrode sidewall via the silicon nitride sidewall 19. Further, there is a problem that the circuit performance is deteriorated. There is a problem that the lateral diffusion distance d L immediately below the gate electrode is reduced due to the presence of the silicon nitride film side wall 19, and the current driving capability is reduced. Disclosure of Kishi
  • An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device having a low-resistance source / drain diffusion layer with a shallow junction and capable of simultaneously achieving a large current driving capability and suppressing a short channel effect, and a method of manufacturing the same. To provide.
  • Another object of the present invention is to provide a CM having a shallow junction and a low resistance source / drain diffusion layer. It is to provide a method for manufacturing a semiconductor device having an OS transistor.
  • the purpose of the above is to dope impurities at a high concentration by ion implantation into a mixed crystal semiconductor 2 of silicon and germanium formed on a semiconductor substrate 1 as shown in FIG. 1 and then to dope this impurity by heat treatment.
  • the impurity was doped with a mixture of ammonia, hydrogen peroxide and water (Fig. 2). This is achieved by a semiconductor device having a low-resistance and shallow junction diffusion layer 5 formed by removing the mixed crystal semiconductor layer 4 of silicon and germanium.
  • the diffusion layer 5 is isotropically formed by solid-phase diffusion, the lateral diffusion distance and the diffusion layer depth are equal, and as shown in FIG.
  • the lateral diffusion distance d L is smaller than that of conventional ion implantation, and high current drive capability can be obtained.
  • Another object of the present invention is to separate n-type impurities and p-type impurities using a photomask at the time of ion implantation into the mixed crystal semiconductor layer 4 of silicon and germanium, thereby forming a shallow junction of a CMOS transistor. This is achieved by forming a source and a drain.
  • the thermal diffusion rate of impurities in the mixed crystal semiconductor layer 4 of silicon and germanium, which is a solid-phase diffusion source is about 100 times faster than that in silicon. Even if the thickness of the mixed crystal semiconductor layer 4 varies, a diffusion layer having a uniform depth in silicon can be manufactured.
  • the mixed crystal semiconductor layer 4 of silicon and germanium is made amorphous or polycrystalline.
  • the impurity can be doped by ion implantation without channeling, so that a shallower junction layer can be formed.
  • the mixed crystal semiconductor layer 4 of silicon and germanium doped with impurities is removed with a mixed solution of ammonia, hydrogen peroxide and water, the high concentration impurity-doped silicon-silicon-silicon oxide film is etched without etching. It can be removed with a selectivity. Further, by selectively growing the mixed crystal semiconductor layer 4 of silicon and germanium, a shallow junction and a deep junction can be simultaneously formed by one ion implantation. This deep diffusion layer can be used for a high breakdown voltage semiconductor device.
  • FIGS. 1A to 1D are views for explaining the steps of a method of manufacturing a semiconductor device according to a first embodiment of the present invention in the order of steps
  • FIGS. Figure 2 is a diagram of experimental data showing the etching rate of a mixed crystal semiconductor of silicon and germanium with respect to a mixed solution of ammonia, hydrogen peroxide and water (2: 1: 5) and a hydrazine solution.
  • 3A and 3B are cross-sectional views for explaining a difference between the conventional example and the MOS transistor of the present invention.
  • FIGS. 3A and 3B are conventional examples
  • FIG. 3C is a cross-sectional view of the semiconductor device of the present invention. .
  • FIG. 5A to 5E are views for explaining each step of the method for manufacturing a semiconductor device according to the third embodiment of the present invention, and FIGS. 5A to 5E are cross-sectional views of each step.
  • FIGS. 6A to 6E are views for explaining the steps of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention in order of steps, and FIGS. 6A to 6E are cross-sectional views of the steps.
  • FIG. 7 shows a semiconductor device according to a fifth embodiment of the present invention.
  • FIGS. 4A to 4E are views for explaining each step of the body device manufacturing method in the order of steps
  • FIGS. 8A to 8E are views for explaining each step of the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention
  • FIGS. 8A to 8E are cross-sectional views of each step.
  • FIG. 9 is a sectional view showing a semiconductor device according to a seventh embodiment of the present invention.
  • FIG. 10 is a cross-sectional view showing a semiconductor device according to an eighth embodiment of the present invention.
  • FIG. 11 is a sectional view showing a semiconductor device according to a ninth embodiment of the present invention.
  • FIGS. 12A to 12C are views for explaining the steps of the method for manufacturing the semiconductor device according to the tenth embodiment of the present invention, and FIGS. 12A to 12C are cross-sectional views of each step.
  • FIGS. 13A to 13F are views for explaining the respective steps in the method of manufacturing the semiconductor device according to the eleventh embodiment of the present invention, and FIGS. 13A to 13F are cross-sectional views of the respective steps.
  • FIGS. 14A to 14E are views for explaining the respective steps in the method of manufacturing the semiconductor device according to the 12th embodiment of the present invention, in which (a) to (e) are cross-sectional views of the respective steps.
  • FIG. 1A a mixed crystal semiconductor layer 2 of silicon and germanium is formed on a semiconductor substrate 1.
  • the mixed crystal semiconductor layer 2 of silicon and germanium can be formed of any of single crystal, polycrystal, and amorphous, and as shown in FIG. 2, the etching selectivity with respect to the silicon layer can be obtained. It is formed so that the germanium composition ratio X becomes 20% and X becomes 100%.
  • FIG. 1A a mixed crystal semiconductor layer 2 of silicon and germanium is formed on a semiconductor substrate 1.
  • the mixed crystal semiconductor layer 2 of silicon and germanium can be formed of any of single crystal, polycrystal, and amorphous, and as shown in FIG. 2, the etching selectivity with respect to the silicon layer can be obtained. It is formed so that the germanium composition ratio X becomes 20% and X becomes 100%.
  • the melting point of germanium is 937 and the melting point of silicon is 1415, it is necessary to prevent the diffusion of impurities from the surface of the mixed crystal semiconductor layer 4 of silicon and germanium by 1 000 °. It is desirable that it be C or less.
  • the mixed-conductivity semiconductor layer 4 of silicon and germanium of the second conductivity type is removed with a mixed solution of ammonia, hydrogen peroxide and water, and the second conductivity type is removed. Only the diffusion layer 5 is formed.
  • Embodiment 2 is an example in which a shallow junction layer 5 is formed in an opening formed by an insulating film layer 6.
  • Example 2 will be described according to the manufacturing process.
  • a first insulating film layer 6 having an opening is formed on a semiconductor substrate 1 by a known method.
  • a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 1.
  • the mixed crystal semiconductor layer 2 of silicon and germanium is formed on the insulating film layer 6 as polycrystalline or amorphous.
  • implanted impurity ions 3 mixed crystal semiconductor layer 2 of silicon and germanium, 1 0 2 ° pieces Roh cm 3 or more of the second conductivity type and the second conductivity type impurity doped A mixed crystal semiconductor layer 4 of silicon and germanium is formed.
  • FIG. 4A a first insulating film layer 6 having an opening is formed on a semiconductor substrate 1 by a known method.
  • a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 1.
  • the mixed crystal semiconductor layer 2 of silicon and germanium is formed on the insulating film layer 6 as polycrystalline or amorphous.
  • the second conductivity type silicon layer 5 is formed by solid phase diffusion from the mixed crystal semiconductor layer 4 of the second conductivity type silicon and germanium by heat treatment.
  • the thermal diffusion rate of impurities in the mixed crystal semiconductor layer 4 of silicon and germanium is Since it is about 100 times faster than in the recon, the impurity is uniformly doped even in the region where the mixed crystal semiconductor layer 4 of silicon and germanium at the edge of the opening is thick.
  • the mixed crystal semiconductor layer 4 of silicon and germanium of the second conductivity type is removed with a mixed solution of ammonia, hydrogen peroxide water and water, and a low-resistance and shallow junction of the second conductivity type is removed.
  • the two conductivity type diffusion layer 5 was left.
  • FIGS. 5A to 5E are cross-sectional views illustrating an example of steps of a method for manufacturing a semiconductor device having a MOS transistor according to the third embodiment of the present invention.
  • reference numeral 10 denotes a semiconductor substrate, for example, doped with n-type.
  • a first insulating film layer 6 for element isolation, a second insulating film layer 7 for a gate insulating film, and a second insulating film layer are arranged on the semiconductor substrate 10 by a known method.
  • the formed p-type polycrystalline silicon gate electrode 8 and the third insulating film layer 9 formed on the gate electrode are formed.
  • a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 10.
  • the p-type source and drain 5 are formed by solid-phase diffusion from the mixed crystal semiconductor layer 4 of p-type silicon and germanium.
  • FIG. 5D the mixed crystal semiconductor layer 4 of p-type silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide water and water.
  • a deep source is formed by ion implantation.
  • the drain 12 was formed, and the MOS transistor shown in FIG. 5E was formed.
  • a low-resistance and shallow source and drain 5 are formed to form a MOS transistor that suppresses the single-channel effect and realizes a high current driving capability.
  • FIGS. 6A to 6E are cross-sectional views illustrating an example of steps of a method for manufacturing a semiconductor device having a CMOS transistor according to a fourth embodiment of the present invention.
  • reference numeral 13 denotes a second conductivity type well, for example, doped with p-type.
  • Reference numeral 14 denotes an n-type gate, and 15 denotes an n-type polysilicon gate electrode.
  • a p-type well 13, an n-type well 14, a first insulating film layer 6 for element isolation, and a second insulating film layer 7 for a gate insulating film are formed on a semiconductor substrate 10 by a known method. I do.
  • FIG. 1 As shown in FIG.
  • an n-type polycrystalline silicon gate electrode 15 disposed on the p-type well 13 and a p-type polycrystalline silicon gate electrode 8 disposed on the n-type well 14 are formed.
  • a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 10.
  • the mixed crystal semiconductor layer 16 of silicon and germanium doped with n-type impurities and the p-type impurities were doped by ion implantation using a photoresist as a mask.
  • a mixed crystal semiconductor layer 17 of silicon and germanium is formed.
  • the gate electrode and the source and drain were silicided to form a CMOS transistor.
  • silicide layer 52 for example, TiSi 2 or CoSi 2 can be used.
  • a CMOS transistor having a low resistance and a shallow junction source and drain could be formed.
  • FIGS. 7A to 7E are cross-sectional views illustrating an example of steps of a method for manufacturing a semiconductor device having a MOS transistor according to a fifth embodiment of the present invention.
  • Example 5 is an example in which the present invention is applied to a MOS transistor having a polymetal gate structure that can prevent an increase in gate resistance even if the gate length is reduced.
  • the formed third insulating film layer 9 is formed.
  • the metal electrode layer 19 for example, tungsten or a laminated film of tungsten and tungsten nitride is used.
  • an insulating film 20 having a thickness of about 10 nm is formed on the side wall of the gate electrode.
  • an insulating film is deposited on the entire surface of the n-type semiconductor substrate 10 and then formed by using anisotropic dry etching, or after the entire surface of the semiconductor substrate 10 is oxidized, Either use anisotropic dry etching May be used.
  • a mixed crystal semiconductor layer 2 of silicon and germanium is formed on the entire surface of the semiconductor substrate 10.
  • a mixed crystal semiconductor layer 4 of silicon and germanium doped with P-type impurities of 102 G cm 3 or more is formed by ion implantation.
  • a p-type source and a drain 5 having a diffusion depth d are formed by solid-phase diffusion from a mixed crystal semiconductor layer 4 of p-type silicon and germanium by heat treatment.
  • the diffusion depth d needs to be larger than the thickness t of the insulating film on the side wall of the gate electrode by this heat treatment.
  • the mixed crystal semiconductor layer 4 of p-type silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide and water. Then, as shown in FIG.
  • a fourth insulating film layer 11 is formed on the side wall of the gut electrode by a known method, and then a p-type deep source and drain 12 are formed by ion implantation. .
  • a MOS transistor having a low resistance and a shallow source and drain 5 and a polymetal gate could be formed.
  • FIGS. 8A to 8E are cross-sectional views illustrating an example of steps of a method for manufacturing a semiconductor device having a CMOS transistor according to Embodiment 6 of the present invention.
  • Embodiment 6 is an example in which the present invention is applied to a CMOS transistor having a polymetal gate structure.
  • an n-type polycrystalline silicon gate electrode layer 15 was formed on the p-type well 13 with the second insulating film layer 7 interposed therebetween. And metal layer 19 and third insulating film layer 9, p-type polycrystalline silicon on n-type well 14 via second insulating film layer 7 ′ Gate electrode 8, all layers 19, and third insulating film Form layer 9.
  • an insulating film 20 on the side wall of the gate electrode as shown in FIG.
  • a mixed crystal semiconductor layer 2 of copper and germanium is formed on the entire surface of the semiconductor substrate 10.
  • a mixed crystal semiconductor layer 16 of n-type impurity doped silicon and germanium and a p-type impurity doped silicon And a mixed crystal semiconductor layer 17 of germanium are formed.
  • the n-type shallow source and drain 18 are formed by solid-phase diffusion from the n-type silicon and germanium mixed crystal semiconductor layer 16 and the p-type silicon and germanium / lemanium mixed crystal semiconductor layer 17.
  • a p-type shallow source and drain 5 are formed, respectively, and the mixed crystal semiconductor layer of silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide and water.
  • a CMOS transistor having a polymetal gate, a source and a drain having a low resistance and a shallow junction can be formed.
  • FIG. 9 is a sectional view of a MOS transistor according to Embodiment 7 of the present invention.
  • 5 is a shallow source / drain region containing germanium, the junction depth d1 of which is 30 nm or less, and 11 is a fourth region not containing germanium formed on the side wall of the gate electrode. This is an insulating film layer.
  • the short channel effect is suppressed by making the source and drain regions 5 shallower, the mobility is increased by introducing germanium into the source and drain regions, and the resistance is reduced by lowering the resistance of the source and drain regions.
  • Obtained current drive capability It is known that the solid solubility limit of impurities in a mixed crystal semiconductor of silicon and germanium increases with an increase in the composition ratio of germanium in silicon. This is because the inclusion of germanium in the silicon caused stress in the crystal structure, and the impurities were mixed into the crystal structure. Since this stress is also generated by introducing carbon and oxygen into silicon, the shallow source and drain layers 5 can be formed of a silicon layer containing any of germanium, carbon, and oxygen.
  • FIG. 10 is a cross-sectional view of a CMOS transistor according to Embodiment 8 of the present invention.
  • Embodiment 8 is an example in which the MO transistor of Embodiment 7 is applied to a CMOS transistor.
  • 5 and 18 are shallow source / drain regions containing germanium, the junction depth d1 of which is 30 nm or less, and 11 is the germanium formed on the side wall of the Good electrode. This is the fourth insulating film layer not including.
  • FIG. 11 shows a cross-sectional view of a MOS transistor according to Embodiment 9 of the present invention.
  • Embodiment 9 Embodiment 9 is a semiconductor device in which a high breakdown voltage and a low breakdown voltage MOS transistor are formed on the same semiconductor substrate.
  • the deep source and drain regions 22 are for forming a high-voltage MOS transistor
  • the shallow source and drain regions 5 containing germanium are for forming a low-voltage and high-performance MOS transistor.
  • the method for manufacturing the source and drain regions 22 for the high-breakdown-voltage MOS transistor is the same as the method for manufacturing the MOS transistor of Example 3 except that silicon and germanium Covering the silicon oxide film to prevent the formation of a mixed crystal semiconductor layer of Ni, This can be realized by forming a mixed crystal semiconductor layer of silicon and germanium on the region where the shallow source and drain regions 5 are formed.
  • FIGS. 12A to 12C are cross-sectional views illustrating an example of steps of a method for manufacturing a semiconductor device having a capacitor according to Example 10 of the present invention.
  • an insulating film layer 23 and a first-conductivity-type polycrystalline silicon layer 24 are sequentially formed on the semiconductor substrate 1, and then a first-conductivity-type island-like silicon is formed.
  • a mixed crystal semiconductor layer 25 of germanium is formed on the semiconductor substrate 1, and then a first-conductivity-type island-like silicon is formed.
  • a mixed crystal semiconductor layer 25 of germanium The island-shaped mixed crystal semiconductor layer 25 of silicon and germanium has a diameter of about 50 nm, and the mixed crystal semiconductor of silicon and germanium has a large anisotropy during crystal growth. Then, it can be easily formed.
  • the first conductivity type polycrystalline semiconductor of the first conductivity type is selectively formed using a hydrazine solution using the island-shaped mixed crystal semiconductor layer 25 of silicon and germanium as a mask. Etching the silicon layer. Polycrystalline silicon and silicon germanium can change the etching selectivity rather than changing the composition ratio of germanium in silicon as shown in FIG. Then, as shown in FIG. 12 (c), an insulating film 26 and a first conductivity type polycrystalline silicon layer 27 were sequentially formed on the entire surface of the semiconductor substrate 1 to form a semiconductor device having a capacitor. According to the present invention, a capacitor having an increased surface area of a semiconductor substrate and an increased capacitance per unit area has been realized. FIGS.
  • FIG. 13A to 13F are cross-sectional views illustrating an example of steps of a method for manufacturing a semiconductor device having a bipolar transistor according to Example 11 of the present invention.
  • reference numeral 1 denotes a semiconductor substrate, which is, for example, n-type doped.
  • a first insulating film layer 6 for element isolation and a p-type multilayer are formed on the semiconductor substrate 1 by a known method.
  • a crystalline silicon layer 28 and an insulating film layer 29 disposed on the p-type polycrystalline silicon are sequentially formed.
  • the insulating film layer 29 and the p-type polycrystalline silicon layer 28 in the base forming region are removed by dry etching to open a window 30 for forming a base region.
  • a heat treatment was performed at 900 ° C. for 30 seconds in a nitrogen atmosphere using a lamp heating apparatus, so that the solidification from the p-type polycrystalline silicon layer 28 was completed.
  • the mixed crystal semiconductor layer 2 of silicon and germanium is formed.
  • boron was introduced into the mixed crystal semiconductor layer of silicon and germanium by ion implantation, and heat treatment was performed at 900 ° C for 30 seconds in a nitrogen atmosphere using a lamp heating device.
  • a shallow junction p-type base layer 33 is formed by solid-phase diffusion from a mixed crystal semiconductor layer 32 of p-type silicon and germanium.
  • the mixed crystal semiconductor layer 32 of p-type silicon and germanium is removed with a mixed solution of ammonia, hydrogen peroxide and water.
  • the insulating film layer 35 is formed on the side wall in the opening by a known method.
  • the n-type polycrystalline silicon layer 36 is subjected to a heat treatment at 100 O: 10 seconds in a nitrogen atmosphere using a lamp heating device.
  • An n-type emitter region 37 was formed by solid-phase diffusion of the 36 layers.
  • a low-resistance and thin base layer 33 is formed, and a high-speed bipolar transistor is realized.
  • a bipolar transistor is formed.
  • a BiCMOS-LSI may be formed by forming a MOS transistor on the same substrate. It is possible.
  • FIGS. 14A to 14D are cross-sectional views illustrating a process example of a method of manufacturing a semiconductor device having a metal gate MOS transistor according to Example 12 of the present invention.
  • reference numeral 38 denotes a gate electrode formed of a mixed crystal semiconductor of silicon and germanium.
  • a MOS transistor having a shallow source and drain 39 is formed by a known method.
  • CMP Chemical Mechanical Polishing
  • the gate electrode 38 is made to appear in the insulating film layer 40 as shown in FIG. 14 (b). Flatten.
  • CMP Chemical Mechanical Polishing
  • the mixed crystal semiconductor layer 38 of silicon and germanium was removed with a mixed solution of ammonia, hydrogen peroxide water and water, and the gate electrode forming opening 41 was formed. Form.
  • the metal gate electrode 42 is formed by filling the opening with a metal, for example, tungsten or a laminated film of tungsten and tungsten nitride, to form a metal gate MOS transistor. Formed.
  • a mixed crystal semiconductor layer of silicon and germanium can be doped with impurities by ion implantation, a low-resistance and shallow diffusion layer of a desired conductivity type can be formed in a desired region.
  • the source and drain regions of the MOS transistor are formed with low resistance and shallow diffusion layers to suppress short channel effects and obtain high current driving capability.
  • the gut capacity is increased by selectively removing it with a mixed solution of ammonia, hydrogen peroxide and water. A shallow junction could be formed without any problem.

Abstract

L'invention porte sur la fabrication d'un transistor MOS consistant à former une couche eutectique semi-conductrice (4) de silicium et de germanium sur un substrat semi-conducteur (10). La susdite couche (4) est d'abord dopée à une concentration en impuretés supérieure à 1020/cm3 par implantation d'ions, puis traitée thermiquement pour former une couche diffusée (5) de faible résistance et une jonction peu profonde par diffusion en phase solide à partir de la couche eutectique semi-conductrice (4). On élimine ensuite la couche eutectique semi-conductrice (4) dopée à l'aide d'une solution de décapage pour former les régions source et drain.
PCT/JP2000/005107 1999-08-06 2000-07-28 Procede de fabrication d'un dispositif semi-conducteur WO2001011668A1 (fr)

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US8569158B2 (en) 2011-03-31 2013-10-29 Tokyo Electron Limited Method for forming ultra-shallow doping regions by solid phase diffusion
US8580664B2 (en) 2011-03-31 2013-11-12 Tokyo Electron Limited Method for forming ultra-shallow boron doping regions by solid phase diffusion
US9899224B2 (en) 2015-03-03 2018-02-20 Tokyo Electron Limited Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions
CN115849297A (zh) * 2022-12-27 2023-03-28 上海铭锟半导体有限公司 一种mems空腔的制备方法

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KR100406537B1 (ko) * 2001-12-03 2003-11-20 주식회사 하이닉스반도체 반도체장치의 제조 방법
KR101155097B1 (ko) 2005-08-24 2012-06-11 삼성전자주식회사 반도체 장치의 제조 방법 및 그에 의해 제조된 반도체 장치
US8987102B2 (en) * 2011-07-27 2015-03-24 Applied Materials, Inc. Methods of forming a metal silicide region in an integrated circuit

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569158B2 (en) 2011-03-31 2013-10-29 Tokyo Electron Limited Method for forming ultra-shallow doping regions by solid phase diffusion
US8580664B2 (en) 2011-03-31 2013-11-12 Tokyo Electron Limited Method for forming ultra-shallow boron doping regions by solid phase diffusion
US8877620B2 (en) 2011-03-31 2014-11-04 Tokyo Electron Limited Method for forming ultra-shallow doping regions by solid phase diffusion
US9012316B2 (en) 2011-03-31 2015-04-21 Tokyo Electron Limited Method for forming ultra-shallow boron doping regions by solid phase diffusion
US9899224B2 (en) 2015-03-03 2018-02-20 Tokyo Electron Limited Method of controlling solid phase diffusion of boron dopants to form ultra-shallow doping regions
CN115849297A (zh) * 2022-12-27 2023-03-28 上海铭锟半导体有限公司 一种mems空腔的制备方法

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