WO2000076200A1 - Appareil de formation d'images a semi-conducteurs, methode de commande de celui-ci et peripherique d'entree d'image - Google Patents
Appareil de formation d'images a semi-conducteurs, methode de commande de celui-ci et peripherique d'entree d'image Download PDFInfo
- Publication number
- WO2000076200A1 WO2000076200A1 PCT/JP2000/003735 JP0003735W WO0076200A1 WO 2000076200 A1 WO2000076200 A1 WO 2000076200A1 JP 0003735 W JP0003735 W JP 0003735W WO 0076200 A1 WO0076200 A1 WO 0076200A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- charge transfer
- charge
- transferring
- train
- column
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
- H04N25/46—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled by combining or binning pixels
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/713—Transfer or readout registers; Split readout registers or multiple readout registers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/745—Circuitry for generating timing or clock signals
Definitions
- the present invention relates to a solid-state imaging device, a driving method thereof, and an image input device.
- the present invention relates to a solid-state imaging device that alternately transfers and outputs charges captured by a plurality of sensor rows or adds and outputs charges of pixels in the same row, a driving method thereof, and an image input device.
- a solid-state imaging device including a linear sensor is used in an image input device applied to a scanner, a copying machine, and the like, and an image is input by scanning a reading position of the solid-state imaging device.
- the timing of the reset pulse for discharging the charge of the floating diffusion which is the charge-voltage conversion means, is controlled, and the floating diffusion amplifier is controlled.
- the pixels captured by both sensor rows, which are transferred alternately, are added by a floating diffusion amplifier and output.
- charge addition is performed by a floating diffusion amplifier in a multiplexed solid-state imaging device.
- the charge captured by one sensor row is transferred to the opening / diffusion amplifier, and then the charge captured by the other sensor row is added.
- the addition output cannot be obtained, and the period of the addition output is shortened, so that there is a problem that it is difficult to perform the subsequent signal processing.
- the cycle of obtaining the added output becomes slower, and there is a problem that it is not possible to respond to the demand for quick signal processing in the subsequent stage. Disclosure of the invention
- the present invention provides a solid-state imaging device, a driving method thereof, and an image input device which have been made to solve such problems. That is, the solid-state imaging device according to the present invention includes a first charge transfer column for transferring the charge captured by the first light receiving pixel column, and a second charge transfer for transferring the charge captured by the second light receiving pixel column. Column, a multiplex section for transferring the charges transferred in the first charge transfer column and the second charge transfer column in the direction of the charge-voltage conversion means, respectively, and, in the case of the alternate output mode, the first charge transfer.
- Signals of opposite phases are applied to the last stage of the column and the last stage of the second charge transfer column, and in the addition output mode, the addition in the second stage of the second charge transfer column is performed in the second stage.
- Signal generation means for providing a signal for accumulating charges only at the transfer timing corresponding to the minute o
- the signal generation means accumulates electric charges at the final stage of the second charge transfer sequence only at the transfer timing corresponding to the added amount in the second charge transfer sequence. Therefore, the charges transferred in the second charge transfer train are accumulated, that is, added, just before the final stage of the second charge transfer train. Also, while the above signal is given to the last stage of the charge transfer sequence of No. 2, the charges transferred in the first charge transfer sequence are sent to the multiplex unit, and the first stage of the multiplex unit corresponds to the added amount. The charge transferred in the first charge transfer train is accumulated, that is, added only at the transfer timing.
- the driving method of the solid-state imaging device includes a first charge transfer row for transferring the charge captured by the first light receiving pixel row and a second charge transfer row for transferring the charge captured by the second light receiving pixel row. And a multiplex unit for transferring the charges transferred in the first charge transfer train and the second charge transfer train in the direction of the charge-to-voltage conversion means, respectively.
- signals of opposite phases are given to the last stage of the first charge transfer train and the last stage of the second charge transfer train, respectively, and in the addition output mode, the second charge transfer is performed.
- a signal for accumulating charges is provided only at the transfer timing corresponding to the added amount in the second charge transfer column.
- the present invention in the addition output mode, only the transfer timing corresponding to the added amount in the second charge transfer train is accumulated at the final stage of the second charge transfer train. Therefore, the charges transferred in the second charge transfer column are accumulated, that is, added, just before the final stage of the second charge transfer column.
- the charges transferred in the first charge transfer train are sent to the multiplex unit, and the addition is performed in the first stage of the multiplex unit. The accumulation, that is, the addition of the charges transferred in the first charge transfer column is performed only at the transfer timing corresponding to.
- the image input device of the present invention includes a first charge transfer column for transferring the charge taken in the first light receiving pixel column, and a second charge transfer for transferring the charge taken in the second light receiving pixel column. And the charges transferred in the first charge transfer row and the second charge transfer row, respectively.
- signal generation means for providing a signal for accumulating charges only at a transfer timing corresponding to an addition in the second charge transfer sequence to a final stage of the second charge transfer sequence.
- a solid-state imaging device having the following.
- FIG. 1 is a schematic diagram illustrating a solid-state imaging device according to the present embodiment
- FIG. 2 is a schematic diagram illustrating a main part of the solid-state imaging device according to the present embodiment
- FIG. FIG. 4 is a timing chart for explaining the mode
- FIG. 4 is a timing chart for explaining the addition output mode.
- FIG. 1 is a schematic diagram illustrating a solid-state imaging device according to the present embodiment
- FIG. 2 is a schematic diagram illustrating main components of the solid-state imaging device of the present embodiment
- FIG. 3 and FIG. 4 is a timing chart illustrating a method for driving the solid-state imaging device according to the embodiment.
- the solid-state imaging device has a first CCD register provided corresponding to two sensor rows, that is, a first light receiving pixel row 1 and a second light receiving pixel row 2. 10, a second CCD register 20, and a multiplex unit 30 for transferring the charges transferred by the first CCD register 10 and the second CCD register 20 according to the output mode.
- the potential of a part of the charge output side is deeper than other areas. It is formed as follows.
- the solid-state imaging device also includes a signal generation unit 3 that supplies a pulse signal to the first CCD register 10, the second CCD register 20, the multiplex unit 30, and the like at a predetermined timing.
- the charges captured by the two sensor rows are alternately transferred by the multiplexing section 30, and each of the charges is received from the floating diffusion amplifier FD connected at the subsequent stage.
- Output mode, and an addition output mode in which, of the charges captured by the two sensor rows, the charges of adjacent pixels in the same row are added and output.
- the first light receiving pixel row 1 and the second light receiving pixel row 2, which are two sensor rows, are arranged in a state shifted by a half pixel pitch, so that the alternate output mode is set.
- the two Sen By alternately outputting the charges captured by the sub-arrays, an image can be read at a resolution twice as high as the pitch of the pixels in a single row in the pixel row direction.
- the addition output mode the charges taken in adjacent pixels in the same column are added and output, so that one pixel of the pixel pitch in one column is output.
- An image is read at a resolution of 2.However, since the added charges are transferred to the floating diffusion amplifier FD, a signal output that adds the charges of adjacent pixels at the same timing as in the alternate output mode is obtained. Can be.
- the solid-state imaging device can apply a pulse signal to the last stage of the second CCD register 20 independently. Switching is performed according to the timing of the pulse signal to be applied.
- a pulse signal composed of ⁇ 1 and ⁇ 2 is alternately applied to the first CCD register 10 and 0 is applied to the second CCD register 20.
- Pulse signals consisting of 2, 0 1 are applied alternately, and 0 1 'is independently applied to the final stage of the second CCD register 20.
- FIG. 3 is a timing chart in the case of the alternate output mode.
- ⁇ 1 and ⁇ 2 which are out of phase with each other, are applied to the first CCD register 10 and the second CCD register 20, respectively.
- the same pulse as ⁇ 1 is applied as 0 1 ′ applied to the final stage of the second CCD register 20.
- the transfer of the charge taken in the first light receiving pixel column by the first CCD register 10 and the transfer of the charge taken in the second light receiving pixel column by the second CCD register 20 are performed alternately. .
- 0 3 and ⁇ 4 which are out of phase with each other, are applied to the multiplex unit 30.
- 0 3 and 4 4 have a frequency twice as high as the above 0 1 and 0 2, and are transmitted alternately from the first CCD register 10 and the second CCD register 20 in the first light receiving pixel column. The charges and the charges in the second light receiving pixel column are sequentially transferred to the floating diffusion amplifier FD.
- the stage is reset to the ⁇ 3 force and L0 w level, and the ⁇ 4 force and Hig h level.
- Lus ⁇ RS While the power is at the Low level (reset, until Lus 3 ⁇ 46 RS goes to the High level)
- the signal of one pixel in the first pixel line from the floating diffusion amplifier FD and the floating diffusion amplifier FD A signal for one pixel in the second pixel column can be output alternately.
- FIG. 4 is a timing chart in the case of the addition output mode.
- ⁇ 1 and ⁇ 2 which are out of phase with each other, are applied to the first CCD register 10 and the second CCD register 20, respectively.
- the High level is set only once in the period of the ⁇ 1 force and the High level twice.
- the floating diffusion ion amplifier FD finally adds the two pixels of the first light receiving pixel array in the period of 1 and the two pixels of the second light receiving pixel column in the period of 2.
- the signals can be output alternately in the order of the signals.
- the above-described solid-state imaging device and its driving method are mainly applied to an image input device such as a scanner and a copying machine.
- an image input device such as a scanner and a copying machine.
- each pixel captured in the first light receiving pixel row and the second light receiving pixel row by the alternate output mode described above is used.
- Pre-scanning at the time of image capture reading to determine image size and area, etc.
- the addition output mode described above is used to add and output the two adjacent pixels of the first light receiving pixel column. Two adjacent pixels of two light receiving pixel columns are alternately output.
- one solid-state imaging device can meet the requirements of both high resolution and high-speed processing.
- the solid-state imaging device, the driving method thereof, and the image input device according to the present invention have the following effects.
- a solid-state imaging device having a multipletus structure charges of adjacent pixels in the same light receiving pixel column can be added by simple pulse change, and the mode can be reduced without complicating circuit wiring and the like. It is possible to respond to switching.
- a single solid-state imaging device can support both high-resolution and high-speed signal processing, and can respond to various needs. As a result, it is possible to reduce the manufacturing cost of the solid-state imaging device that can support both high-resolution and high-speed signal processing.
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Facsimile Heads (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/762,623 US6744539B1 (en) | 1999-06-09 | 2000-06-08 | Solid-state image pick-up apparatus, driving method therefor, and image input apparatus |
EP00935594A EP1102467B1 (en) | 1999-06-09 | 2000-06-08 | Solid-state imaging device, method for driving the same, and image input device |
DE60020324T DE60020324T2 (de) | 1999-06-09 | 2000-06-08 | Festkörper-Bildaufnahmevorrichtung, Verfahren zur Ansteuerung und Bildeingabevorrichtung |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16216099 | 1999-06-09 | ||
JP11/162160 | 1999-06-09 | ||
JP2000162289A JP4419275B2 (ja) | 1999-06-09 | 2000-05-31 | 固体撮像装置およびその駆動方法並びに画像入力装置 |
JP2000/162289 | 2000-05-31 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2000076200A1 true WO2000076200A1 (fr) | 2000-12-14 |
Family
ID=26488054
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2000/003735 WO2000076200A1 (fr) | 1999-06-09 | 2000-06-08 | Appareil de formation d'images a semi-conducteurs, methode de commande de celui-ci et peripherique d'entree d'image |
Country Status (5)
Country | Link |
---|---|
US (1) | US6744539B1 (ja) |
EP (1) | EP1102467B1 (ja) |
JP (1) | JP4419275B2 (ja) |
DE (1) | DE60020324T2 (ja) |
WO (1) | WO2000076200A1 (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6770860B1 (en) * | 2000-02-14 | 2004-08-03 | Dalsa, Inc. | Dual line integrating line scan sensor |
JP3832661B2 (ja) * | 2003-12-12 | 2006-10-11 | ソニー株式会社 | 固体撮像装置の駆動方法 |
JP5181840B2 (ja) * | 2008-05-30 | 2013-04-10 | ソニー株式会社 | 固体撮像装置、固体撮像装置の駆動方法、及び電子機器 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09321953A (ja) * | 1996-05-28 | 1997-12-12 | Sanyo Electric Co Ltd | 撮像装置 |
JPH10285343A (ja) * | 1997-04-09 | 1998-10-23 | Canon Inc | 画像処理装置及び画像処理方法 |
JPH11164087A (ja) * | 1997-11-28 | 1999-06-18 | Sony Corp | 固体撮像装置およびその駆動方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
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US4432017A (en) * | 1981-07-20 | 1984-02-14 | Xerox Corporation | Adjacent bilinear photosite imager |
US4438457A (en) * | 1981-07-20 | 1984-03-20 | Xerox Corporation | High resolution imager employing staggered sensor structure |
US4712137A (en) | 1981-07-20 | 1987-12-08 | Xerox Corporation | High density CCD imager |
JPS58190169A (ja) * | 1982-04-30 | 1983-11-07 | Toshiba Corp | 固体撮像装置 |
CA1219337A (en) | 1983-08-22 | 1987-03-17 | Peter A. Levine | Reduced-noise ccd camera with single-sampled output |
JP2868915B2 (ja) | 1991-03-27 | 1999-03-10 | 株式会社東芝 | 固体撮像装置 |
JP2973650B2 (ja) | 1991-10-08 | 1999-11-08 | ソニー株式会社 | 電荷転送装置の出力回路 |
CA2060556A1 (en) | 1992-02-03 | 1993-08-04 | Savvas G. Chamberlain | Dual mode on-chip high frequency output structure with pixel video differencing for ccd image sensors |
JP2968898B2 (ja) * | 1993-02-23 | 1999-11-02 | シャープ株式会社 | 読取り装置 |
US5751444A (en) * | 1995-12-18 | 1998-05-12 | Adobe Systems Incorporated | Imaging apparatus for copying bound documents |
JPH09219824A (ja) | 1996-02-09 | 1997-08-19 | Sony Corp | 固体撮像装置 |
US6166831A (en) * | 1997-12-15 | 2000-12-26 | Analog Devices, Inc. | Spatially offset, row interpolated image sensor |
US6462779B1 (en) * | 1998-02-23 | 2002-10-08 | Eastman Kodak Company | Constant speed, variable resolution two-phase CCD |
-
2000
- 2000-05-31 JP JP2000162289A patent/JP4419275B2/ja not_active Expired - Fee Related
- 2000-06-08 US US09/762,623 patent/US6744539B1/en not_active Expired - Fee Related
- 2000-06-08 DE DE60020324T patent/DE60020324T2/de not_active Expired - Lifetime
- 2000-06-08 EP EP00935594A patent/EP1102467B1/en not_active Expired - Lifetime
- 2000-06-08 WO PCT/JP2000/003735 patent/WO2000076200A1/ja active IP Right Grant
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09321953A (ja) * | 1996-05-28 | 1997-12-12 | Sanyo Electric Co Ltd | 撮像装置 |
JPH10285343A (ja) * | 1997-04-09 | 1998-10-23 | Canon Inc | 画像処理装置及び画像処理方法 |
JPH11164087A (ja) * | 1997-11-28 | 1999-06-18 | Sony Corp | 固体撮像装置およびその駆動方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP1102467A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP1102467A4 (en) | 2001-10-04 |
JP2001057622A (ja) | 2001-02-27 |
EP1102467A1 (en) | 2001-05-23 |
DE60020324T2 (de) | 2006-04-27 |
EP1102467B1 (en) | 2005-05-25 |
US6744539B1 (en) | 2004-06-01 |
JP4419275B2 (ja) | 2010-02-24 |
DE60020324D1 (de) | 2005-06-30 |
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