WO2000065658A2 - Verfahren zum strukturieren einer metall- oder metallsilizidschicht sowie ein mit diesem verfahren hergestellter kondensator - Google Patents
Verfahren zum strukturieren einer metall- oder metallsilizidschicht sowie ein mit diesem verfahren hergestellter kondensator Download PDFInfo
- Publication number
- WO2000065658A2 WO2000065658A2 PCT/DE2000/001303 DE0001303W WO0065658A2 WO 2000065658 A2 WO2000065658 A2 WO 2000065658A2 DE 0001303 W DE0001303 W DE 0001303W WO 0065658 A2 WO0065658 A2 WO 0065658A2
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- WIPO (PCT)
- Prior art keywords
- layer
- metal
- zone
- structuring
- metal silicide
- Prior art date
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 151
- 239000002184 metal Substances 0.000 title claims abstract description 151
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000003990 capacitor Substances 0.000 title claims abstract description 30
- 229910021332 silicide Inorganic materials 0.000 title claims description 70
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 68
- 230000003647 oxidation Effects 0.000 claims description 34
- 238000007254 oxidation reaction Methods 0.000 claims description 34
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 16
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000005496 tempering Methods 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 2
- 229910052697 platinum Inorganic materials 0.000 claims description 2
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims 1
- 229910044991 metal oxide Inorganic materials 0.000 claims 1
- 150000004706 metal oxides Chemical class 0.000 claims 1
- 230000008569 process Effects 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000009413 insulation Methods 0.000 description 4
- 230000015654 memory Effects 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 2
- 229910019001 CoSi Inorganic materials 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 229910052762 osmium Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
Definitions
- the invention relates to a method for structuring a metal or metal silicide layer and to a high-epsilon dielectric or ferroelectric capacitor in an integrated semiconductor circuit.
- DRAMs microelectronic memory elements
- Semiconductor memory elements comprise a capacitor in which the information to be stored is stored in the form of a charge.
- Silicon oxide or silicon nitride layers which have a dielectric constant of at most about 8 are mostly used as the capacitor material.
- FeRAMs non-volatile memories
- US Pat. No. 5,561,307 describes a ferroelectric capacitor in an integrated circuit, the base electrode of which is formed from a Pt layer by an RIE (reactive ion etching) process.
- RIE reactive ion etching
- the RIE process shows an unsatisfactory selectivity towards mask materials and Pt background and does not allow the production of a base electrode with a well-defined edge profile.
- the invention has for its object to provide a method for structuring a metal or metal silicide layer, which in a technologically simple manner e.g. enables the manufacture of a high-epsilon dielectric or ferroelectric capacitor with a metal or metal silicide electrode in an integrated circuit.
- the invention further aims to produce a high-epsilon dielectric or ferroelectric capacitor with a metal or metal silicide electrode with a well-defined edge profile.
- the invention is based on undesired areas of the unstructured metal or metal silicide layer, from which, for example, a base electrode for a condensate buried under an oxide instead of being removed by chemical or physical processes as was previously the case.
- a structuring layer is first produced with an image (pre-structured base layer zone) of the structured metal layer to be formed. Since the structuring layer can be realized from customary, technologically simple to use layer materials (Si, in particular polysilicon in the sinking layer zone; for example SiO 2 in the base layer zone), ⁇ ? this layer can easily be produced using the usual planar technology (layer deposition method; layer structuring using lithography and etching techniques).
- the pre-structured base layer zone preferably has the same structure with respect to the metal layer to be structured (metal region). That is, the base layer zone 20 serves as a mask of the metal region to be formed, which is to be created by structuring the metal layer.
- a metal layer is deposited over the structuring layer.
- the 25 undesired areas of the metal layer lying laterally outside the base layer zone are silicidized and subsequently "sunk" by oxidation in the structuring layer.
- a structured metal layer can be formed, which consists largely of metal over its entire surface and serves as an electrode, metallization or conductor track.
- the structured metal layer comprises a structured metal region which is essentially of the same structure with respect to the base layer zone, ie that the outer contour of the base layer zone corresponds to the contour of the structured corresponds to the metal area.
- the created metal area is not changed in its position, but can also be partially or completely silicided.
- the electrical contacting of the structured metal region to be produced is preferably formed by an electrical connection structure made of Si, in particular polysilicon, provided in the base layer zone.
- an electrically conductive barrier layer is expediently deposited between the connection structure and the metal layer to protect the metal layer from silicidation by the connection structure and to protect the connection structure against oxidation.
- the structured metal area can also be contacted subsequently by, for example, a contact structure introduced into an insulation layer covering the metal area.
- An oxidation mask for protection against oxidation of such silicided metal layer regions is preferably produced on the deposited metal layer in the area above the base layer zone and at least where later the metal layer is to be silicided. Oxidation and "sinking" of silicided metal areas within the base electrode contour are thereby reliably excluded.
- the countersink layer zone of the structuring layer is preferably at least twice as thick as the metal layer. The submerged layer zone then has a sufficiently large depth to ensure that the electrical and mechanical contact between the positionally stable metal region above the base layer zone and the adjacent, lowered metal silicide layer section is reliably broken off.
- a metal silicide layer is produced on the structuring layer.
- a metal silicide area (e.g. base electrode of a capacitor) is formed, which consists largely of metal silicide over the entire surface.
- the countersink layer zone of the structuring layer is thicker than the metal silicide layer. In particular, it can be about twice as thick as the metal silicide layer.
- a measure which can advantageously be carried out in both aspects of the invention is characterized in that an oxide layer formed during the oxidation in the countersink layer zone above the countersunk metal silicide layer section is removed again in a side wall region of the metal or metal silicide region. This also enables the exposed side wall area to be used to build up a capacitor, for example. This allows the effective (ie with the high-epsilon dielectric or ferroelectric in contact bringable) area of the base electrode and thus the capacitance of the capacitor may be increased considerably. Assuming a sufficient layer thickness of the metal or metal silicide layer, capacitors can be created whose vertical base electrode area exceeds the horizontal base electrode area.
- the invention is explained below using two exemplary embodiments with reference to the drawing,. in which the structuring of the metal layer serves to form a base electrode for a capacitor.
- the invention is not limited to this, but can e.g. can also be used in the manufacture of metallizations.
- Figure 1 is a schematic representation of a semiconductor layer sequence in the manufacture of a capacitor according to the first embodiment.
- FIG. 2 shows the layer sequence shown in FIG. 1 after creating a connection structure and applying a metal layer
- 3 shows the layer sequence shown in FIG. 2 after a local silicidation of the metal layer
- FIG. 4 shows the layer sequence shown in FIG. 3 after oxidation of the silicided metal layer sections
- FIG. 5 shows a schematic illustration of a layer sequence in the production of a capacitor according to the second exemplary embodiment
- FIG. 6 shows the layer sequence shown in FIG. 5 after a local oxidation of desired metal silicide layer sections
- the Si semiconductor substrate 1 can be p-doped, for example.
- An n + -doped drain region 3 is formed in the semiconductor substrate 1 and is separated from an n + -doped source region 4 via an intermediate channel 5 made of substrate material.
- a thin gate oxide layer 6 lies above the channel 5.
- a polysilicon gate electrode 7 is attached to the gate oxide layer 6.
- LOCOS technology (Local Oxidation of Silicon) realizes, spaced the described N-channel MOS transistor 3, 4, 5, 6, 7 from an adjacent transistor, not shown.
- the cover oxide layer 9 there is a cover oxide layer 9 above the Si semiconductor substrate 1, which in this exemplary embodiment is the substrate 9 forms.
- a structuring layer 10 is arranged on this.
- the structuring layer 10 has a base layer zone 11 arranged vertically above the drain region 3 and a recess layer zone 12 which laterally surrounds the base layer zone 11.
- the base layer zone 11 usually consists of silicon dioxide and the sink layer zone 12 is formed from silicon, in particular polysilicon. However, other materials that are largely inert to silicidation can also be used for the base layer zone 11.
- the lateral dimensions of the base layer zone 11 correspond to the desired horizontal dimensions of the base electrode of the capacitor to be manufactured.
- the zonal pattern of the structuring layer 10 is an image of the base electrode structure to be produced.
- a process control for producing the layer sequence 2.1 is explained below in an exemplary manner. In addition to the specified process steps, a large number of alternative and / or further process steps are possible.
- the covering oxide layer 9 is preferably deposited by a TEOS (tetra-ethyl-ortho-silicate) method or a PECVD (plasma enhanced CVD) method.
- TEOS tetra-ethyl-ortho-silicate
- PECVD plasma enhanced CVD
- silane oxide processes for example silane oxide processes, LTO (Low Temperature Oxide) processes, SAVCD (Sub-Atmospheric CVD), HTO (High Temperature Oxide)
- silane oxide processes for example silane oxide processes, LTO (Low Temperature Oxide) processes, SAVCD (Sub-Atmospheric CVD), HTO (High Temperature Oxide)
- SAVCD Low Temperature Oxide
- HTO High Temperature Oxide
- a continuous insulation layer is deposited on the top oxide layer 9, which later (ie after its structuring) forms the structuring layer 10.
- the insulation layer preferably also consists of SiO 2 , in which case the same layer production method and the same process step as in the formation of the cover oxide layer 9 can be used.
- trenches 13 for the countersink layer zones 12 are made in the insulation layer (or in the possibly (material) identical decoxide layer 9). Conventional lithographic and etching processes can be used for this.
- the trenches 13 are then filled with polysilicon, whereby the sink layer regions 12 are formed.
- the polysilicon is preferably deposited using a low-pressure CVD process.
- the applied polysilicon layer is etched back uniformly.
- a CMP (Chemical Mechanical Polishing) planarization can be carried out.
- FIG. 1 After the process steps described, the structure shown in FIG. 1 is present with a structuring layer 10 that is essentially flat on the surface side.
- a continuous metal layer 14 made of Pt, Ir, Ru, Os, Ti, Co or another suitable electrode metal is applied above the structuring layer 10.
- an oxidation mask 15 which consists for example of Si 3 N 4 and whose peripheral contour is essentially identical to the peripheral contour of the base layer zone 11.
- connection structure 16 which in the example shown here consists of tungsten.
- the connection structure 16 also passes through the cover oxide layer 9 and establishes an electrical connection between the drain region 3 and the metal layer 14.
- the process steps for building up the layer sequence 2.2 shown in FIG. 2 include the etching of a contact hole 17 into the structuring layer 10 and the cover oxide layer 9, the filling of the contact hole 17 with the material of the connection structure 16 (tungsten), various HF and / or sputtering Cleaning steps of the surface of the structuring layer 10, the deposition of the metal layer 14 and the deposition and structuring of the oxidation mask 15.
- the zone pattern of the structuring layer 10 is subsequently transferred into the metal layer 14 in the course of a silicidation step.
- the silicidation step is carried out in a protective gas atmosphere (inert gas) under the action of heat.
- a protective gas atmosphere inert gas
- the resulting metal silicide layer sections 18 are approximately twice as thick as the metal layer 14, they protrude into the trenches 13 on the underside.
- connection structure 16 consisting of polysilicon
- a silicidation of the metal layer 10 also takes place in the region above the connection structure 16. Since the metal silicide (for example CoSi 2 , TiSi 2 , PtSi) has a sufficiently good electrical conductivity to also be used as an electrode material, this can be quite acceptable or even desirable.
- the metal silicide for example CoSi 2 , TiSi 2 , PtSi
- the metal silicide for example CoSi 2 , TiSi 2 , PtSi
- the metal silicide for example CoSi 2 , TiSi 2 , PtSi
- a barrier layer between the connection structure 16 and the metal layer 14 is also used for a connection structure 16 made of W to protect the connection structure 16 against oxidation.
- the structuring of the metal layer 14 is carried out by oxidizing the metal silicide layer sections 18 in a further annealing step.
- the oxidation can take place at around 900 ° C in moist air and takes around 45 minutes.
- metal silicide layer sections 18 During the oxidation, silicon diffuses from the sinking layer zones 12 through the metal silicide layer sections 18, and a layer of silicon dioxide forms on the metal silicide layer sections 18.
- the metal silicide layer sections 18 thereby migrate into the sinking layer zones 12, i.e. they "sink” into this.
- the metal silicide layer sections 18 “sink” When the metal silicide layer sections 18 “sink”, their electrical and mechanical contact to the metal layer 14 lying above the base layer zone 11 breaks off; the base electrode 19 is thus created in accordance with the layer sequence 2.4 shown in FIG. 4.
- the exact mechanism for “sinking” "The metal silicide layer sections 18 is described in the already cited article by S. Mantl (Phys.Bl.51 (1995), pp. 951-953), the contents of which are hereby incorporated by reference in their entirety.
- the oxidation mask 15 can also be omitted in the process sequence shown in FIGS. 1-4, since there are no silicided, oxidizable metal layer regions above the base layer zone 11. However, the oxidation mask 15 is mandatory if one Connection structure 15 made of polysilicon without an overlying barrier layer is used.
- an isotropic Si0 2 etching back can be carried out to expose its side walls 19b, 19c, provided that these are also to be used as electrode surfaces.
- the oxidation mask 15 (if present) is removed by wet or plasma chemistry, so that the top-side surface 19a of the base electrode 19 is exposed.
- a high-epsilon dielectric or a ferroelectric for example PZT, SBT, ST or BST, is then deposited above the exposed wall regions 19a, 19b, 19c.
- a counterelectrode which can consist of the same material as the base electrode 19, is deposited in a manner not shown above the deposited high-epsilon dielectric / ferroelectric.
- FIG. 5 shows a view of a layer sequence 200.3 of a second exemplary embodiment of the invention. Parts corresponding to the first exemplary embodiment (FIGS. 1-4) are identified by the same reference symbols.
- the layer sequence 200.3 differs from the layer sequence 2.3 shown in FIG. 3 essentially only in that a metal silicide layer 114 is applied to the structuring layer 10 instead of a metal layer 14, and in that an oxidation mask 115 (for example made of Si 3 N) is provided, which with the exception of the sections 118 of the metal silicide layer 114 (vertically) lying above the sinking layer zones 12, which completely covers them.
- an oxidation mask 115 for example made of Si 3 N
- connection structure 16 consists of polysilicon and there is no barrier layer between the connection structure 16 and the metal silicide layer 114. For reasons of protecting the connection structure 16, however, its use is generally recommended.
- the metal silicide layer 114 can consist of CoSi 2 , TiSi 2 , PtSi or another technologically suitable metal silicide. It can be generated, for example, by sputtering a silicide target or by layer-by-layer sputtering of metal and silicon layer layers onto the structuring layer 10 and a subsequent tempering step (“annealing”).
- an oxidation step is carried out in an oxygen or water vapor atmosphere at an elevated temperature.
- the process parameters can be selected as specified in the first embodiment. As already explained, a layer of silicon dioxide forms on the exposed metal silicide layer sections 118, and the sections 118 migrate into the trenches 13.
- the contact between the metal silicide layer section 118 and the rest of the metal silicide layer 114 also breaks off here.
- FIG. 6 shows the structure shown in FIG. 5 after the oxidation step has been completed with “recessed” metal silicide layer sections 118 and structured base electrode 119 (layer sequence 200.4), which here represents the metal silicide region 119.
- the further processing for forming the capacitor is carried out in accordance with the above The procedure described in the first embodiment.
- the sunken metal silicide layer sections 18, 118 can also be used in a suitable manner as conductor tracks of the integrated circuit.
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00940148A EP1186029A2 (de) | 1999-04-27 | 2000-04-20 | Verfahren zum strukturieren einer metall- oder metallsilizidschicht sowie ein mit diesem verfahren hergestellter kondensator |
JP2000614506A JP3830762B2 (ja) | 1999-04-27 | 2000-04-20 | 金属層又は金属ケイ化物層の構造化法 |
US10/012,176 US6537900B2 (en) | 1999-04-27 | 2001-10-29 | Method for patterning a metal or metal silicide layer and a capacitor structure fabricated by the method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19919110A DE19919110C2 (de) | 1999-04-27 | 1999-04-27 | Verfahren zum Strukturieren einer Metall- oder Metallsilizidschicht sowie ein mit diesem Verfahren hergestellter Kondensator |
DE19919110.7 | 1999-04-27 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/012,176 Continuation US6537900B2 (en) | 1999-04-27 | 2001-10-29 | Method for patterning a metal or metal silicide layer and a capacitor structure fabricated by the method |
Publications (2)
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WO2000065658A2 true WO2000065658A2 (de) | 2000-11-02 |
WO2000065658A3 WO2000065658A3 (de) | 2001-03-29 |
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PCT/DE2000/001303 WO2000065658A2 (de) | 1999-04-27 | 2000-04-20 | Verfahren zum strukturieren einer metall- oder metallsilizidschicht sowie ein mit diesem verfahren hergestellter kondensator |
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US (1) | US6537900B2 (de) |
EP (1) | EP1186029A2 (de) |
JP (1) | JP3830762B2 (de) |
KR (1) | KR100427447B1 (de) |
CN (1) | CN1199260C (de) |
DE (1) | DE19919110C2 (de) |
WO (1) | WO2000065658A2 (de) |
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DE10207130B4 (de) * | 2002-02-20 | 2007-09-27 | Infineon Technologies Ag | Verfahren zur Herstellung eines Bauelements sowie Bauelement mit einer Edelmetallschicht, einer Edelmetallsilizidschicht und einer oxidierten Silizidschicht |
US7629247B2 (en) * | 2007-04-12 | 2009-12-08 | Sandisk 3D Llc | Method of fabricating a self-aligning damascene memory structure |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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US5366920A (en) * | 1993-04-12 | 1994-11-22 | Nec Corporation | Method for fabricating a thin film capacitor |
DE19503641A1 (de) * | 1995-02-06 | 1996-08-08 | Forschungszentrum Juelich Gmbh | Schichtstruktur mit einer Silicid-Schicht, sowie Verfahren zur Herstellung einer solchen Schichtstruktur |
EP0867926A1 (de) * | 1997-03-25 | 1998-09-30 | Siemens Aktiengesellschaft | Herstellverfahren für eine Kondensatorelektrode aus einem Platinmetall |
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JPS59100520A (ja) * | 1982-11-30 | 1984-06-09 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS6342164A (ja) * | 1986-08-08 | 1988-02-23 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
JP3108115B2 (ja) * | 1991-03-28 | 2000-11-13 | ロート製薬株式会社 | イムノクロマトグラフ法による物質検出法 |
JP3407204B2 (ja) * | 1992-07-23 | 2003-05-19 | オリンパス光学工業株式会社 | 強誘電体集積回路及びその製造方法 |
US5401677A (en) | 1993-12-23 | 1995-03-28 | International Business Machines Corporation | Method of metal silicide formation in integrated circuit devices |
DE19640244A1 (de) * | 1996-09-30 | 1998-04-02 | Siemens Ag | Kondensator mit einem Elektrodenkern und einer dünnen Edelmetallschicht als erster Elektrode |
DE19640246A1 (de) * | 1996-09-30 | 1998-04-02 | Siemens Ag | Halbleiteranordnung mit geschützter Barriere für eine Stapelzelle |
US5994736A (en) * | 1997-09-22 | 1999-11-30 | United Microelectronics Corporation | Semiconductor device having buried gate electrode with silicide layer and manufacture method thereof |
US6274511B1 (en) * | 1999-02-24 | 2001-08-14 | Advanced Micro Devices, Inc. | Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer |
-
1999
- 1999-04-27 DE DE19919110A patent/DE19919110C2/de not_active Expired - Fee Related
-
2000
- 2000-04-20 CN CNB008068305A patent/CN1199260C/zh not_active Expired - Fee Related
- 2000-04-20 KR KR10-2001-7013729A patent/KR100427447B1/ko not_active IP Right Cessation
- 2000-04-20 EP EP00940148A patent/EP1186029A2/de not_active Withdrawn
- 2000-04-20 JP JP2000614506A patent/JP3830762B2/ja not_active Expired - Fee Related
- 2000-04-20 WO PCT/DE2000/001303 patent/WO2000065658A2/de not_active Application Discontinuation
-
2001
- 2001-10-29 US US10/012,176 patent/US6537900B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5366920A (en) * | 1993-04-12 | 1994-11-22 | Nec Corporation | Method for fabricating a thin film capacitor |
DE19503641A1 (de) * | 1995-02-06 | 1996-08-08 | Forschungszentrum Juelich Gmbh | Schichtstruktur mit einer Silicid-Schicht, sowie Verfahren zur Herstellung einer solchen Schichtstruktur |
EP0867926A1 (de) * | 1997-03-25 | 1998-09-30 | Siemens Aktiengesellschaft | Herstellverfahren für eine Kondensatorelektrode aus einem Platinmetall |
Non-Patent Citations (1)
Title |
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PATENT ABSTRACTS OF JAPAN vol. 012, no. 254 (E-634), 16. Juli 1988 (1988-07-16) & JP 63 042164 A (HITACHI LTD), 23. Februar 1988 (1988-02-23) * |
Also Published As
Publication number | Publication date |
---|---|
JP3830762B2 (ja) | 2006-10-11 |
WO2000065658A3 (de) | 2001-03-29 |
CN1199260C (zh) | 2005-04-27 |
KR100427447B1 (ko) | 2004-04-17 |
DE19919110C2 (de) | 2002-06-27 |
CN1349658A (zh) | 2002-05-15 |
US20020064914A1 (en) | 2002-05-30 |
JP2002543592A (ja) | 2002-12-17 |
US6537900B2 (en) | 2003-03-25 |
KR20020015036A (ko) | 2002-02-27 |
EP1186029A2 (de) | 2002-03-13 |
DE19919110A1 (de) | 2000-11-09 |
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