Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
  • H10D30/65—Lateral DMOS [LDMOS] FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
  • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
  • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
  • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
  • H10D62/109—Reduced surface field [RESURF] PN junction structures
  • H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures

Definitions

• the invention relates to a lateral high-voltage transistor with a semiconductor body consisting of a weakly doped semiconductor substrate of one conductivity type and an epitaxial layer of the other provided on the semiconductor substrate, for one conductivity type of opposite conductivity type, a drain electrode, a source electrode, a gate electrode and one under the gate electrode provided and embedded in the epitaxial layer semiconductor zone of one conductivity type.
• This object is achieved according to the invention in a lateral high-voltage transistor of the type mentioned at the outset by trenches (trenches) arranged in rows and rows between the source electrode and the drain electrode in the epitaxial layer, the walls of which are highly doped with dopant of one conductivity type.
• the trenches are line by line between the source electrode and drain electrode on the surface of the epitaxial
• Layer with strip-shaped, lightly doped areas of one conductivity type interconnected At a. Layer thickness of the epitaxial layer of, for example, approximately 20 ⁇ m, the trenches have a depth of approximately 18 ⁇ m with a diameter of approximately 1 ⁇ m.
• the distance between rows of the trenches i.e. between trenches in the direction between the source electrode and drain electrode, is preferably dimensioned such that the area of the other conduction type is cleared between the rows of the trenches rather than the trenches or their walls of the one Line type to the epitaxial layer of the other line type reach the breakdown voltage.
• the lateral high-voltage transistor In the lateral high-voltage transistor according to the invention, it increases when a positive voltage is applied to the drain electrode.
• the space charge zone lies from the source electrode side in the direction of the drain electrode side with increasing voltage at the drain electrode.
• the floating trenches of one line type are located in rows on the
• the trenches are preferably, as already explained, line by line, connected on the surface of the semiconductor body with narrow s ⁇ ripe shaped regions of one conductivity type, 30 are lightly doped with one another.
• the trenches can form a structure which is ring-shaped or elongated, ellipsoidal, the drain electrode being arranged essentially in the middle of such a structure.
• Fig. 1 is a sectional view of the invention
• FIG. 2 shows a top view of the lateral high-voltage transistor from FIG. 1.
• An n-type epitaxial layer 2 is provided on a p ' -conducting silicon semiconductor substrate 1, in the surface of which an n + -conducting drain electrode connection region 3, to which a voltage + U D is applied, a p-type trough 4 and a n + conductive source electrode connection region 5 are introduced.
• the tub 4 and the area 5 are connected to ground.
• a gate electrode 7 with a contact G is arranged above a gate insulating layer 6 made of silicon dioxide, for example.
• connection area 5 for the source electrode are located between the connection area 5 for the source electrode and the connection area 3 for the
• Trenche drain electrode 8 which are introduced, for example, by etching into the epitaxial layer 2 and whose walls are highly doped with p + dopant, for example boron. This can be done by diffusion out of p-doped polycrystalline silicon or from a corresponding oxide filling.
• the trenches 8 are arranged in rows and rows (cf. FIG. 2), wherein they are connected to one another line by line on the surface with a narrow p " -conducting strip 9, as is indicated schematically in the top view of FIG. 2
• the trenches 8 are "floating" or potential-free and - as has been explained - are connected to one another line by line via the strips 9.
• connection area 3 When an increasing voltage + U D is applied to the connection area 3, the space charge zone increases from the side of the source electrode (connection area 5) towards the side of the drain electrode (connection area 3).
• the floating p-type trenches 8 are row by row at the potential with which the space charge zone reaches the corresponding row.
• the distance between the rows of trenches 8, that is to say in FIG. 1 between the trenches 8 shown there, is preferably such that the removal of charge carriers of the epitaxial layer 2 takes place between the rows rather than the trenches 8 to the n-conducting epitaxial layer 2 reach the breakdown voltage.
• the structure of the trench 8 can be designed in the manner of a ring or an elongated ellipse, the drain (cf. the connection region 3) being arranged in the middle of this structure.

Landscapes

• Insulated Gate Type Field-Effect Transistor (AREA)

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Applications Claiming Priority (2)

Related Child Applications (1)

Publications (1)

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ID=7871901

Family Applications (1)

Country Status (5)

Cited By (1)

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Citations (3)

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• 1998
  • 1998-06-24 DE DE19828191A patent/DE19828191C1/de not_active Expired - Fee Related
• 1999
  • 1999-03-17 EP EP99913117A patent/EP1008184A1/de not_active Withdrawn
  • 1999-03-17 WO PCT/DE1999/000761 patent/WO1999067826A1/de not_active Ceased
  • 1999-03-17 JP JP2000556403A patent/JP2002519852A/ja active Pending
• 2000
  • 2000-02-24 US US09/511,813 patent/US6326656B1/en not_active Expired - Lifetime

Patent Citations (3)

Non-Patent Citations (4)

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