WO1999060618A1 - Dispositif a semi-conducteurs et procede de fabrication dudit dispositif - Google Patents

Dispositif a semi-conducteurs et procede de fabrication dudit dispositif Download PDF

Info

Publication number
WO1999060618A1
WO1999060618A1 PCT/JP1999/002564 JP9902564W WO9960618A1 WO 1999060618 A1 WO1999060618 A1 WO 1999060618A1 JP 9902564 W JP9902564 W JP 9902564W WO 9960618 A1 WO9960618 A1 WO 9960618A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor
chips
memory
chip
semiconductor wafer
Prior art date
Application number
PCT/JP1999/002564
Other languages
English (en)
Japanese (ja)
Inventor
Kouichi Ikeda
Takeshi Ikeda
Original Assignee
T.I.F. Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by T.I.F. Co., Ltd. filed Critical T.I.F. Co., Ltd.
Publication of WO1999060618A1 publication Critical patent/WO1999060618A1/fr
Priority to US09/716,843 priority Critical patent/US6969623B1/en
Priority to US09/716,165 priority patent/US6479306B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a semiconductor device that can be mounted on a memory substrate, a motherboard, or the like, and a method for manufacturing the same.
  • a semiconductor chip such as a memory chip cut from a semiconductor wafer is generally mounted on a printed circuit board or the like in a packaged state.
  • the outer dimensions of the knockout are considerably larger than the size of various semiconductor chips themselves, there are certain restrictions on the number of packages that can be mounted on a printed circuit board or the like.
  • M CM M (M CM) is spreading.
  • the failure rate of each semiconductor chip is accumulated, and the failure rate of the module as a whole increases.
  • the entire module will be defective. Therefore, it was necessary to carry out repair work to replace the defective memory chip or to dispose of the entire module as a defective product, resulting in a low yield and a lot of waste.
  • each semiconductor chip is mounted on the substrate one by one, which complicates the manufacturing process.
  • An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can reduce the defect rate in manufacturing a semiconductor device that can be mounted and can simplify the process.
  • a semiconductor device is formed by performing a pass / fail inspection and cutting a semiconductor chip into one or more units according to the result. Since semiconductor chips are separated according to the results of the pass / fail inspection, when a semiconductor device composed of a plurality of semiconductor chips and capable of high-density mounting is manufactured, some of the semiconductor chips in the semiconductor devices are not acceptable. Since the semiconductor device is a non-defective product, the entire semiconductor device does not become defective, and the defect rate in manufacturing the semiconductor device can be reduced. Further, since a semiconductor device including a plurality of semiconductor chips can be used in a subsequent process, the subsequent process is simplified as compared with a case where a plurality of semiconductor devices including a single semiconductor chip are combined. can do.
  • FIG. 1 is a diagram showing a manufacturing process of the memory module of the first embodiment
  • FIG. 2 is a diagram schematically showing a memory chip formed on a semiconductor wafer
  • FIG. 3 is a diagram showing an example of a method for separating memory chips formed on a semiconductor wafer
  • FIG. 4 is a diagram showing a manufacturing process of the memory module of the second embodiment
  • Figure 5 is an enlarged cross-sectional view of a memory chip mounted with CSP.
  • FIG. 6 is a diagram showing a connection state between the mutually connected memory chips.
  • FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment.
  • FIGS. 1 (a) and 1 (b) a semiconductor wafer 2 which is, for example, a silicon single crystal flake is introduced, and the same memory chip 1 is formed on the semiconductor wafer 2 (first step). ).
  • Each area surrounded by a dotted line in FIG. 1B shows one unit of the memory chip 1 (minimum unit of division), and a plurality of memory chips 1 are formed on the semiconductor wafer 2.
  • FIG. 2 is a diagram schematically showing a memory chip 1 formed on a semiconductor wafer 2.
  • the memory chip 1 includes a semiconductor wafer 2 having a predetermined size and a plurality of chip pads 3 formed on the surface of the semiconductor wafer 2.
  • the chip pad 3 is a connection terminal for making an electrical connection with a substrate on which the memory chip 1 is mounted.
  • a pass / fail inspection is performed on each of the memory chips 1 (second step). For example, various functional tests are performed by pressing a test probe against a chip pad 3 formed on each memory chip 1 to make electrical contact therewith. Inspection efficiency is improved by performing the pass / fail inspection of each memory chip 1 on the whole semiconductor wafer 2 as a unit, that is, by conducting pass / fail inspection of a plurality of memory chips 1 formed on the semiconductor wafer 2 at one time. ing.
  • FIG. 3 is a diagram illustrating an example of a method for separating a plurality of memory chips 1 formed on a semiconductor wafer 2.
  • FIG. 3 (a) shows each memory chip in the second step described above.
  • FIG. 9 is a diagram showing the results of a pass / fail inspection of the memory chip 1, in which a mark ⁇ indicates a memory chip 1 determined to be good, and a mark X indicates a memory chip 1 determined to be defective.
  • FIG. 3B is a diagram showing how the memory chip 1 determined to be non-defective in FIG. 3A is cut out, and a range surrounded by a solid line indicates a unit of cutting. As described above, the memory chip 1 is divided into one or more (two or four) units, but it is preferable to divide as many units as possible.
  • the segmentation method shown in Fig. 3 (b) is divided into four when four memory chips 1 can be cut out, and two when four memory chips 1 cannot be cut out. If one memory chip 1 cannot be cut out, the procedure is to cut out only one.
  • this separation method is applied to the results of the pass / fail inspection shown in Fig. 3 (a), as shown in Fig. 3 (b), one set of four memory chips 1 is Three sets are obtained by cutting one memory chip 1, and three sets are obtained by cutting one memory chip 1. In this way, one or more semiconductor devices are manufactured.
  • the divided memory chip 1 is mounted on the substrate 4, and finally, the memory module 10a having four memory chips 1 and the memory module having two memory chips 1 are obtained.
  • Complete one of the module 10b and the memory module 10c taken out (fourth step).
  • a chip pad 3 formed on the memory chip 1 and an electrode (not shown) formed on the substrate 4 are connected using a bonding wire.
  • a memory module 10a having four memory chips 1 is a substrate on which the memory module 10a is mounted, assuming that the bit configuration of each memory chip 1 is 16M x 4 bits, for example.
  • Can be used as any of 16MX16-bit, 32-Mx8-bit, and 64Mx4-bit memory elements, depending on the wiring method of c) Can be handled in the same way as a single memory element, so that the process of mounting on another substrate or the like can be simplified.
  • a memory module 10b including two memory chips 1 implements the memory module 10b when the bit configuration of each memory chip 1 is 16M x 4 bits. Depending on the wiring method of the board to be mounted, it can be used as either a 16 MX 8-bit or a 32 MX 4-bit memory element. In addition, since the memory module 10b can be handled in the same manner as a single memory element, the process of mounting the memory module on another substrate or the like can be simplified.
  • a plurality of the same memory chips 1 are formed on the semiconductor wafer 2, and only those which are determined to be non-defective by the quality inspection are cut out of the memory chips 1 to manufacture the memory module 10.
  • the entire memory module 10 does not become defective because some of the memory chips 1 included in the memory module 10 are defective. Can be reduced.
  • the pass / fail inspection of the plurality of memory chips 1 formed on the semiconductor wafer 2 is performed at once for the entire semiconductor wafer 2, the efficiency of the inspection can be increased. Furthermore, the memory chip 1 is cut from the semiconductor wafer 2 in units of one or more (two or four), but as many as possible are cut into one unit, that is, four chips are cut as much as possible. Thus, the memory module 10a having four memory chips 1 can be efficiently manufactured.
  • the memory module 10a and the memory module 10b are mounted in such a manner that a plurality of the memory chips 1 formed on the semiconductor wafer 2 are collectively cut and separated-that is, a plurality of the memory chips 1 are connected to each other. Since they are mounted in a state, the memory chips 1 are cut out one by one from the semiconductor wafer 2, and compared with the case where the memory modules are formed by mounting the memory chips 1 at intervals, the components of the high-density mounting are reduced. The size can be reduced. In addition, since a plurality of semiconductor chips 1 can be mounted at one time, the manufacturing process can be simplified.
  • FIG. 4 is a diagram showing a manufacturing process of the memory module of the present embodiment.
  • FIGS. 4 (a) and (b) a semiconductor wafer 12 is introduced.
  • the same memory chip 11 is formed on the semiconductor wafer 12 (first step).
  • Each of a plurality of regions surrounded by a dotted line in FIG. 4 (b) indicates one unit (minimum unit of division) of the memory chip 11 after CSP mounting.
  • FIG. 4C CSP mounting is performed on the entire semiconductor wafer 12 in a state where a plurality of memory chips 11 are formed, and after forming wiring and resin sealing, forming terminals.
  • FIG. 5 is an enlarged cross-sectional view of the memory chip 11 mounted with CSP.
  • CSP-mounted memory chip 11 is composed of semiconductor wafer 12, wiring board 13, via 'post 14, norya' metal 15, resin layer 16, and solder ball It is composed including 1 7.
  • the wiring pattern 13 is formed by processing a metal thin film formed on the surface of the semiconductor wafer 12 with a resist, and then performing an electrolytic plating process.
  • the via post 14 is connected to the wiring pattern 13, and a barrier metal 15 is formed on the top of the via post 14.
  • the resin layer 16 seals the surface of the semiconductor wafer 12.
  • the resin layer 16 has a thickness substantially equal to the height of the via post 14, and the barrier metal 15 is exposed to the outside when the resin is sealed.
  • the solder ball 17 is a connection terminal for making an electrical connection with a substrate on which the memory chip 11 is mounted.
  • a pass / fail inspection of each memory chip 11 is performed (third step). For example, various functional tests are performed by pressing a test probe against a solder ball 17 formed corresponding to each memory chip 11 to make it electrically contact.
  • the inspection efficiency is improved. Is being improved.
  • the CSP mounting is performed, and among the memory chips 11 after the CSP mounting, the memory chips 11 are determined to be non-defective by the quality inspection.
  • the memory module 20 as a semiconductor device is manufactured by cutting only the memory module 20.Since some of the memory chips 11 included in the memory module 20 are defective, the entire memory module 20 is defective. Therefore, the defect rate when manufacturing the memory module 20 can be reduced.
  • the memory module 20a and the memory module 20b a plurality of memory chips 11 cut out from the semiconductor wafer 12 are mounted. For this reason, compared to the case where memory chips 11 are cut out from the semiconductor wafer 12 one by one and then mounted at intervals between the memory chips 1, memory components are reduced by high-density mounting. Becomes possible. In particular, since CSP mounting is used, the mounting area is minimized. Further, since the memory modules 20a and the like including as many memory chips 11 as possible are cut out based on the pass / fail pattern, it is possible to efficiently manufacture the multi-cavity memory modules 20a and the like. it can.
  • the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention.
  • the corresponding terminals may be connected to each other by wiring in each of the memory chips 1.
  • a common power supply voltage is applied to a power supply terminal of each memory chip 1, and a common operation clock signal is input to a clock terminal. If the terminals to which the same voltage is applied or the signals to which the same signal is input are connected when forming each memory chip 1 and four or two are cut out at the same time, four or two A common voltage is applied to any one of the memory chips 1 or a common signal is input.
  • the amount of wiring between the plurality of memory chips 1 and the board 4 on which the memory chips 1 are mounted can be reduced, and the mounting process can be simplified. become.
  • the same terminals of all the adjacent memory chips 1 are wired to each other. It is preferable to keep it.
  • the case where the power supply terminal and the clock terminal are connected to each other has been described, but other terminals, for example, the address terminal and the data terminal may be connected to each other.
  • the memory module 10 b that cuts out two memory chips 1 at the same time has 16 M x
  • An 8-bit bit configuration can be easily realized with a small amount of wiring
  • a memory module 10a that simultaneously cuts out four memory chips 1 can easily realize a 16-M x 16-bit bit configuration with a small amount of wiring.
  • the memory module 10b that cuts out two memory chips 1 at the same time is 3 2
  • the M x 4 bit configuration can be easily realized with a small amount of wiring
  • the memory module 10a that cuts out four memory chips 1 at the same time can easily realize the 64 MX 4-bit configuration with a small amount of wiring. Can be realized.
  • the corresponding terminals of the respective memory chips 11 included in the semiconductor wafer 12 of the second embodiment described above may be connected to each other by wiring.
  • the wiring formed when performing CSP mounting (the wiring pattern 13 shown in FIG. 5) ) May be used to connect the terminals of each memory chip 11 to each other.
  • the bit configuration of each memory chip 1 is 16 M ⁇ 4 bits
  • the force s may be other bit configurations
  • the memory chip 1 having a different bit configuration or capacity may be used. They may be combined.
  • the case where a memory chip is used as a semiconductor chip and a memory module as a semiconductor device is manufactured has been described as an example.
  • a semiconductor chip other than a memory chip for example, various chips such as a processor chip and an ASIC.
  • the present invention can be applied to the case where a semiconductor device is manufactured using a semiconductor device.
  • a plurality of or one memos are cut out one by one.
  • the rechip 1 is mounted on the substrate 4 to form the memory module 10, the memory chip 1 may be mounted directly on a motherboard or the like of a personal computer.
  • a semiconductor chip is separated from a semiconductor wafer in units of one or a plurality of units according to the result of a pass / fail inspection, so that a high-density mounting composed of a plurality of semiconductor chips is realized.
  • some of the semiconductor chips in them are defective, so that the entire semiconductor device does not become defective, reducing the defect rate when manufacturing semiconductor devices.
  • the subsequent The process can be simplified.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

On décrit un procédé de fabrication d'un dispositif à semi-conducteurs à forte densité d'intégration, qui inclut un processus simplifié mais capable de diminuer la proportion de défectueux. Une pluralité de puces mémoire identiques (1) sont formées sur une microplaquette de semi-conducteur (2) et un essai tout ou rien est effectué sur toutes les puces mémoire (1). La microplaquette de semi-conducteur (2) est découpée en pièces comportant chacune une, deux ou quatre puces mémoire viables (1) et ces pièces sont montées sur un substrat (4) pour former un module de mémoire (10).
PCT/JP1999/002564 1998-05-19 1999-05-18 Dispositif a semi-conducteurs et procede de fabrication dudit dispositif WO1999060618A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/716,843 US6969623B1 (en) 1998-05-19 2000-11-17 Semiconductor device and method for manufacturing the same
US09/716,165 US6479306B1 (en) 1998-05-19 2000-11-17 Method for manufacturing semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP10153818A JPH11330256A (ja) 1998-05-19 1998-05-19 半導体装置およびその製造方法
JP10/153818 1998-05-19

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1999/002565 Continuation WO1999060619A1 (fr) 1998-05-19 1999-05-18 Dispositif a semi-conducteurs et procede de fabrication dudit dispositif

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US09/716,843 Continuation US6969623B1 (en) 1998-05-19 2000-11-17 Semiconductor device and method for manufacturing the same
US09/716,165 Continuation US6479306B1 (en) 1998-05-19 2000-11-17 Method for manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
WO1999060618A1 true WO1999060618A1 (fr) 1999-11-25

Family

ID=15570772

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1999/002564 WO1999060618A1 (fr) 1998-05-19 1999-05-18 Dispositif a semi-conducteurs et procede de fabrication dudit dispositif

Country Status (3)

Country Link
JP (1) JPH11330256A (fr)
TW (1) TW457425B (fr)
WO (1) WO1999060618A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002082540A1 (fr) * 2001-03-30 2002-10-17 Fujitsu Limited Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe
JP2005072223A (ja) * 2003-08-25 2005-03-17 Casio Comput Co Ltd 半導体装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100806060B1 (ko) * 1999-11-29 2008-02-21 루센트 테크놀러지스 인크 멀티-칩 패키지들의 ｉｃ칩들의 클러스터 패키징
KR100699314B1 (ko) * 2002-01-28 2007-03-26 후지쯔 가부시끼가이샤 반도체 장치, 반도체 장치의 제조 방법, 및 반도체 기판
CN1624919A (zh) * 2003-12-05 2005-06-08 三星电子株式会社 具有整体连接器接触件的晶片级电子模块及其制造方法
JP2010192837A (ja) * 2009-02-20 2010-09-02 Showa Denko Kk 半導体ウェーハのダイシング方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935586B1 (fr) * 1968-12-14 1974-09-24
JPH06334034A (ja) * 1993-05-21 1994-12-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH09199450A (ja) * 1996-01-22 1997-07-31 Oki Electric Ind Co Ltd ウエハ上の半導体素子ダイシング方法及び装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4935586B1 (fr) * 1968-12-14 1974-09-24
JPH06334034A (ja) * 1993-05-21 1994-12-02 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH09199450A (ja) * 1996-01-22 1997-07-31 Oki Electric Ind Co Ltd ウエハ上の半導体素子ダイシング方法及び装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002082540A1 (fr) * 2001-03-30 2002-10-17 Fujitsu Limited Dispositif a semi-conducteurs, son procede de fabrication et substrat semi-conducteur connexe
US6972487B2 (en) 2001-03-30 2005-12-06 Fujitsu Limited Multi chip package structure having a plurality of semiconductor chips mounted in the same package
JP2005072223A (ja) * 2003-08-25 2005-03-17 Casio Comput Co Ltd 半導体装置

Also Published As

Publication number Publication date
JPH11330256A (ja) 1999-11-30
TW457425B (en) 2001-10-01

Similar Documents

Publication Publication Date Title
KR100843214B1 (ko) 메모리 칩과 프로세서 칩이 관통전극을 통해 연결된 플래너멀티 반도체 칩 패키지 및 그 제조방법
USRE36773E (en) Method for plating using nested plating buses and semiconductor device having the same
US7257884B2 (en) Method for fabricating semiconductor component with adjustment circuitry for electrical characteristics or input/output configuration
US20050104182A1 (en) Stacked BGA packages
KR100843213B1 (ko) 메모리 칩과 프로세서 칩이 스크라이브 영역에 배열된관통전극을 통해 연결된 다중 입출력 반도체 칩 패키지 및그 제조방법
US20100102440A1 (en) High density three dimensional semiconductor die package
US6677219B2 (en) Method of forming a ball grid array package
KR19990006158A (ko) 볼 그리드 어레이 패키지
US6855573B2 (en) Integrated circuit package and manufacturing method therefor with unique interconnector
US6969623B1 (en) Semiconductor device and method for manufacturing the same
WO1999060618A1 (fr) Dispositif a semi-conducteurs et procede de fabrication dudit dispositif
JP2003174122A (ja) 半導体装置
WO1999026288A1 (fr) Dispositif a semi-conducteur et son procede de fabrication
WO1999060619A1 (fr) Dispositif a semi-conducteurs et procede de fabrication dudit dispositif
US6924557B2 (en) Semiconductor package
JP3977014B2 (ja) 半導体装置およびその製造方法
WO1999026289A1 (fr) Dispositif a semi-conducteur et son procede de production
JP2000260931A (ja) 半導体装置およびその製造方法
CN107205315B (zh) 印刷电路板以及组件制造方法
US7199460B2 (en) Semiconductor device and method of manufacturing the same
US6159774A (en) Multi-layer interconnection layout between a chip core and peripheral devices
JPH07183320A (ja) ボンディングワイヤ接続構造及びボンディングワイヤ接続方法
JPH1093009A (ja) 半導体チップモジュール、マルチチップモジュールおよび電子機器
WO1985001390A1 (fr) Tranche
JP2002373958A (ja) 半導体チップの実装構造及び半導体チップの実装方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 09716843

Country of ref document: US

Ref document number: 09700623

Country of ref document: US

Ref document number: 09716165

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: KR

122 Ep: pct application non-entry in european phase