WO1999026289A1 - Dispositif a semi-conducteur et son procede de production - Google Patents

Dispositif a semi-conducteur et son procede de production Download PDF

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Publication number
WO1999026289A1
WO1999026289A1 PCT/JP1998/000813 JP9800813W WO9926289A1 WO 1999026289 A1 WO1999026289 A1 WO 1999026289A1 JP 9800813 W JP9800813 W JP 9800813W WO 9926289 A1 WO9926289 A1 WO 9926289A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
memory
substrate
semiconductor
chips
Prior art date
Application number
PCT/JP1998/000813
Other languages
English (en)
Japanese (ja)
Inventor
Kouichi Ikeda
Takeshi Ikeda
Original Assignee
T.I.F. Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by T.I.F. Co., Ltd. filed Critical T.I.F. Co., Ltd.
Publication of WO1999026289A1 publication Critical patent/WO1999026289A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Definitions

  • the present invention relates to a semiconductor device that can be mounted on a memory substrate, a motherboard, or the like, and a method for manufacturing the same.
  • a multi-chip module is formed by mounting a plurality of semiconductor chips on a substrate.
  • the semiconductor chip mounted on the packaged semiconductor chip module board is subjected to a pass / fail inspection in units of one or a plurality of units.
  • the present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of improving the efficiency of a semiconductor chip quality test and a method of manufacturing the same.
  • a semiconductor device is provided by mounting a plurality of semiconductor chips (preferably memory chips) on a substrate, performing a quality inspection of each semiconductor chip in a resin-sealed state, and then dividing the semiconductor chip into a predetermined number of units. Is formed. Since the quality inspection of semiconductor chips is performed on a substrate basis, the efficiency of inspection can be increased as compared with the case where one or a small number of semiconductor chips are individually inspected.
  • a plurality of semiconductor chips are mounted on one surface of the substrate, and the quality of each semiconductor chip is inspected via terminals formed on the other surface.
  • the entire board is treated as one component, and multiple semiconductors mounted on it are handled. Since the quality of semiconductor chips can be inspected, the quality of the semiconductor chips can be compared with the quality of semiconductor chips individually packaged or the semiconductor substrate on which multiple semiconductor chips are mounted. The required labor can be reduced.
  • FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment
  • FIG. 2 is a view showing a partial structure of the substrate before the memory bay chip is mounted.
  • FIG. 3 is a view showing a state where the memory bay chip is mounted on the board shown in FIG. 2.
  • FIG. 4 is a view showing the results of a pass / fail inspection of the memory bay chip mounted on the board
  • FIG. 5 is a view showing a connection state between the memory bay chip and the board in the case of flip chip mounting
  • FIG. 6 is a diagram showing a cross section of a memory bare chip having a CIB structure and a substrate
  • FIG. 7 is a diagram illustrating an outline of resin molding by transfer molding
  • FIG. 8 is using an LCC type external connection terminal Figure showing the partial structure of the memory module in the case
  • FIG. 9 is a diagram for explaining a process of forming the external connection terminals when using the LCC type external connection terminals.
  • FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment.
  • the memory module 10 as a semiconductor device includes a memory bare chip (memory chip) 1 cut out from a semiconductor wafer, a substrate 2 on which the memory bare chip 1 is mounted, and a substrate. And a resin 3 for sealing the surface on which the memory chip 2 is mounted.
  • a substrate 2 is introduced, and a plurality of memory bare chips 1 are arranged on one side of the substrate 2 at predetermined intervals vertically and horizontally. (1st step).
  • COB Chip On Board
  • FIG. 2 is a diagram showing a partial structure of the substrate 2 before the memory bay chip 1 is mounted.
  • 1A shows the surface on which the memory carrier 1 is mounted
  • FIG. 2B shows the opposite surface (back surface)
  • FIG. 1C shows the structure viewed from the side.
  • the board 2 is provided with a board pad 11 necessary for making an electrical connection with the memory bare chip 1 for each predetermined area where the memory bear chip 1 is mounted.
  • the substrate pad 11 is electrically connected to a BGA (Ball Grid Array) pad 13 on the rear side through a through hole 12.
  • BGA All Grid Array
  • FIG. 3 is a view showing a state in which the memory bare chip 1 is mounted on the substrate 2 shown in FIG. 2 in the first step.
  • FIG. 3 (a) shows the mounting surface of the memory bear chip 1
  • FIG. 3 (b) shows the structure viewed from the side.
  • Each memory tape 1 is a DRAM having a capacity of, for example, 16 M ⁇ 4 bits, and a chip pad 14 is formed on the surface thereof in a line in the center along the long side. Have been.
  • the chip pads 14 are connected to the substrate pads 11 formed on the substrate 2 by using bonding wires 15. COB mounting using such bonding wires 15 is performed on each memory chip 1.
  • the resin 3 is poured into the surface of the substrate 2 on which the memory bare chip 1 is mounted, as shown in FIG.
  • the memory chip 1 is sealed with the resin 3 (second step).
  • each memory bear chip 1 is sealed with the resin 3 to prevent disconnection and short circuit of the bonding wires 15 connected to the memory bear chip 1.
  • the resin 3 has a predetermined thickness, variations in the height of the manufactured memory module 10 are suppressed.
  • a pass / fail inspection of each memory bare 1 is performed (third step). For example, by pressing an inspection probe against a BGA pad 13 formed on the back surface of the substrate 2 to make electrical contact therewith, Perform some functional tests.
  • the pass / fail inspection of the memory bay chip 1 as a unit of the entire board 2, that is, by conducting pass / fail inspection of a plurality of memory bays 1 mounted on the board 2 at one time, Improving efficiency.
  • FIG. 4 is a diagram showing the results of a pass / fail inspection (third step) of the memory bare chip 1 mounted on the substrate 2, where a mark ⁇ indicates a memory bare chip 1 determined to be non-defective, and a mark X indicates non-defective. Each of the bare chips 1 for memory that have been determined to be non-defective is shown.
  • a plurality of memory bare chips 1 mounted on the substrate 2 are collectively inspected, and a matrix-like inspection result indicating the quality of the inspection is obtained.
  • defective products are removed from the separated memory modules 10 and only non-defective products are taken out.
  • the pass / fail inspection of a plurality of memory bare chips 1 mounted on the board 2 is performed collectively for the entire board 2 as a unit. Inspection efficiency can be increased as compared with the case where quality inspection is performed.
  • memory bare chips can be cut in units of one or more (two or four). -Can be manufactured efficiently.
  • FIG. 5 is a diagram showing a connection state between the bare memory chip 1 and the substrate 2 in the case of flip-chip mounting.
  • the board pads formed on the mounting surface of the memory bare chip 1 and the chip pads formed on the surface of the board 2 on which the memory bare chip 1 is mounted face each other and are connected by bumps 21.
  • flip chip mounting is performed. According to the flip-chip mounting, further high-density mounting is possible, so that the outer dimensions of the manufactured memory module 10 are further reduced. It becomes possible to cut.
  • DRAMs and other semiconductor chips will have shorter wiring lengths because of their higher operating speeds, but shorter wiring lengths will be realized by adopting flip mounting. Can be.
  • each bare chip 1 for memory may be housed in the substrate 2 to have a CIB (Chip In Board) structure in which the bonding wires 15 and the like are not exposed to the outside.
  • FIG. 6 is a diagram showing a cross section of a memory bear chip 1 having a CIB structure and a substrate 2. As shown in the figure, a concave portion is formed in the substrate 2, a memory chip 1 is mounted inside the concave portion, and the substrate pad 11 and the chip pad 14 are substantially flush with each other.
  • FIG. 7 is a view for explaining resin molding by transfer molding.
  • FIG. 7 (a) shows a case where flat resin molding is performed on the entire substrate 2, and
  • FIG. ) Shows a case in which a groove is provided along a dividing line.
  • Transfer molding resin molding is suitable for mass production because the molding time can be shortened.
  • the BGA pad 13 is used as the external connection terminal of the memory module 10.
  • a so-called LCC (Leadless Chip Carrier) type terminal may be used.
  • FIG. 8 is a diagram showing a partial structure of the memory module 10 when an external connection terminal of the LCC system is used. As shown in the figure, a concave portion is formed in one side (or in both directions) of the longitudinal direction or the horizontal direction on the side surface of the memory module or the module 10 after the separation, and the surface of the concave portion is formed. Metal cover to cover As a result, the external connection terminal 31 is formed.
  • FIG. 9 is a view for explaining a process of forming the external connection terminal 31 of the LCC system.
  • the substrate 2a has through holes 3 along one or both of the dividing lines for separating the mounted memory bare chip 1 in the vertical or horizontal direction. 2 are formed.
  • the external connection terminals 31 may be clogged by the poured resin 3 during the resin sealing in the second manufacturing process described above. May occur. Therefore, as shown in FIG. 3B, a protective member such as an insulating tape 33 is formed along the through hole 32 to prevent the resin 3 from flowing into the through hole 32. .
  • solder or the like may be poured into each through hole 32 in advance so that clogging with the resin does not occur later. Thereafter, the above-described through-hole 32 is cut at the center thereof to form the external connection terminal 31 shown in FIG.
  • a flexible substrate or other various substrates may be used as the substrate 2 used in the above-described embodiment.
  • a case where a memory chip is used as a semiconductor chip and a memory module as a semiconductor device is manufactured has been described as an example.
  • various types of semiconductor chips other than the memory chip such as a processor chip and an ASIC, may be used. It can be applied when mounting a chip on a substrate.
  • the memory bare chips 1 to be separated from the substrate 2 may not be separated one by one, but may be separated into two or more predetermined chips.
  • the quality of semiconductor chips is inspected in units of the entire board on which a plurality of semiconductor chips are mounted, so that one or a small number of semiconductor chips are individually inspected. Inspection efficiency can be increased as compared with the above.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Memories (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

L'invention concerne un dispositif à semi-conducteur avec lequel on peut réaliser des contrôles de qualité plus efficaces concernant chaque puce de semi-conducteur, ainsi qu'un procédé de production de ce dispositif à semi-conducteur. Selon ledit procédé, plusieurs puces (1) nues identiques, destinées à une mémoire, sont montées par pastillage sur un substrat (2), et la surface dudit substrat (2) équipée de ces puces (1) est encapsulée avec une résine (3). Ensuite, les puces (1) montées sur le substrat (2) sont soumises en même temps à un contrôle de qualité, et chaque module mémoire (10) est découpé et divisé.
PCT/JP1998/000813 1997-11-18 1998-02-27 Dispositif a semi-conducteur et son procede de production WO1999026289A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP9/333656 1997-11-18
JP33365697 1997-11-18

Publications (1)

Publication Number Publication Date
WO1999026289A1 true WO1999026289A1 (fr) 1999-05-27

Family

ID=18268505

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1998/000813 WO1999026289A1 (fr) 1997-11-18 1998-02-27 Dispositif a semi-conducteur et son procede de production

Country Status (2)

Country Link
TW (1) TW399276B (fr)
WO (1) WO1999026289A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373952A (ja) * 2001-06-15 2002-12-26 Seiko Instruments Inc 気密封止ｉｃパッケージの製造方法
JP2003007888A (ja) * 2001-06-18 2003-01-10 Seiko Instruments Inc 気密封止ｉｃパッケージの製造方法
JP2004138391A (ja) * 2002-10-15 2004-05-13 Renesas Technology Corp 半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661417A (ja) * 1992-06-10 1994-03-04 Origin Electric Co Ltd 半導体装置，電子回路装置，それらの製造方法および製造装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0661417A (ja) * 1992-06-10 1994-03-04 Origin Electric Co Ltd 半導体装置，電子回路装置，それらの製造方法および製造装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373952A (ja) * 2001-06-15 2002-12-26 Seiko Instruments Inc 気密封止ｉｃパッケージの製造方法
JP2003007888A (ja) * 2001-06-18 2003-01-10 Seiko Instruments Inc 気密封止ｉｃパッケージの製造方法
JP2004138391A (ja) * 2002-10-15 2004-05-13 Renesas Technology Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
TW399276B (en) 2000-07-21

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