WO1999031722A1 - Barriereschicht für kupfermetallisierung - Google Patents
Barriereschicht für kupfermetallisierung Download PDFInfo
- Publication number
- WO1999031722A1 WO1999031722A1 PCT/EP1998/008255 EP9808255W WO9931722A1 WO 1999031722 A1 WO1999031722 A1 WO 1999031722A1 EP 9808255 W EP9808255 W EP 9808255W WO 9931722 A1 WO9931722 A1 WO 9931722A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- blocker
- electrical circuit
- layer
- diffusion
- integrated electrical
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the invention relates to an integrated electrical circuit with a plurality of structure levels, in which there are electrically active elements on at least one element structure level, at least one insulation layer being arranged above the element structure level, electrical connection lines being arranged inside and / or above the insulation layer are, wherein at least a part of the connecting lines contains so much copper that copper is dominant for the properties of these connecting lines, and wherein at least one diffusion blocker is arranged below the connecting lines, which hinders and / or prevents the diffusion of copper.
- the invention further relates to a method for producing such an integrated electrical circuit.
- an RC element is formed from the resistance R of a conductor track and its capacitance C, which depends on the material surrounding it and its geometry.
- the damping and resonance effects of this RC element impair the signal propagation in the integrated electrical circuit.
- the diameter of the conductor track decreases considerably. Since the length of the conductor tracks is changed only slightly at the same time, the resistance R of the conductor track increases. This increases the undesirable resonance and damping effects in the case of integrated electrical circuits with smaller structure sizes.
- barrier layer has a minimum layer thickness in order to prevent diffusion of the copper into the substrate in which it is located. In order to effectively prevent diffusion, the barrier layer must not be less than a certain thickness. A sufficient thickness of the barrier layer to prevent diffusion means that only a small part of the web cross section consists of copper. Since all known barrier layers have a significantly higher specific resistance than copper, the effective electrical conductivity thus decreases undesirably as the width of the contact holes progressively narrows.
- the object of the invention is to avoid the disadvantages of the prior art.
- it is the object of the invention to create an integrated electrical circuit in which an undisturbed power line is achieved even with small structure sizes. Even with a high one Signal frequency, resonance and damping effects should be as low as possible. Furthermore, a diffusion of copper atoms into the semiconductor substrate is to be effectively avoided.
- this object is achieved in a generic integrated electrical circuit in that the diffusion blocker is designed as a blocker layer interrupted only in the area of contact holes, and in that the blocker layer is located between the element structure level and the insulation layer.
- the invention therefore provides to provide an integrated electrical circuit in which there is a continuous layer between a copper-containing connecting line and electrically active elements, and that there is at least one insulation layer between this layer and a connecting line.
- a diffusion barrier for copper is preferably effective on the surface of the contact holes at least below the blocker layer.
- This diffusion barrier can be realized in that the contact holes are filled with a conductive material that has a diffusion barrier effect for copper.
- This material can in particular be tungsten or titanium nitride.
- this diffusion barrier can be realized by a thin layer which lines the side walls and the bottom of the contact hole and has the diffusion barrier effect for copper. Titanium / titanium nitride, titanium nitride, tantalum nitride or the like is particularly suitable for the thin layer.
- This thin layer can be realized by an adhesive layer, as is often used when filling contact holes with tungsten.
- the thin layer has a thickness of 50 to 200 nm, preferably 50 to 100 nm.
- the diffusion barrier on the surface of the contact holes forms together with the blocker layer ne continuous layer with diffusion barrier effect against copper. In this way it is effectively avoided that copper atoms get into the semiconductor substrate.
- the copper-containing connecting line is separated from the semiconductor substrate by a closed diffusion barrier layer, which is formed from the blocker layer and the diffusion barrier effective on the surface of the contact holes.
- the connecting lines can be both conductor tracks and electrical contacts.
- the conductor tracks preferably extend within a structural level and serve to connect different active electrical elements to one another or to contacts located outside the actual integrated electrical circuit. They can be part of an assembly of layers of conductive and insulating materials that are laterally multiply structured and built up above the active elements. This whole is also referred to as metallization.
- Connection lines which serve as direct electrical contacts are preferably formed by contact holes filled with a conductive material. These contact holes preferably extend perpendicular to the structural planes from which the integrated electrical circuit is constructed.
- the connecting lines contain so much copper that copper is dominant for the properties of the connecting lines. It is fundamentally possible for the connecting lines to consist entirely of copper. However, it is also possible for the connecting lines to be formed from a material which contains copper only as a fraction and which also contains additives, for example made of zirconium. has conium, hafnium or the like. According to the invention, however, this proportion is so large that the copper is present in a content which is sufficient to significantly increase the electrical conductivity of the material. For this purpose, it is expedient that the copper content in the connecting lines is at least 10 percent by weight.
- the copper is present in a concentration that is higher than is required to improve the process properties of the production process of a conductor track, so that the properties, in particular the electrical conductivity, the etching behavior, the adhesion, the nucleation, the deposition properties, the surface properties and the like, the connecting lines are determined by the copper. Copper-specific processes may therefore be required when manufacturing these connecting lines. In order to exploit the potential of the copper-containing connecting lines, it is advantageous to provide a copper content of greater than or equal to 90 percent by weight in the connecting lines.
- a diffusion blocker is located below the connecting lines. However, at least one insulation layer is arranged between the connecting lines and the diffusion blocker.
- the insulation layer can be constructed from any material. In order to achieve the lowest possible RC constant of the connecting line, however, it is expedient that the dielectric constant of the material used for the insulation layer is as low as possible.
- the lowest possible dielectric constant of the insulation layer can be achieved if it consists of air or an airgel. However, materials that can be more easily integrated into the manufacturing process also have a suitable low dielectric constant.
- teroxides such as Si0 2
- semiconductor nitrides such as SiJJj
- fluorinated semiconductor oxides such as SiOF
- fluorinated (amorphous) carbon fluorinated (amorphous) carbon
- nitrides such as boron nitride
- polymers and polymer compounds such as polyimides, in particular fluorinated polyimides, polystyrenes, polyethylenes, polycarbonates, polybenzoxazole (PBO) benzocyclobutene (BCB), Parylene, fluoropolymers such as tetrafluerethylene.
- the blocker layer is located below the insulation layer. As a result, the blocker layer is spatially separated from the connection lines. The result of this configuration is that copper atoms can penetrate into the insulation layer. The invention therefore does not rule out the partial penetration of individual copper atoms in the insulation layer. It has been shown that such a slight penetration of copper atoms into the insulation layer does not impair the functionality of the integrated electrical circuit.
- the blocker layer serving as a diffusion blocker can in principle be formed from any material.
- a material is expediently used which has a diffusion length for copper which is smaller than the thickness of the blocker layer at the usually occurring process temperatures of m, as a rule, above 400 degrees Celsius.
- the blocker layer contains nitrogen, oxygen, fluorine or a compound of these elements.
- Suitable materials for the blocker layer are, for example, nitrides such as silicon nitride S ⁇ JST 4 , oxidized nitrides such as silicon oxynitride SiON, silicon boroxynitride SiBON, T ⁇ N x O y , TaN x O y , WN x Oy, WS ⁇ x N, fluorinated nitrides such as silicon fluoroxymtride SiOFN and metal oxides such as T ⁇ 0 2 , Ta 2 0 5 . It is particularly expedient that the thickness of the blocker layer is between 50 nm and 800 nm.
- a minimum layer thickness of approximately 100 nm is sufficient in most cases to effectively prevent diffusion of copper atoms into the plane of the electrically active elements.
- One possible upper limit for the layer thickness is thereby give ge ⁇ that an undesirable increase of the lateral Koppelka- pazticianem and an unfavorable geometric shape of the insulating layer is to be avoided.
- the invention also includes the case that several blocker layers are provided. These blocker layers can be located on different structural levels and have a different degree of diffusion hindrance or diffusion prevention.
- At least one further diffusion blocker prefferably be in contact with at least part of the connecting lines.
- the further diffusion blocker can have any shape. However, it is particularly advantageous that the further diffusion blocker rests on the side surfaces and / or the lower edges of at least some of the connecting lines. This part of the connecting lines can be both the conductor tracks and the electrical contacts.
- the further diffusion blocker (s) in such a way that they prevent massive diffusion of the copper into the insulation layer and that the blocker layer has a greater degree of diffusion impediment.
- This configuration can be achieved in a particularly simple and expedient manner in that the blocker layer is thicker than the further diffusion blocker.
- the invention further relates to a method for producing an integrated electrical circuit
- connection lines which contain so much copper that copper is dominant for the properties of the connection lines, are produced within and / or on the insulation layer, - in which at least one diffusion blocker is applied below the connection lines.
- This method is carried out in accordance with the invention in such a way that the diffusion blocker is deposited as a continuous blocker layer before the insulation layer is produced, and that the insulation layer is produced on this blocker layer.
- FIG. 1 shows a cross section through an integrated electrical circuit according to the invention, with a blocker layer which is interrupted by contact holes filled with tungsten, 2 shows a detail of Figure 1 in the area of a filled j ⁇ th contact hole,
- FIG. 3 shows an integrated electrical circuit with a blocker layer, which is interrupted by contact holes and connecting pieces filled with tungsten, and
- FIG. 4 shows a detail from FIG. 3 in the area of a contact hole.
- field effect transistors 20, 30 and 40 are located on a semiconductor substrate 10, which is preferably made of silicon.
- the field effect transistors 20, 30 and 40 each have source and drain regions 50, 60, 70, 80, 90 and 100 and gate electrodes 120, 130 and 140.
- an insulation layer 150 which is in particular an intermediate oxide, for example a flowable one Planarization oxide such as borophosphosilicate glass (BPSG) can be formed.
- BPSG borophosphosilicate glass
- the intermediate oxide can be replaced by any other insulating material.
- borophosphosilicate glass has the particular advantage that, owing to its flowability, a process of chemical-mechanical planarization to produce a planar surface may be omitted.
- a 150 nm thick blocker layer 160 for example made of silicon oxynitride SiON, is arranged above the insulation layer 150.
- the blocker layer 160 is arranged above the entire surface of the semiconductor substrate 10 and only in the region of contact holes 170, 180, 190, 200, 210 and 220 interrupted.
- the contact holes 170, 180, 190, 200, 210 and 220 are preferably completely covered by a conductive Mate ⁇ rial, for example a metal, preferably tungsten or a tungsten alloy is filled.
- tungsten fill 230 of a contact hole 240 and the layers delimiting the contact hole, i. the insulation layer 150 and the blocker layer 160 an approximately 100 nm thick adhesive layer 165 made of a titanium / titanium nitride alloy.
- the adhesive layer 165 serves as a seeding layer for subsequent deposition processes, in particular for filling the contact holes 170, 180, 190, 200, 210, 220 and 240, for example with tungsten.
- the adhesive layer 165 protects the material lying below the bottom of the contact hole.
- connection pieces 250, 260, 270, 280, 290, 300 and 310 directly on the blocker layer made of a material which has a high conductivity with a low Dif ⁇ fusion tendency connects, for example aluminum.
- the insulation layer 320 which is also referred to as intermetallic oxide.
- the insulation layer 320 ie here the inert metal oxide
- CVD Chemical Vacuum Deposition
- Contact holes 330, 340, 350, 360 and 370 are also etched into the insulation layer 320.
- connection pieces 390 and 400 as well as an interconnect 410 made of copper.
- contact holes 420 and 430 in the insulation layer 380 are completely filled with tungsten or copper.
- Connections 440 and 450 made of copper are also arranged above the contact holes 420 and 430. They are located in an intermetallic dielectric 460 above the insulation layer 380, which consists, for example, of silicon oxide SiO 2 .
- Field-effect transistors 20, 30 and 40 with source and drain regions 50, 60, 70, 80, 90 and 100 and with gate electrodes 120, 130 and 140 are produced in a known manner in the region of a main area of a semiconductor substrate 10.
- An insulation layer 150 is then produced, for example, by flowing a flowable planarization oxide such as boron phosphorus silicate glass (BPSG) or by an application process such as plasma-assisted CVD: PECVD (Plasma Enhanced Chemical Vapor Deposition) process.
- a flowable planarization oxide such as boron phosphorus silicate glass (BPSG)
- PECVD Plasma-assisted Chemical Vapor Deposition
- Blocker layer 160 An approximately 100 nm thick layer is applied to the insulation layer 150 Blocker layer 160 applied.
- the blocker layer 160 - for example made of silicon oxynitride SiON - can preferably be produced by a PECVD process.
- a major advantage of the PECVD process is that it can also be carried out at temperatures below 500 ° C. Free radicals are generated in a plasma. These are silicon, oxide and nitride radicals during the deposition of a SiON layer. Silane (SiH 4 ), ammonia (NH 3 ) and oxygen are used to carry out the process.
- the blocker layer 160 is deposited at a pressure in the range from approximately 20 to 100 Pa, preferably approximately 30 Pa, and a temperature below 500 ° C., preferably approximately 300 ° C.
- contact holes 170, 180, 190, 200, 210, 220 and 240 are preferably etched in a reactive plasma in a reactive plasma in the insulation layer 150 and in the blocker layer 160.
- a gas mixture of CHF 3 and 0 2 or of CHF 3 and CF 4 is used as the etchant.
- An approximately 100 nm thick adhesive layer 165 made of a titanium / titanium nitride alloy is then deposited.
- the contact holes 170, 180, 190, 200, 210, 220 and 240 are then filled with tungsten or copper.
- connecting pieces 250, 260, 270, 280, 290, 300 and 310 which can also be connecting elements, are applied, for example by sputtering and subsequent structuring of a metal layer.
- a structuring process according to a conventional photolithographic method structures the part of the adhesive layer 165 lying above the blocker layer 160 as well as the connecting pieces 250, 260, 270, 280, 290, 300 and 310.
- An insulation layer 320 is then deposited onto the blocker layer 160 and the connecting pieces 250, 260, 270, 280, 290, 300 and 310 by a suitable deposition method, such as plasma enhanced chemical vapor deposition (PECVD).
- PECVD plasma enhanced chemical vapor deposition
- Connectors 390 and 400 made of copper as well as a conductor track 410 serving to connect the contact holes 350 and 360, which also consists of copper, are produced in the manner shown below.
- a copper layer of 300 nm to 600 nm thickness is applied to the layer 320 by means of a sputtering (sputtering) process.
- a paint mask is applied and structured using photolithographic process steps.
- contact holes 420 and 430 are preferably etched into the insulation layer 380 by a dry etching process in a reactive plasma. For example, a gas mixture of CHF 3 and 0 2 or CHF ? and CF 4 used. The contact holes 420 and 430 are then filled with copper. Copper and copper connectors 440 and 450 are then applied to contact holes 420 and 430.
- a further level 460 is then applied, which is formed, for example, by an intermetallic dielectric such as SiO 2.
- field effect transistors 520, 530 and 540 on a semiconductor substrate 510, preferably made of silicon.
- the field effect transistors 520, 530 and 540 each have source and drain regions 550, 560, 570, 580, 590 and 600 as well as gate electrodes 620, 630 and 640.
- an insulation layer 650 between the field effect transistors 520, 530 and 540 and above the source and drain regions as well as the gate electrodes which may consist in particular of an intermediate oxide, for example a flowable planarization oxide such as boron phosphorus silicate glass (BPSG).
- BPSG boron phosphorus silicate glass
- the intermediate oxide can be replaced by any other insulating material.
- borophosphosilicate glass has the particular advantage that, owing to its flowability, a process of chemical-mechanical planarization to produce a planar surface may be omitted.
- a 150 nm thick blocker layer 660 made of silicon oxynitride SiON is arranged above the insulation layer 650.
- the blocker layer 660 is arranged above the entire surface of the semiconductor substrate 510 and encloses the connection pieces 750, 760, 770, 780, 790 and 800 located in the area of contact holes 670, 680, 690, 700, 710, 720 and 740.
- the contact holes 670, 680, 690, 700, 710 and 720 are preferably filled over their entire surface with a conductive material, for example a metal, preferably tungsten or a tungsten alloy.
- the connectors 750, 760, 770, 780, 790, 800 and 810 are made of a material that combines high conductivity with a low tendency to diffuse, for example aluminum.
- an approximately 100 nm-thick adhesive layer 665 is located between the tungsten filling 730 of a contact hole 740 and the layer delimiting the contact hole, ie here the insulation layer 650 a titanium / titanium nitride alloy.
- the adhesive layer 665 serves as a seeding layer for subsequent deposition processes, in particular for filling the contact holes 670, 680, 690, 700, 710, 720 and 740, for example with tungsten.
- Adhesive layer 665 also protects the material below the bottom of the contact hole.
- the insulation layer 820 which is also referred to as intermetallic oxide.
- the insulation layer 820 (that is to say the intermetallic oxide here) can be deposited using a CVD (Chemical Vapor Deposition) method, for example. In all of the cases mentioned, the generation of the insulation layer 820 can be integrated without any problems into the manufacturing process of the electrical circuit.
- Contact holes 830, 840, 850 and 860 are also etched into the insulation layer 820.
- connection pieces 890 and 900 and a conductor track 910 made of copper in a further insulation layer 880 are completely filled with tungsten or copper.
- contact holes 920 and 930 in the insulation layer 880 are also contact holes 920 and 930 in the insulation layer 880, which in turn are completely filled with tungsten or copper.
- Field-effect transistors 520, 530 and 540 with source and drain regions 550, 560, 570, 580, 590 and 600 and with gate electrodes 620, 630 and 640 are produced in a known manner in the area of a main area of a semiconductor substrate 510.
- an insulation layer 650 is produced, for example, by flowing a flowable planarization oxide such as borophosphosilicate glass (BPSG) or by an application process such as plasma-assisted CVD: PECVD (Plasma Enhanced Chemical Vapor Deposition) process.
- a flowable planarization oxide such as borophosphosilicate glass (BPSG)
- PECVD Plasma-assisted Chemical Vapor Deposition
- contact holes 670, 680, 690, 700, 710, 720 and 740 are preferably etched into the insulation layer 650 in a reactive plasma using a dry etching method.
- a gas mixture of CHF 3 and 0 2 or of CHF 3 and CF 4 is used as the etchant.
- an approximately 100 nm thick adhesive layer 665 made of a titanium / titanium nitride alloy is deposited.
- the contact holes 670, 680, 690, 700, 710, 720 and 740 are then filled with tungsten or copper.
- connectors 750, 760, 770, 780, 790 and 800 which can also be connecting elements, are applied, for example by sputtering and subsequent structuring of a metal layer, for example made of aluminum or an aluminum alloy.
- a structuring process according to a conventional photolithographic method structures the part of the adhesive layer 665 lying above the insulation layer 650 as well as the connectors 750, 760, 770, 780, 790 and 800.
- An approximately 100 nm thick blocker layer 660 is then applied to the insulation layer 650 and the connecting pieces 750, 760, 770, 780, 790 and 800.
- the blocker layer 660 for example made of silicon oxynitride SiON, can preferably be produced by a PECVD process.
- a major advantage of the PECVD process is that it can also be carried out at temperatures below 500 ° C.
- free radicals are generated in a plasma; these are silicon, oxide and nitride radicals when a SiON layer is deposited.
- Silane (SiH), ammonia (NH 3 ) and oxygen are used to carry out the process.
- the blocker layer 660 is preferably deposited at a pressure in the range from approximately 20 to 100 Pa, ideally at approximately 30 Pa, and a temperature below 500 ° C., preferably approximately 300 ° C.
- connectors 750, 760, 770, 780, 790 and 800 are produced by applying and then structuring a metal layer.
- An insulation layer 820 is then deposited on the blocker layer 660 and the connecting pieces 750, 760, 770, 780, 790, 800 and 810 by a suitable deposition method such as chemical vapor deposition (CVD).
- CVD chemical vapor deposition
- contact holes 830, 840, 850, 860 and 870 are etched into the insulation layer 820.
- a gas mixture of CHF 3 and 0 2 or of CHF 3 and CF 4 is used as the etchant.
- Connectors 890 and 900 made of copper and a conductor track 910 which serves to connect the contact holes 850 and 860 and which likewise consists of copper are produced in the manner shown below.
- a copper layer of 300 nm to 600 nm thickness is applied to the insulation layer 820 by means of a sputtering (sputtering) method.
- a paint mask is applied and structured using photolithographic process steps.
- a further insulation layer 880 is then deposited.
- the insulating layer 880 contact holes 920 and 930 are preferably etched by a dry etching process in a reactive plasma. For example, a gas mixture of CHF 3 and 0 2 or of CHF 3 and CF 4 is used as the etchant.
- the contact holes 920 and 930 are then filled with copper.
- Connection pieces 940 and 950 made of copper are then applied to the contact holes 920 and 930.
- An intermetallic dielectric 960 for example made of silicon oxide SI0, is then applied.
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- General Physics & Mathematics (AREA)
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Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98965273A EP1042793A1 (de) | 1997-12-16 | 1998-12-16 | Barriereschicht für kupfermetallisierung |
JP2000539521A JP2002509354A (ja) | 1997-12-16 | 1998-12-16 | 電気集積回路および該電気集積回路を製造する方法 |
US09/595,860 US7064439B1 (en) | 1997-12-16 | 2000-06-16 | Integrated electrical circuit and method for fabricating it |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19755869 | 1997-12-16 | ||
DE19755869.0 | 1997-12-16 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/595,860 Continuation US7064439B1 (en) | 1997-12-16 | 2000-06-16 | Integrated electrical circuit and method for fabricating it |
Publications (1)
Publication Number | Publication Date |
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WO1999031722A1 true WO1999031722A1 (de) | 1999-06-24 |
Family
ID=7852089
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP1998/008255 WO1999031722A1 (de) | 1997-12-16 | 1998-12-16 | Barriereschicht für kupfermetallisierung |
Country Status (5)
Country | Link |
---|---|
US (1) | US7064439B1 (de) |
EP (1) | EP1042793A1 (de) |
JP (1) | JP2002509354A (de) |
KR (1) | KR100417725B1 (de) |
WO (1) | WO1999031722A1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2001098160A (ja) * | 1999-09-30 | 2001-04-10 | Sumitomo Bakelite Co Ltd | 絶縁材用樹脂組成物及びこれを用いた絶縁材 |
US7170115B2 (en) * | 2000-10-17 | 2007-01-30 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit device and method of producing the same |
US6847077B2 (en) * | 2002-06-25 | 2005-01-25 | Agere Systems, Inc. | Capacitor for a semiconductor device and method for fabrication therefor |
US7608538B2 (en) | 2007-01-05 | 2009-10-27 | International Business Machines Corporation | Formation of vertical devices by electroplating |
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- 1998-12-16 KR KR10-2000-7006296A patent/KR100417725B1/ko not_active IP Right Cessation
- 1998-12-16 EP EP98965273A patent/EP1042793A1/de not_active Withdrawn
- 1998-12-16 JP JP2000539521A patent/JP2002509354A/ja active Pending
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2000
- 2000-06-16 US US09/595,860 patent/US7064439B1/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
KR100417725B1 (ko) | 2004-02-11 |
US7064439B1 (en) | 2006-06-20 |
JP2002509354A (ja) | 2002-03-26 |
EP1042793A1 (de) | 2000-10-11 |
KR20010032951A (ko) | 2001-04-25 |
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