WO1999013502A1 - Procede de fabrication de substrat de semi-conducteur forme par epitaxie - Google Patents

Procede de fabrication de substrat de semi-conducteur forme par epitaxie Download PDF

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Publication number
WO1999013502A1
WO1999013502A1 PCT/JP1998/004000 JP9804000W WO9913502A1 WO 1999013502 A1 WO1999013502 A1 WO 1999013502A1 JP 9804000 W JP9804000 W JP 9804000W WO 9913502 A1 WO9913502 A1 WO 9913502A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
ion
halogen element
epitaxial
semiconductor
Prior art date
Application number
PCT/JP1998/004000
Other languages
English (en)
Japanese (ja)
Inventor
Toshihiko Itoga
Seiichi Isomae
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Publication of WO1999013502A1 publication Critical patent/WO1999013502A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Definitions

  • the present invention relates to a method for manufacturing an epitaxial semiconductor substrate and a semiconductor device.
  • the present invention relates to a method for manufacturing an epitaxial semiconductor substrate used for forming a semiconductor element, and a semiconductor device using the same.
  • a conventional method of manufacturing a semiconductor substrate having an epitaxial layer has been to grow an epitaxial film of a semiconductor material on a substrate surface prepared by the Czochralski (CZ) method.
  • Substrates manufactured by the Czochralski (CZ) method in which an epitaxy layer is formed on a so-called CZ substrate, have the ability to get rid of contaminants such as heavy metals because oxygen precipitates are not easily formed inside. Is insufficient. Therefore, when a semiconductor element was formed on such a substrate, the yield rate of the semiconductor element was low.
  • a first object of the present invention is to provide a method of manufacturing an epitaxy semiconductor substrate having a high getlability and capable of obtaining a device having excellent characteristics when a semiconductor device is formed.
  • a second object of the present invention is to provide a semiconductor device having excellent characteristics using a semiconductor substrate having a high gettering ability.
  • the problems underlying the present invention are as follows.
  • the prior art described in the above-mentioned Japanese Patent Application Laid-Open Nos. 4-104544 and 6-164410 of the Japanese Patent Publication has the following problems. That is, (1) When ions are implanted into a surface (referred to as a surface) on which an epitaxial layer is to be formed, crystal defects grow from the ion-implanted layer in the epitaxial layer formed on this surface. Cheap. Therefore, the semiconductor device formed on the epitaxial layer has a very low production yield. (2) Further, when ion implantation is performed on the surface opposite to the surface on which the epitaxial layer is formed (referred to as the back surface), no defect is formed on the surface. However, since the ion-implanted element is carbon, it has gettering ability but does not have a function to improve the performance of the semiconductor element.
  • the prior art described in the above-mentioned Japanese Patent Application Laid-Open No. 7-149914 has a problem that the impurity concentration in the epitaxial layer changes. This is because impurities diffuse from the inside of the substrate to the surface side in a heat treatment step for forming a semiconductor element.
  • the method for producing the epitaxial semiconductor substrate of the present invention for achieving the first object of the present invention is as follows. That is, the manufacturing method is to implant ions of a halogen element, an ion of a compound containing a halogen element or an ion of a carbon element and a hydrogen element into a semiconductor substrate, or to implant ions of a halogen element, Ion or carbon element and hydrogen element consisting of compounds containing elements After exposure to the plasma of ions consisting of, an epitaxial layer is grown on this semiconductor substrate.
  • the ion composed of a compound containing a halogen element refers to, for example, an ion such as CF 3 + ion generated from a compound containing a halogen element such as CF 4 .
  • an ion composed of a carbon element and a hydrogen element refers to, for example, an ion such as a CH 3 + ion.
  • a halogen element has a function of electrically inactivating defects existing at an interface between a semiconductor layer and an oxide film. Therefore, when a semiconductor element is formed using this substrate, a semiconductor element having excellent characteristics is obtained. can get. Since the diffusion rate of the halogen element inside the substrate is high, the effect remains the same even when ion implantation is performed on the back surface.
  • an ion composed of a compound of carbon and a halogen element is used as an ion composed of a compound containing a halogen element, a gettering effect of carbon is added, and a semiconductor substrate having higher gettering ability can be obtained.
  • the ions include carbon and hydrogen, it is preferable to perform ion implantation on the back surface.
  • a semiconductor device of the present invention is as follows. That is, it is constituted by an epitaxial semiconductor substrate manufactured by any of the above-described methods, and a semiconductor element provided in an epitaxial layer of the epitaxial semiconductor substrate. Things.
  • the semiconductor device of the present invention A semiconductor element having a semiconductor layer provided on the ebita-axial layer, and a desired portion in the depth direction of the semiconductor substrate is defined as a region containing a halogen element or a region containing a halogen element and a carbon element. It was done.
  • the concentration of the halogen element in the region containing the halogen element is preferably in the range of 1 ⁇ 10 17 at oms / cm 3 to 1 ⁇ 10 21 at oms / cm 3 , and lx 10 19 at oms / cm 3 to lx More preferably, it is in the range of 10 20 atoms / cm 3 .
  • the concentration of the halogen element and the carbon element in the region containing the halogen element and the carbon element may be in the range of 1 ⁇ 10 17 at oms / cm 3 to 1 ⁇ 10 21 at oms / cm 3.
  • the range is from lxl 0 19 at oms / cm 3 to lxl 0 20 at oms / cm 3 .
  • the surface of the semiconductor substrate, the concentration of the halogen element the preferably range from lx 10 13 at oms / cm 2 of 5 xl 0 16 at oms / cm 2, 5 x 10 14 at oms / cm ⁇ More preferably, it is in the range of 5 ⁇ 10 15 at oms / cm 2 .
  • the concentration of the carbon element on the surface of the semiconductor substrate is preferably in the same range as the concentration of the halogen element.
  • FIG. 1 is a manufacturing process diagram showing a part of the method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 2 is a manufacturing process diagram showing a part of the method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 3 is a manufacturing process diagram showing a part of another method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 4 is a manufacturing process diagram showing a part of another method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 5 is a sectional view of the semiconductor device of the present invention.
  • FIG. 6 is a diagram showing the amounts of diffusion elements for explaining the gettering effect of heavy metals.
  • FIG. 7 is a graph showing the yield rate of the gate oxide film and the junction leakage current of the MOS field-effect transistor. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 A method for manufacturing an epitaxial semiconductor substrate of the present invention will be described with reference to FIGS. 1, 2, 3, and 4.
  • FIG. 1 A method for manufacturing an epitaxial semiconductor substrate of the present invention will be described with reference to FIGS. 1, 2, 3, and 4.
  • ion implantation (1) is performed on the surface of the semiconductor substrate 101 (the surface on which the epitaxial layer is to be grown and the surface on which the semiconductor element is to be formed). .
  • Crystal defects are formed in the ion implantation layer 102 near the surface in the semiconductor substrate 101 by ion implantation.
  • the ion species an example in which F + ions are implanted is shown here.
  • an epitaxial layer 103 was formed to a thickness of 1 ⁇ m using monosilane as a source (FIG. 2).
  • the crystal defects are recovered to some extent by the heat treatment during the growth of the epitaxial layer, they are not perfect and the crystal defects remain. This crystal defect acts as a gettering site.
  • CF 3 + ions (2) are implanted into the back surface of semiconductor substrate 201 (the surface opposite to the surface on which the epitaxial layer is formed).
  • the ion implantation layer 202 is formed near the back surface of the substrate, contrary to the example of FIG. In the example of FIG. 4, the surface was mirror-polished after ion implantation. After that, a 1-micron thick epitaxial layer 203 was formed on the surface (Fig. 4).
  • FIG. 6 is a diagram comparing the gage ring effects of various substrates. It consists of (1) various epitaxial semiconductor substrates obtained by the methods shown in FIGS. 1 to 4 and (2) an epitaxial semiconductor substrate manufactured in the same manner without using the conventional ion implantation. It is a comparison of the guttering effect. After applying Fe, Ni, Cu, and Pt at a surface density of 1 ⁇ 10 13 at oms / cm 2 to the back surfaces of these substrates, a heat treatment was performed at 900 ° C. for 120 minutes. In this case, the concentration of the metal diffused to the surface was measured.
  • metal elements in the order of 1 O ⁇ at oms / cm 2 to 10 12 at oms / cm 2 are diffused.
  • the substrate manufactured according to the present invention when F + ions are implanted, The amount of diffusion is reduced to less than 1/3. This is because crystal defects are formed in the ion-implanted layer and function as gettering sites.
  • the addition of a carbon atom gettering function further reduces the amount of diffused metal other than in the case of Cu.
  • This method is particularly effective for Pt group elements.
  • the effect of the present invention can be exerted by using at least one of the above elements.
  • FIG. 5 is a cross-sectional view of a portion of a MOS transistor of the semiconductor device of the present invention.
  • F + ions were ion-implanted into a semiconductor substrate 301 manufactured by the CZ method, thereby forming an ion-implanted layer 302.
  • an epitaxy layer 303 was formed with a thickness of 1 micron, and an insulated gate field effect transistor was manufactured using this epitaxy semiconductor substrate.
  • the ion implantation may be performed on a part of the semiconductor substrate. For example, substantially the same effect can be obtained without ion implantation in the peripheral portion of the wafer.
  • the thickness of the epitaxial layer is preferably in the range of 0.1 to 5 microns, more preferably in the range of 1 to 3 microns.
  • a poly Si (polycrystalline silicon: hereinafter abbreviated as poly Si) layer 306 for a gate electrode having a thickness of 30 Onm is formed by a CVD (chemical vapor deposition) method.
  • the poly Si layer for the gate electrode was patterned into a desired shape by dry etching.
  • the p-well 305 was formed by implanting boron at 1 ⁇ 10 13 at 0 ms / cm 2 and then performing a heat treatment at 1150 ° C. for 10 hours.
  • the drain 307 and the source 308 were formed by implantation of arsenic ions of 2 ⁇ 10 15 at oms / cm 2 and heat treatment at 900 ° C. for 10 minutes.
  • An interlayer oxide film 309 is formed by a CVD method, and a contact hole (c 0 ntact ho 1 e) is formed in the interlayer oxide film.
  • an A1 electrode 310 was formed, and a MOS type transistor was fabricated. From the current and voltage characteristics of the gate oxide film of the M ⁇ S type transistor, the yield rate of the gate oxide film and the leak current at the drain junction can be calculated.
  • FIG. 7 shows the yield rate of the gate oxide film and the leakage current at the drain junction of the above-mentioned MS type transistor thus calculated.
  • FIG. 7 shows the respective values when an epitaxy semiconductor substrate manufactured without performing ion implantation is used as a conventional example.
  • the manufacturing conditions in each example are as follows.
  • Example 1 uses a semiconductor substrate in which F + ions are implanted at lxl 0 14 at oms / cm 2 into the surface by the method shown in FIG.
  • the second embodiment uses a semiconductor substrate in which F + ions are similarly implanted into the surface at 1 ⁇ 10 15 atoms / cm 2 .
  • Example 3 uses a semiconductor substrate in which CF 3 + ions are implanted on the back surface at 1 ⁇ 10 15 at oms / cm 2 by the method shown in FIGS. 3 and 4.
  • Example 4 uses a semiconductor substrate whose surface is exposed to CF 3 + plasma.
  • the yield rate of the gate oxide film is increased and the junction leak current is reduced in each of the embodiments as compared with the conventional example.
  • the improvement in the yield rate of the gate oxide film is due to the gettering of heavy metals that deteriorate the oxide film characteristics. If the junction leakage current is decreased, F is in the order in which c present embodiment has the effect of terminating dangling bonds in the oxide film / S i interface, which has been subjected to CF 3 + ion implantation However, the best results were obtained for both the yield rate of the gate oxide film and the junction leakage current characteristics. This is because both the gettering effect of carbon and the termination effect of F are obtained.
  • the implanted dose of 1 ⁇ 10 15 at oms / cm 2 is larger than that of 1 ⁇ 10 14 at oms / cm 2 in the gate oxide film.
  • Good product ratio and good junction leakage current characteristics This is thought to be due to the fact that the larger the amount of implanted ions, the larger the amount of crystal defects and the amount of F (fluorine) remaining in the substrate.
  • the ion implantation amount exceeds 1 ⁇ 10 16 at oms / cm 2 , the crystal defects easily grow into the epitaxy layer. The following are appropriate:
  • the time required for performing ion implantation becomes longer, which leads to an increase in cost.
  • the epitaxy layer was formed on the substrate whose surface was exposed to CF 3 + plasma, basically the same effect as that of the substrate subjected to CF 3 + ion implantation was obtained.
  • the method for manufacturing a semiconductor device according to the present invention can manufacture various semiconductor devices having high gettering ability and excellent characteristics. Further, various semiconductor devices according to the present invention can ensure excellent characteristics.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

L'invention, qui a trait à un procédé de fabrication d'un substrat de semi-conducteur formé par épitaxie faisant montre d'un potentiel élevé de fixation du gaz et, partant, conférant de remarquables qualités de fonctionnement à un dispositif à semi-conducteurs réalisé sur ce substrat, porte également sur un dispositif à semi-conducteurs produit grâce à ce procédé de fabrication. Ce procédé consiste à implanter des ions halogènes ou des ions d'un composé renfermant un halogène dans un substrat de semi-conducteur afin de donner lieu à une couche à implantation ionique, puis à faire croître une couche épitaxiale sur le substrat à semi-conducteur.
PCT/JP1998/004000 1997-09-08 1998-09-07 Procede de fabrication de substrat de semi-conducteur forme par epitaxie WO1999013502A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24295497 1997-09-08
JP9/242954 1997-09-08

Publications (1)

Publication Number Publication Date
WO1999013502A1 true WO1999013502A1 (fr) 1999-03-18

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132272A (ja) * 1974-09-13 1976-03-18 Hitachi Ltd Handotaisochinoseizohoho
JPS61240637A (ja) * 1985-04-18 1986-10-25 Fujitsu Ltd 半導体装置の製法
JPH0411736A (ja) * 1990-04-28 1992-01-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0661234A (ja) * 1992-08-06 1994-03-04 Hitachi Ltd 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132272A (ja) * 1974-09-13 1976-03-18 Hitachi Ltd Handotaisochinoseizohoho
JPS61240637A (ja) * 1985-04-18 1986-10-25 Fujitsu Ltd 半導体装置の製法
JPH0411736A (ja) * 1990-04-28 1992-01-16 Mitsubishi Electric Corp 半導体装置およびその製造方法
JPH0661234A (ja) * 1992-08-06 1994-03-04 Hitachi Ltd 半導体装置の製造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
PROCEEDINGS OF THE SYMPOSIUM ON SEMICONDUCTORS AND INTEGRATED CIRCUITS TECHNOLOGY, Vol. 42, (1992), pages 7-12. *

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