WO1999013502A1 - Method of manufacturing epitaxial semiconductor substrate, and semiconductor device - Google Patents

Method of manufacturing epitaxial semiconductor substrate, and semiconductor device Download PDF

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Publication number
WO1999013502A1
WO1999013502A1 PCT/JP1998/004000 JP9804000W WO9913502A1 WO 1999013502 A1 WO1999013502 A1 WO 1999013502A1 JP 9804000 W JP9804000 W JP 9804000W WO 9913502 A1 WO9913502 A1 WO 9913502A1
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Prior art keywords
semiconductor substrate
ion
halogen element
epitaxial
semiconductor
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PCT/JP1998/004000
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French (fr)
Japanese (ja)
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Toshihiko Itoga
Seiichi Isomae
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Hitachi, Ltd.
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Publication of WO1999013502A1 publication Critical patent/WO1999013502A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering

Definitions

  • the present invention relates to a method for manufacturing an epitaxial semiconductor substrate and a semiconductor device.
  • the present invention relates to a method for manufacturing an epitaxial semiconductor substrate used for forming a semiconductor element, and a semiconductor device using the same.
  • a conventional method of manufacturing a semiconductor substrate having an epitaxial layer has been to grow an epitaxial film of a semiconductor material on a substrate surface prepared by the Czochralski (CZ) method.
  • Substrates manufactured by the Czochralski (CZ) method in which an epitaxy layer is formed on a so-called CZ substrate, have the ability to get rid of contaminants such as heavy metals because oxygen precipitates are not easily formed inside. Is insufficient. Therefore, when a semiconductor element was formed on such a substrate, the yield rate of the semiconductor element was low.
  • a first object of the present invention is to provide a method of manufacturing an epitaxy semiconductor substrate having a high getlability and capable of obtaining a device having excellent characteristics when a semiconductor device is formed.
  • a second object of the present invention is to provide a semiconductor device having excellent characteristics using a semiconductor substrate having a high gettering ability.
  • the problems underlying the present invention are as follows.
  • the prior art described in the above-mentioned Japanese Patent Application Laid-Open Nos. 4-104544 and 6-164410 of the Japanese Patent Publication has the following problems. That is, (1) When ions are implanted into a surface (referred to as a surface) on which an epitaxial layer is to be formed, crystal defects grow from the ion-implanted layer in the epitaxial layer formed on this surface. Cheap. Therefore, the semiconductor device formed on the epitaxial layer has a very low production yield. (2) Further, when ion implantation is performed on the surface opposite to the surface on which the epitaxial layer is formed (referred to as the back surface), no defect is formed on the surface. However, since the ion-implanted element is carbon, it has gettering ability but does not have a function to improve the performance of the semiconductor element.
  • the prior art described in the above-mentioned Japanese Patent Application Laid-Open No. 7-149914 has a problem that the impurity concentration in the epitaxial layer changes. This is because impurities diffuse from the inside of the substrate to the surface side in a heat treatment step for forming a semiconductor element.
  • the method for producing the epitaxial semiconductor substrate of the present invention for achieving the first object of the present invention is as follows. That is, the manufacturing method is to implant ions of a halogen element, an ion of a compound containing a halogen element or an ion of a carbon element and a hydrogen element into a semiconductor substrate, or to implant ions of a halogen element, Ion or carbon element and hydrogen element consisting of compounds containing elements After exposure to the plasma of ions consisting of, an epitaxial layer is grown on this semiconductor substrate.
  • the ion composed of a compound containing a halogen element refers to, for example, an ion such as CF 3 + ion generated from a compound containing a halogen element such as CF 4 .
  • an ion composed of a carbon element and a hydrogen element refers to, for example, an ion such as a CH 3 + ion.
  • a halogen element has a function of electrically inactivating defects existing at an interface between a semiconductor layer and an oxide film. Therefore, when a semiconductor element is formed using this substrate, a semiconductor element having excellent characteristics is obtained. can get. Since the diffusion rate of the halogen element inside the substrate is high, the effect remains the same even when ion implantation is performed on the back surface.
  • an ion composed of a compound of carbon and a halogen element is used as an ion composed of a compound containing a halogen element, a gettering effect of carbon is added, and a semiconductor substrate having higher gettering ability can be obtained.
  • the ions include carbon and hydrogen, it is preferable to perform ion implantation on the back surface.
  • a semiconductor device of the present invention is as follows. That is, it is constituted by an epitaxial semiconductor substrate manufactured by any of the above-described methods, and a semiconductor element provided in an epitaxial layer of the epitaxial semiconductor substrate. Things.
  • the semiconductor device of the present invention A semiconductor element having a semiconductor layer provided on the ebita-axial layer, and a desired portion in the depth direction of the semiconductor substrate is defined as a region containing a halogen element or a region containing a halogen element and a carbon element. It was done.
  • the concentration of the halogen element in the region containing the halogen element is preferably in the range of 1 ⁇ 10 17 at oms / cm 3 to 1 ⁇ 10 21 at oms / cm 3 , and lx 10 19 at oms / cm 3 to lx More preferably, it is in the range of 10 20 atoms / cm 3 .
  • the concentration of the halogen element and the carbon element in the region containing the halogen element and the carbon element may be in the range of 1 ⁇ 10 17 at oms / cm 3 to 1 ⁇ 10 21 at oms / cm 3.
  • the range is from lxl 0 19 at oms / cm 3 to lxl 0 20 at oms / cm 3 .
  • the surface of the semiconductor substrate, the concentration of the halogen element the preferably range from lx 10 13 at oms / cm 2 of 5 xl 0 16 at oms / cm 2, 5 x 10 14 at oms / cm ⁇ More preferably, it is in the range of 5 ⁇ 10 15 at oms / cm 2 .
  • the concentration of the carbon element on the surface of the semiconductor substrate is preferably in the same range as the concentration of the halogen element.
  • FIG. 1 is a manufacturing process diagram showing a part of the method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 2 is a manufacturing process diagram showing a part of the method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 3 is a manufacturing process diagram showing a part of another method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 4 is a manufacturing process diagram showing a part of another method for manufacturing an epitaxial semiconductor substrate of the present invention.
  • FIG. 5 is a sectional view of the semiconductor device of the present invention.
  • FIG. 6 is a diagram showing the amounts of diffusion elements for explaining the gettering effect of heavy metals.
  • FIG. 7 is a graph showing the yield rate of the gate oxide film and the junction leakage current of the MOS field-effect transistor. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 A method for manufacturing an epitaxial semiconductor substrate of the present invention will be described with reference to FIGS. 1, 2, 3, and 4.
  • FIG. 1 A method for manufacturing an epitaxial semiconductor substrate of the present invention will be described with reference to FIGS. 1, 2, 3, and 4.
  • ion implantation (1) is performed on the surface of the semiconductor substrate 101 (the surface on which the epitaxial layer is to be grown and the surface on which the semiconductor element is to be formed). .
  • Crystal defects are formed in the ion implantation layer 102 near the surface in the semiconductor substrate 101 by ion implantation.
  • the ion species an example in which F + ions are implanted is shown here.
  • an epitaxial layer 103 was formed to a thickness of 1 ⁇ m using monosilane as a source (FIG. 2).
  • the crystal defects are recovered to some extent by the heat treatment during the growth of the epitaxial layer, they are not perfect and the crystal defects remain. This crystal defect acts as a gettering site.
  • CF 3 + ions (2) are implanted into the back surface of semiconductor substrate 201 (the surface opposite to the surface on which the epitaxial layer is formed).
  • the ion implantation layer 202 is formed near the back surface of the substrate, contrary to the example of FIG. In the example of FIG. 4, the surface was mirror-polished after ion implantation. After that, a 1-micron thick epitaxial layer 203 was formed on the surface (Fig. 4).
  • FIG. 6 is a diagram comparing the gage ring effects of various substrates. It consists of (1) various epitaxial semiconductor substrates obtained by the methods shown in FIGS. 1 to 4 and (2) an epitaxial semiconductor substrate manufactured in the same manner without using the conventional ion implantation. It is a comparison of the guttering effect. After applying Fe, Ni, Cu, and Pt at a surface density of 1 ⁇ 10 13 at oms / cm 2 to the back surfaces of these substrates, a heat treatment was performed at 900 ° C. for 120 minutes. In this case, the concentration of the metal diffused to the surface was measured.
  • metal elements in the order of 1 O ⁇ at oms / cm 2 to 10 12 at oms / cm 2 are diffused.
  • the substrate manufactured according to the present invention when F + ions are implanted, The amount of diffusion is reduced to less than 1/3. This is because crystal defects are formed in the ion-implanted layer and function as gettering sites.
  • the addition of a carbon atom gettering function further reduces the amount of diffused metal other than in the case of Cu.
  • This method is particularly effective for Pt group elements.
  • the effect of the present invention can be exerted by using at least one of the above elements.
  • FIG. 5 is a cross-sectional view of a portion of a MOS transistor of the semiconductor device of the present invention.
  • F + ions were ion-implanted into a semiconductor substrate 301 manufactured by the CZ method, thereby forming an ion-implanted layer 302.
  • an epitaxy layer 303 was formed with a thickness of 1 micron, and an insulated gate field effect transistor was manufactured using this epitaxy semiconductor substrate.
  • the ion implantation may be performed on a part of the semiconductor substrate. For example, substantially the same effect can be obtained without ion implantation in the peripheral portion of the wafer.
  • the thickness of the epitaxial layer is preferably in the range of 0.1 to 5 microns, more preferably in the range of 1 to 3 microns.
  • a poly Si (polycrystalline silicon: hereinafter abbreviated as poly Si) layer 306 for a gate electrode having a thickness of 30 Onm is formed by a CVD (chemical vapor deposition) method.
  • the poly Si layer for the gate electrode was patterned into a desired shape by dry etching.
  • the p-well 305 was formed by implanting boron at 1 ⁇ 10 13 at 0 ms / cm 2 and then performing a heat treatment at 1150 ° C. for 10 hours.
  • the drain 307 and the source 308 were formed by implantation of arsenic ions of 2 ⁇ 10 15 at oms / cm 2 and heat treatment at 900 ° C. for 10 minutes.
  • An interlayer oxide film 309 is formed by a CVD method, and a contact hole (c 0 ntact ho 1 e) is formed in the interlayer oxide film.
  • an A1 electrode 310 was formed, and a MOS type transistor was fabricated. From the current and voltage characteristics of the gate oxide film of the M ⁇ S type transistor, the yield rate of the gate oxide film and the leak current at the drain junction can be calculated.
  • FIG. 7 shows the yield rate of the gate oxide film and the leakage current at the drain junction of the above-mentioned MS type transistor thus calculated.
  • FIG. 7 shows the respective values when an epitaxy semiconductor substrate manufactured without performing ion implantation is used as a conventional example.
  • the manufacturing conditions in each example are as follows.
  • Example 1 uses a semiconductor substrate in which F + ions are implanted at lxl 0 14 at oms / cm 2 into the surface by the method shown in FIG.
  • the second embodiment uses a semiconductor substrate in which F + ions are similarly implanted into the surface at 1 ⁇ 10 15 atoms / cm 2 .
  • Example 3 uses a semiconductor substrate in which CF 3 + ions are implanted on the back surface at 1 ⁇ 10 15 at oms / cm 2 by the method shown in FIGS. 3 and 4.
  • Example 4 uses a semiconductor substrate whose surface is exposed to CF 3 + plasma.
  • the yield rate of the gate oxide film is increased and the junction leak current is reduced in each of the embodiments as compared with the conventional example.
  • the improvement in the yield rate of the gate oxide film is due to the gettering of heavy metals that deteriorate the oxide film characteristics. If the junction leakage current is decreased, F is in the order in which c present embodiment has the effect of terminating dangling bonds in the oxide film / S i interface, which has been subjected to CF 3 + ion implantation However, the best results were obtained for both the yield rate of the gate oxide film and the junction leakage current characteristics. This is because both the gettering effect of carbon and the termination effect of F are obtained.
  • the implanted dose of 1 ⁇ 10 15 at oms / cm 2 is larger than that of 1 ⁇ 10 14 at oms / cm 2 in the gate oxide film.
  • Good product ratio and good junction leakage current characteristics This is thought to be due to the fact that the larger the amount of implanted ions, the larger the amount of crystal defects and the amount of F (fluorine) remaining in the substrate.
  • the ion implantation amount exceeds 1 ⁇ 10 16 at oms / cm 2 , the crystal defects easily grow into the epitaxy layer. The following are appropriate:
  • the time required for performing ion implantation becomes longer, which leads to an increase in cost.
  • the epitaxy layer was formed on the substrate whose surface was exposed to CF 3 + plasma, basically the same effect as that of the substrate subjected to CF 3 + ion implantation was obtained.
  • the method for manufacturing a semiconductor device according to the present invention can manufacture various semiconductor devices having high gettering ability and excellent characteristics. Further, various semiconductor devices according to the present invention can ensure excellent characteristics.

Abstract

A method of manufacturing an epitaxial semiconductor substrate having a high gettering capability and, therefore, imparting a superior performance to a semiconductor device fabricated on the substrate, and a semiconductor device fabricated by this manufacturing method. The manufacturing method comprises implanting halogen ions or ions of a compound containing a halogen into a semiconductor substrate to form an ion-implanted layer and growing an epitaxial layer on the semiconductor substrate.

Description

明 細 書  Specification
ェピタキシャル半導体基板の製造方法及び半導体装置 技術分野  TECHNICAL FIELD The present invention relates to a method for manufacturing an epitaxial semiconductor substrate and a semiconductor device.
本発明は、 半導体素子を形成するために用いられるェピタキシャル半導体基板 の製造方法及びそれを用いた半導体装置に関するものである。 背景技術  The present invention relates to a method for manufacturing an epitaxial semiconductor substrate used for forming a semiconductor element, and a semiconductor device using the same. Background art
従来のェピ夕キシャル層を有する半導体基板の製造方法は、 通常、 チヨクラル スキー (CZ) 法で作製した基板表面に、 半導体材料のェビタキシャル膜を成長 させる方法が用いられていた。 このチヨクラルスキー (CZ) 法で製造された、 いわゆる C Z基板上にェピタキシャル層を形成した基板は、 その内部に酸素析出 物が形成されにくいために重金属等の汚染元素をゲッ夕リングする能力が不足す る。 このため、 こうした基板に半導体素子を形成した際、 その半導体素子の良品 率は低くかった。  A conventional method of manufacturing a semiconductor substrate having an epitaxial layer has been to grow an epitaxial film of a semiconductor material on a substrate surface prepared by the Czochralski (CZ) method. Substrates manufactured by the Czochralski (CZ) method, in which an epitaxy layer is formed on a so-called CZ substrate, have the ability to get rid of contaminants such as heavy metals because oxygen precipitates are not easily formed inside. Is insufficient. Therefore, when a semiconductor element was formed on such a substrate, the yield rate of the semiconductor element was low.
これを解決するため、 炭素又は炭素と砒素のイオンをイオン打ち込みした半導 体基板上に、 ェピタキシャル層を形成する技術が提案されている。 この方法によ り半導体基板内にゲヅ夕リングサイ ト (Ge t t e r ing S i t e)を形成す ることができ、こうした半導体基板は上記汚染元素等を捕獲する能力が向上する。 こうした技術は、 例えば日本国特許公開公報の特開平 4一 10544号あるいは 特開平 6— 163410号に見ることが出来る。  In order to solve this problem, a technique has been proposed in which an epitaxial layer is formed on a semiconductor substrate into which carbon or carbon and arsenic ions are ion-implanted. By this method, a gate ring site can be formed in the semiconductor substrate, and such a semiconductor substrate has an improved ability to capture the contaminant element and the like. Such a technique can be found, for example, in Japanese Patent Laid-Open Publication No. Hei 4-110544 or JP-A-6-163410.
また、 高濃度の不純物 (ドービング元素) を含む基板上に低濃度の不純物を含 む層を形成し、 寄生 MOSトランジスタのしきい値電圧の低下を防ぐようにした ものも提案されている。 こうした技術は例えば、 日本国特許公開公報の特開平 7 - 14914号に記載されている。 発明の開示 本発明の第 1の目的は、 ゲッ夕リング能力が高く、 且つ半導体素子を形成した ときに、 特性の優れた素子が得られるェピタキシャル半導体基板の製造方法を提 供することにある。 In addition, a proposal has been made in which a layer containing a low-concentration impurity is formed on a substrate containing a high-concentration impurity (doping element) so as to prevent the threshold voltage of a parasitic MOS transistor from being lowered. Such a technique is described, for example, in Japanese Patent Laid-Open Publication No. 7-14914. Disclosure of the invention A first object of the present invention is to provide a method of manufacturing an epitaxy semiconductor substrate having a high getlability and capable of obtaining a device having excellent characteristics when a semiconductor device is formed.
本発明の第 2の目的は、 ゲッ夕リング能力が高い半導体基板を用いた、 特性の 優れた半導体装置を提供することにある。  A second object of the present invention is to provide a semiconductor device having excellent characteristics using a semiconductor substrate having a high gettering ability.
本願発明の基礎となった問題点は次の諸点にある。 日本国公開特許公報の上記 特開平 4— 1 0 5 4 4号、 特開平 6— 1 6 3 4 1 0号に記載されている従来技術 は、 次のような問題を有している。 すなわち、 ( 1 ) ェピタキシャル層を形成す る面 (表面と称する) にイオン打ち込みした場合、 この面上に形成されたェピ夕 キシャル層に、 前記イオン打ち込みをした層から結晶欠陥が成長しやすい。 この 為、 このェピタキシャル層に形成した半導体素子は、 その製造歩留まりが極めて 低い。 (2 ) また、 ェピタキシャル層を形成する面の逆の面 (裏面と称する) に イオン打ち込みした場合は、 表面に欠陥は形成されない。 しかし、 イオン打ち込 み元素が炭素であるので、 ゲッ夕リング能力は有するが、 半導体素子の性能を向 上させる機能を有していない。  The problems underlying the present invention are as follows. The prior art described in the above-mentioned Japanese Patent Application Laid-Open Nos. 4-104544 and 6-164410 of the Japanese Patent Publication has the following problems. That is, (1) When ions are implanted into a surface (referred to as a surface) on which an epitaxial layer is to be formed, crystal defects grow from the ion-implanted layer in the epitaxial layer formed on this surface. Cheap. Therefore, the semiconductor device formed on the epitaxial layer has a very low production yield. (2) Further, when ion implantation is performed on the surface opposite to the surface on which the epitaxial layer is formed (referred to as the back surface), no defect is formed on the surface. However, since the ion-implanted element is carbon, it has gettering ability but does not have a function to improve the performance of the semiconductor element.
また、 上記特開平 7— 1 4 9 1 4号に記載の従来技術は、 ェピタキシャル層中 の不純物濃度が変化してしまうという問題を有している。 それは、 半導体素子を 形成する熱処理工程において、 基板内部から表面側に不純物が拡散するためであ る。  Further, the prior art described in the above-mentioned Japanese Patent Application Laid-Open No. 7-149914 has a problem that the impurity concentration in the epitaxial layer changes. This is because impurities diffuse from the inside of the substrate to the surface side in a heat treatment step for forming a semiconductor element.
上記諸目的に添って、 本明細書に閧示される本発明の諸形態を説明すれば、 次 の通りである。  The following is a description of the embodiments of the present invention set forth in the present specification with reference to the above objects.
上記本願発明の第 1の目的を達成するための本発明のェピタキシャル半導体基 板の製造方法は次の通りである。 即ち、 その製造方法は、 半導体基板に、 ハロゲ ン元素のイオン、 ハロゲン元素を含む化合物からなるイオン又は炭素元素及び水 素元素からなるイオンをイオン打ち込みするか或いは半導体基板をハロゲン元素 のイオン、 ハロゲン元素を含む化合物からなるィオン又は炭素元素及び水素元素 からなるイオンのプラズマ中に曝した後、 この半導体基板にェピ夕キシャル層を 成長させるようにしたものである。 The method for producing the epitaxial semiconductor substrate of the present invention for achieving the first object of the present invention is as follows. That is, the manufacturing method is to implant ions of a halogen element, an ion of a compound containing a halogen element or an ion of a carbon element and a hydrogen element into a semiconductor substrate, or to implant ions of a halogen element, Ion or carbon element and hydrogen element consisting of compounds containing elements After exposure to the plasma of ions consisting of, an epitaxial layer is grown on this semiconductor substrate.
ハロゲン元素を含む化合物からなるイオンとは、 例えば、 C F 4のようにハロ ゲン元素を含む化合物から生成した C F 3 +イオンのようなイオンをいう。また、 炭素元素及び水素元素からなるイオンとは、例えば、 C H 3 +イオンのようなィォ ンをいう。 The ion composed of a compound containing a halogen element refers to, for example, an ion such as CF 3 + ion generated from a compound containing a halogen element such as CF 4 . In addition, an ion composed of a carbon element and a hydrogen element refers to, for example, an ion such as a CH 3 + ion.
上記のような方法を行うとき、 ハロゲン元素をイオン打ち込みした領域には結 晶欠陥が形成されるが、 ハロゲン元素は結晶欠陥が成長することを抑制する作用 がある。 この為、結晶欠陥はイオン打ち込みした領域のみに形成される。従って、 たとえ表面にイオン打ち込みを施した場合でも、 結晶欠陥がェピ夕キシャル層に 成長し、 悪影響を与えることは殆どない。  When the above method is performed, a crystal defect is formed in a region where the halogen element is ion-implanted, but the halogen element has an effect of suppressing the growth of the crystal defect. Therefore, crystal defects are formed only in the ion-implanted region. Therefore, even if ion implantation is performed on the surface, crystal defects grow in the epitaxial layer and have almost no adverse effect.
また、 ハロゲン元素には、 半導体層と酸化膜の界面に存在する欠陥を電気的に 不活性化させる作用があるので、 半導体素子をこの基板を用いて形成した際には 特性のよい半導体素子が得られる。 ハロゲン元素は基板内部での拡散速度が速い ので、 イオン打ち込みを裏面に施した場合でも効果は変わらない。  In addition, a halogen element has a function of electrically inactivating defects existing at an interface between a semiconductor layer and an oxide film. Therefore, when a semiconductor element is formed using this substrate, a semiconductor element having excellent characteristics is obtained. can get. Since the diffusion rate of the halogen element inside the substrate is high, the effect remains the same even when ion implantation is performed on the back surface.
ハロゲン元素を含む化合物からなるイオンとして、 炭素とハロゲン元素の化合 物からなるイオンを用いれば、 炭素のゲッ夕リング効果が付加され、 よりゲッ夕 リング能力の高い半導体基板が得られる。 なお、 イオンが炭素や水素を含むとき は、 イオン打ち込みを裏面に施すことが好ましい。  When an ion composed of a compound of carbon and a halogen element is used as an ion composed of a compound containing a halogen element, a gettering effect of carbon is added, and a semiconductor substrate having higher gettering ability can be obtained. When the ions include carbon and hydrogen, it is preferable to perform ion implantation on the back surface.
これらの方法では、 高濃度の不純物を含む半導体基板を用いる必要がないので 、 ェピタキシャル層の不純物濃度を変化させるような問題は生じない。  In these methods, since it is not necessary to use a semiconductor substrate containing a high concentration of impurities, there is no problem that the impurity concentration of the epitaxial layer is changed.
また、 上記本願発明の第 2の目的を達成するために、 本発明の半導体装置は次 の如きものである。 即ち、 それは、 上に述べたいずれかの方法により製造された ェピ夕キシャル半導体基板と、 このェピ夕キシャル半導体基板のェピ夕キシャル 層に設けられた半導体素子とから構成するようにしたものである。  In order to achieve the second object of the present invention, a semiconductor device of the present invention is as follows. That is, it is constituted by an epitaxial semiconductor substrate manufactured by any of the above-described methods, and a semiconductor element provided in an epitaxial layer of the epitaxial semiconductor substrate. Things.
さらに、 上記第 2の目的を達成するために、 本発明の半導体装置は、 ェピタキ シャル層を有する半導体基板と、 このェビタキシャル層に設けられた半導体素子 を有し、 この半導体基板の深さ方向の所望の部分を、 ハロゲン元素を含む領域又 はハロゲン元素と炭素元素を含む領域としたものである。 Furthermore, in order to achieve the second object, the semiconductor device of the present invention A semiconductor element having a semiconductor layer provided on the ebita-axial layer, and a desired portion in the depth direction of the semiconductor substrate is defined as a region containing a halogen element or a region containing a halogen element and a carbon element. It was done.
このハロゲン元素を含む領域のハロゲン元素の濃度は、 1 X 1017a t oms /cm3から 1 x 1021 a t oms/cm3の範囲とすることが好ましく、 l x 1019 a t oms/cm3から l x 1020 a t o m s / c m3の範囲とするこ とがより好ましい。 また、 上記のハロゲン元素と炭素元素を含む領域のハロゲン 元素及び炭素元素の濃度は、 いずれも 1 X 1017 a t oms/cm3から 1 x 1 021 a t oms/cm3の範囲とすることが好ましく、 l x l 019at oms/ cm3から l x l 020at o m s / c m3の範囲とすることがより好ましい。 また、 半導体基板の表面では、 ハロゲン元素の濃度は、 l x 1013 at oms /cm2から 5 x l 016at o m s / c m 2の範囲とすることが好ましく、 5 x 1014 a t oms/cm^から 5 x 1015 a t oms/cm2の範囲とするこ とがより好ましい。 また、 ハロゲン元素と共に炭素元素を含むとき、 炭素元素の 半導体基板の表面での濃度は、 ハロゲン元素の濃度と同様の範囲であることが好 ましい。 図面の簡単な説明 The concentration of the halogen element in the region containing the halogen element is preferably in the range of 1 × 10 17 at oms / cm 3 to 1 × 10 21 at oms / cm 3 , and lx 10 19 at oms / cm 3 to lx More preferably, it is in the range of 10 20 atoms / cm 3 . In addition, the concentration of the halogen element and the carbon element in the region containing the halogen element and the carbon element may be in the range of 1 × 10 17 at oms / cm 3 to 1 × 10 21 at oms / cm 3. More preferably, the range is from lxl 0 19 at oms / cm 3 to lxl 0 20 at oms / cm 3 . Further, the surface of the semiconductor substrate, the concentration of the halogen element, the preferably range from lx 10 13 at oms / cm 2 of 5 xl 0 16 at oms / cm 2, 5 x 10 14 at oms / cm ^ More preferably, it is in the range of 5 × 10 15 at oms / cm 2 . When a carbon element is contained together with the halogen element, the concentration of the carbon element on the surface of the semiconductor substrate is preferably in the same range as the concentration of the halogen element. BRIEF DESCRIPTION OF THE FIGURES
第 1図は本発明のェピタキシャル半導体基板の製造方法の一部を示す製造工程 図である。 第 2図は本発明のェピタキシャル半導体基板の製造方法の一部を示す 製造工程図である。 第 3図は本発明のェピタキシャル半導体基板の別な製造方法 の一部を示す製造工程図である。 第 4図は本発明のェピタキシャル半導体基板の 別な製造方法の一部を示す製造工程図である。 第 5図は本発明の半導体装置の断 面図である。 第 6図は重金属のゲッタリング効果を説明するための拡散元素量を 示す図である。 第 7図は MOS型電界効果型トランジスタのゲート酸化膜良品率 と接合リーク電流を示す図である。 発明を実施するための最良の形態 FIG. 1 is a manufacturing process diagram showing a part of the method for manufacturing an epitaxial semiconductor substrate of the present invention. FIG. 2 is a manufacturing process diagram showing a part of the method for manufacturing an epitaxial semiconductor substrate of the present invention. FIG. 3 is a manufacturing process diagram showing a part of another method for manufacturing an epitaxial semiconductor substrate of the present invention. FIG. 4 is a manufacturing process diagram showing a part of another method for manufacturing an epitaxial semiconductor substrate of the present invention. FIG. 5 is a sectional view of the semiconductor device of the present invention. FIG. 6 is a diagram showing the amounts of diffusion elements for explaining the gettering effect of heavy metals. FIG. 7 is a graph showing the yield rate of the gate oxide film and the junction leakage current of the MOS field-effect transistor. BEST MODE FOR CARRYING OUT THE INVENTION
本発明のェピタキシャル半導体基板の作製方法を第 1図、 第 2図、 第 3図およ び第 4図を用いて説明する。  A method for manufacturing an epitaxial semiconductor substrate of the present invention will be described with reference to FIGS. 1, 2, 3, and 4. FIG.
第 1図に示すように、 ェピタキシャル成長を行う前に、 半導体基板 101の表 面 (ェピタキシャル層を成長する面、 かつ、 半導体素子を形成する方の面) にイオン打ち込み ( 1) を施す。 半導体基板 101内の表面近傍のイオン打ち込 み層 102にはイオン打ち込みにより結晶欠陥が形成される。 イオン種はここで は 1例として F+イオンを打ち込んだ例を示した。イオン打ち込みを行った後に、 モノシランをソースとしてェピ夕キシャル層 103を厚さ 1ミクロン形成した (第 2図) 。 このェピ夕キシャル層成長の際の熱処理により結晶欠陥はある程度 回復するが完全ではなく、 結晶欠陥が残留する。 この結晶欠陥はゲッ夕リングサ ィ トとして作用する。  As shown in FIG. 1, before performing epitaxial growth, ion implantation (1) is performed on the surface of the semiconductor substrate 101 (the surface on which the epitaxial layer is to be grown and the surface on which the semiconductor element is to be formed). . Crystal defects are formed in the ion implantation layer 102 near the surface in the semiconductor substrate 101 by ion implantation. As the ion species, an example in which F + ions are implanted is shown here. After ion implantation, an epitaxial layer 103 was formed to a thickness of 1 μm using monosilane as a source (FIG. 2). Although the crystal defects are recovered to some extent by the heat treatment during the growth of the epitaxial layer, they are not perfect and the crystal defects remain. This crystal defect acts as a gettering site.
次の例は、 第 3図に示すように、 半導体基板 201の裏面 (ェピタキシャル層 を形成する面と逆の面) に CF3+イオン (2) を打ち込んだ例である。 イオン打 ち込み層 202は、 第 2図の例とは逆に基板の裏面近傍に形成される。 第 4図の 例では、 イオン打ち込みを行った後に、 表面を鏡面研磨した。 その後、 表面に 1 ミクロンの厚さのェビタキシャル層 203を形成した (第 4図) 。 In the following example, as shown in FIG. 3 , CF 3 + ions (2) are implanted into the back surface of semiconductor substrate 201 (the surface opposite to the surface on which the epitaxial layer is formed). The ion implantation layer 202 is formed near the back surface of the substrate, contrary to the example of FIG. In the example of FIG. 4, the surface was mirror-polished after ion implantation. After that, a 1-micron thick epitaxial layer 203 was formed on the surface (Fig. 4).
第 6図は各種基板のゲヅ夕リング効果を比較する図である。 それは、 ( 1) 第 1図より第 4図に示した各方法で得た各種ェピタキシャル半導体基板と (2) 従 来法のイオン打ち込みを行わずに同様にして作製したェピ夕キシャル半導体基板 のゲヅタリング効果の比較である。 これらの基板の裏面に、面密度で 1 X 1013 a t oms/cm2の F e、 Ni、 Cu、 P tを付着させた後に、 900°C、 1 20分の熱処理を施した。 この場合の表面に拡散した金属濃度を測定した。 従来 法で作製したェピタキシャル半導体基板表面には、 1 O ^at oms/cm2か ら 1012 at oms/cm2台の金属元素が拡散している。 これに対し、 本発明 により製造した基板では、 F+イオンを打ち込んだ場合、 それそれの原子とも、 1/3以下にまで拡散量が低減されている。 これはイオン打ち込み層に結晶欠陥 が形成され、 ゲッ夕リングサイ トとして機能するためである。 CF3 +イオン打ち 込みを行った場合、 この効果に加え、 炭素原子のゲッ夕リング機能が付加される ために、 Cuの場合の他は、 さらに拡散金属量が低減している。 本方法は特に P t族元素に対して有効である。 尚、 本願発明は前記各元素の少なくとも一者を用 いることによってその効果を奏することができる。 FIG. 6 is a diagram comparing the gage ring effects of various substrates. It consists of (1) various epitaxial semiconductor substrates obtained by the methods shown in FIGS. 1 to 4 and (2) an epitaxial semiconductor substrate manufactured in the same manner without using the conventional ion implantation. It is a comparison of the guttering effect. After applying Fe, Ni, Cu, and Pt at a surface density of 1 × 10 13 at oms / cm 2 to the back surfaces of these substrates, a heat treatment was performed at 900 ° C. for 120 minutes. In this case, the concentration of the metal diffused to the surface was measured. On the surface of the epitaxial semiconductor substrate manufactured by the conventional method, metal elements in the order of 1 O ^ at oms / cm 2 to 10 12 at oms / cm 2 are diffused. On the other hand, in the substrate manufactured according to the present invention, when F + ions are implanted, The amount of diffusion is reduced to less than 1/3. This is because crystal defects are formed in the ion-implanted layer and function as gettering sites. In the case of CF 3 + ion implantation, in addition to this effect, the addition of a carbon atom gettering function further reduces the amount of diffused metal other than in the case of Cu. This method is particularly effective for Pt group elements. The effect of the present invention can be exerted by using at least one of the above elements.
第 5図は、 本発明の半導体装置の M 0 S型トランジス夕部分の断面図である。 CZ法により作製した半導体基板 301に F +イオンをイオン打ち込みし、 ィォ ン打ち込み層 302を形成した。 その後に、 ェピタキシャル層 303を厚さ 1ミ クロン形成し、 このェピタキシャル半導体基板を用いて絶縁ゲート型電界効果型 トランジスタを作製した。  FIG. 5 is a cross-sectional view of a portion of a MOS transistor of the semiconductor device of the present invention. F + ions were ion-implanted into a semiconductor substrate 301 manufactured by the CZ method, thereby forming an ion-implanted layer 302. Thereafter, an epitaxy layer 303 was formed with a thickness of 1 micron, and an insulated gate field effect transistor was manufactured using this epitaxy semiconductor substrate.
イオン打ち込みは、 半導体基板の一部に行う方法でもよい。 例えば、 ウェハの 周辺部にはイオン打ち込みしなくとも実質的に同じ効果が得られる。 また、 ェピ 夕キシャル層の厚さは、 0. 1ミクロンから 5ミクロンの範囲が好ましく、 1ミ クロンから 3ミクロンの範囲がより好ましい。  The ion implantation may be performed on a part of the semiconductor substrate. For example, substantially the same effect can be obtained without ion implantation in the peripheral portion of the wafer. The thickness of the epitaxial layer is preferably in the range of 0.1 to 5 microns, more preferably in the range of 1 to 3 microns.
まず、 熱酸化法により、 素子分離用の酸化膜 304を形成した後に、 ゲート部 の酸化を行なう。 次いで、 膜厚 30 Onmのゲート電極用のポリ S i (多結晶シ リコン:以下、 ポリ S iと略記する) 層 306を CVD (化学気相成長) 法によ り形成し、 この形成されたのゲート電極用のポリ S i層をドライエッチングによ り所望形状にパ夕一ニングした。 p—ゥエル 305はボロンを 1 X 1013at 0 ms/ cm2イオン打ち込みした後に、 1150°C、 10時間の熱処理を行い形 成した。 ドレイン 307、 ソース 308は 2 X 1015a t oms/cm2の砒素 イオンの打ち込みと 900°C、 10分の熱処理により形成した。 層間酸化膜 30 9を CVD法により形成し、 この層間酸化膜にコンタクトホール (c 0 n t a c t ho 1 e)を形成する。 この後、 A 1電極 310を形成し、 MO S型トランジ ス夕を作製した。 M〇 S型トランジスタのゲート酸化膜の電流、 電圧特性からゲート酸化膜の良 品率とドレイン接合のリーク電流を算定することが出来る。 第 7図に、 こうして 算定された前記の M〇 S型トランジスタのゲ一ト酸化膜の良品率とドレイン接合 のリーク電流を示す。 また、 比較のため、 従来例としてイオン打ち込み行わない で製造したェピタキシャル半導体基板を用いたときの各値を、 第 7図に合わせて 示す。 第 7図において、 各実施例での製造条件は次の通りである。 実施例 1は、 第 1図に示した方法により、 F +イオンを表面に l x l 014at oms/cm2 イオン打ち込みを行った半導体基板を用いたものである。 実施例 2は、 同様に F +イオンを表面に 1 x 1015a t oms/cm2イオン打ち込みを行った半導体 基板を用いたものである。実施例 3は、第 3図および第 4図に示した方法により、 CF 3 +イオンを裏面に 1 X 1015 at oms/cm2のイオン打ち込みを行つ た半導体基板を用いたものである。実施例 4は、 CF3 +プラズマ中に表面を暴露 した半導体基板を用いたものである。 First, after an oxide film 304 for element isolation is formed by a thermal oxidation method, the gate portion is oxidized. Next, a poly Si (polycrystalline silicon: hereinafter abbreviated as poly Si) layer 306 for a gate electrode having a thickness of 30 Onm is formed by a CVD (chemical vapor deposition) method. The poly Si layer for the gate electrode was patterned into a desired shape by dry etching. The p-well 305 was formed by implanting boron at 1 × 10 13 at 0 ms / cm 2 and then performing a heat treatment at 1150 ° C. for 10 hours. The drain 307 and the source 308 were formed by implantation of arsenic ions of 2 × 10 15 at oms / cm 2 and heat treatment at 900 ° C. for 10 minutes. An interlayer oxide film 309 is formed by a CVD method, and a contact hole (c 0 ntact ho 1 e) is formed in the interlayer oxide film. Thereafter, an A1 electrode 310 was formed, and a MOS type transistor was fabricated. From the current and voltage characteristics of the gate oxide film of the M〇S type transistor, the yield rate of the gate oxide film and the leak current at the drain junction can be calculated. FIG. 7 shows the yield rate of the gate oxide film and the leakage current at the drain junction of the above-mentioned MS type transistor thus calculated. For comparison, FIG. 7 shows the respective values when an epitaxy semiconductor substrate manufactured without performing ion implantation is used as a conventional example. In FIG. 7, the manufacturing conditions in each example are as follows. Example 1 uses a semiconductor substrate in which F + ions are implanted at lxl 0 14 at oms / cm 2 into the surface by the method shown in FIG. The second embodiment uses a semiconductor substrate in which F + ions are similarly implanted into the surface at 1 × 10 15 atoms / cm 2 . Example 3 uses a semiconductor substrate in which CF 3 + ions are implanted on the back surface at 1 × 10 15 at oms / cm 2 by the method shown in FIGS. 3 and 4. Example 4 uses a semiconductor substrate whose surface is exposed to CF 3 + plasma.
従来例に比べて、 各実施例では何れもゲート酸化膜の良品率が増加し、 接合リ ーク電流が低減している。 ゲート酸化膜の良品率の向上は、 酸化膜特性を劣化さ せる重金属がゲッ夕リングされた為である。 接合リーク電流が減少したのは、 F が酸化膜/ S i界面のダングリングボンドを終端する効果を有している為である c 本実施例の中では、 CF3 +イオン打ち込みを施した場合が、 ゲート酸化膜の良品 率、 接合リーク電流特性が共に最も良い結果が得られた。 これは炭素のゲッタリ ング効果及び Fの終端効果が両方得られる為である。 また、 F +イオンの打ち込 み量依存性に着目すると、 1 X 1014 at oms/cm2の打ち込み量よりは 1 X 1015a t oms/cm2の打ち込み量の方が、 ゲート酸化膜の良品率、 接合 リーク電流特性とも良好である。 これは、 イオン打ち込み量が多いほど、 基板内 に残留する結晶欠陥と F量 (弗素量) が多いことが原因していると考えられる。 しかし、 イオン打ち込み量が 1 X 1016a t oms/cm2を超えると、 結晶欠 陥がェピタキシャル層にまで成長しやすくなるので、 イオン打ち込み量は、 それ 以下が適当である。 また、 イオン打ち込みを行うのに要する時間も長くなるので コス卜の増大にもつながる。 CF 3 +プラズマ中に表面を暴露した基板にェピタキ シャル層を形成した場合も、基本的に、 CF 3+イオン打ち込みを施した基板とほ ぼ同様の効果が得られた。 In each of the embodiments, the yield rate of the gate oxide film is increased and the junction leak current is reduced in each of the embodiments as compared with the conventional example. The improvement in the yield rate of the gate oxide film is due to the gettering of heavy metals that deteriorate the oxide film characteristics. If the junction leakage current is decreased, F is in the order in which c present embodiment has the effect of terminating dangling bonds in the oxide film / S i interface, which has been subjected to CF 3 + ion implantation However, the best results were obtained for both the yield rate of the gate oxide film and the junction leakage current characteristics. This is because both the gettering effect of carbon and the termination effect of F are obtained. Focusing on the implanted dose dependence of F + ions, the implanted dose of 1 × 10 15 at oms / cm 2 is larger than that of 1 × 10 14 at oms / cm 2 in the gate oxide film. Good product ratio and good junction leakage current characteristics. This is thought to be due to the fact that the larger the amount of implanted ions, the larger the amount of crystal defects and the amount of F (fluorine) remaining in the substrate. However, when the ion implantation amount exceeds 1 × 10 16 at oms / cm 2 , the crystal defects easily grow into the epitaxy layer. The following are appropriate: In addition, the time required for performing ion implantation becomes longer, which leads to an increase in cost. When the epitaxy layer was formed on the substrate whose surface was exposed to CF 3 + plasma, basically the same effect as that of the substrate subjected to CF 3 + ion implantation was obtained.
上記の他に、 C1イオン、 Brイオン、 CFxHyイオン (x + y=3)等のィ オンを用いたときもほぼ同様の効果が得られた。 ただし、 CH3イオン用いたと きは、効果の値は他の場合よりも劣っていたが、効果を奏することは変わりない。 本発明によれば、 ゲッ夕リング能力が高く、 且つ特性の優れた半導体素子を製 造することのできるェピタキシャル半導体基板を得ることが出来た。 In addition to the above, C1 ions, Br ion, CF x H y ions (x + y = 3) substantially the same effect even when using the I-on or the like is obtained. However, when the CH 3 ion was used, the effect value was inferior to the other cases, but the effect was still exhibited. According to the present invention, it is possible to obtain an epitaxial semiconductor substrate capable of producing a semiconductor element having high gettering ability and excellent characteristics.
また、 本発明によれば、 ゲッ夕リング能力が高い半導体基板を用いた為、 特性 の優れた半導体装置が得られた。 産業上の利用可能性  Further, according to the present invention, a semiconductor device having excellent characteristics was obtained because a semiconductor substrate having a high gettering ability was used. Industrial applicability
以上のように、 本発明にかかる半導体装置の製造方法は、 ゲッ夕リング能力が 高く、 且つ特性の優れた各種半導体装置を製造することが出来る。 又、 本発明に かかる各種半導体装置は優れた特性を確保することが出来る。  As described above, the method for manufacturing a semiconductor device according to the present invention can manufacture various semiconductor devices having high gettering ability and excellent characteristics. Further, various semiconductor devices according to the present invention can ensure excellent characteristics.

Claims

請 求 の 範 囲 The scope of the claims
1 . 半導体基板に、 ハロゲン元素イオン、 ハロゲン元素を含む化合物からなるィ オン、 又は炭素元素及び水素元素からなるイオンをイオン打ち込みするか、 或い は半導体基板をハロゲン元素イオン 、ロゲン元素を含む化合物からなるイオン、 又は炭素元素及び水素元素からなるイオンのプラズマ中に曝す工程、 及び該ィォ ン打ち込みが行われた半導体基板又は該プラズマ中に曝された半導体基板にェピ タキシャル層を成長させる工程を有することを特徴とするェピタキシャル半導体 基板の製造方法。 1. The semiconductor substrate is ion-implanted with a halogen element ion, an ion composed of a compound containing a halogen element, or an ion composed of a carbon element and a hydrogen element. Exposing in a plasma of ions of, or ions of, a carbon element and a hydrogen element; and growing an epitaxy layer on the semiconductor substrate on which the ion implantation has been performed or on the semiconductor substrate exposed in the plasma. A method for manufacturing an epitaxial semiconductor substrate, comprising the steps of:
2 . 上記イオン打ち込みするイオンは、 ハロゲン元素イオンであり、 上記イオン 打ち込みは、 上記半導体基板のェビタキシャル層が形成される面に行うことを特 徴とする請求の範囲 1に記載のェピタキシャル半導体基板の製造方法。 2. The epitaxy semiconductor substrate according to claim 1, wherein the ion implantation is a halogen element ion, and the ion implantation is performed on a surface of the semiconductor substrate on which an epitaxial layer is formed. Manufacturing method.
3 . 上記ハロゲン元素イオンは、 フッ素イオンであることを特徴とする請求の範 囲 1ないし 2記載のェピタキシャル半導体基板の製造方法。 3. The method according to claim 1, wherein the halogen element ion is a fluorine ion.
4 . 上記イオン打ち込みするイオンは、 ハロゲン元素を含む化合物からなるィォ ンであり、 上記イオン打ち込みは、 上記半導体基板のェピタキシャル層が形成さ れる面と反対側の面に行うことを特徴とする請求の範囲 1に記載のェピ夕キシャ ル半導体基板の製造方法。 4. The ion-implanted ions are ions made of a compound containing a halogen element, and the ion-implantation is performed on a surface of the semiconductor substrate opposite to a surface on which an epitaxial layer is formed. 2. The method for producing an epitaxial semiconductor substrate according to claim 1, wherein
5 . 上記ハロゲン元素を含む化合物からなるイオンは、 炭素及び水素の内の少な くとも 1種の元素と、 ハロゲン元素とを含む化合物からなるイオンであることを 特徴とする請求の範囲 1又は 4記載のェピタキシャル半導体基板の製造方法。 5. The ion according to claim 1 or 4, wherein the ion comprising a compound containing a halogen element is an ion comprising a compound containing a halogen element and at least one element of carbon and hydrogen. The method for producing the epitaxy semiconductor substrate according to the above.
6 . 上記炭素元素及び水素元素からなるイオンは、 C H 3イオンであり、 上記ィ オン打ち込みは、 上記半導体基板のェビタキシャル層が形成される面と反対側の 面に行うことを特徴とする請求の範囲 1に記載のェビタキシャル半導体基板の製 造方法。 6. The ion comprising the carbon element and the hydrogen element is a CH 3 ion, and the ion implantation is performed on a surface of the semiconductor substrate opposite to a surface on which an epitaxial layer is formed. 2. The method for producing the epitaxial semiconductor substrate according to range 1.
7 . 請求の範囲 1から 6に記載のェビ夕キシャル半導体基板の製造方法により製 造されたェビタキシャル半導体基板と、 該ェピ夕キシャル半導体基板のェピタキ シャル層に設けられた半導体素子を有することを特徴とする半導体装置。 7. The method for manufacturing a shrinkable semiconductor substrate according to claims 1 to 6. A semiconductor device comprising: a manufactured epitaxial semiconductor substrate; and a semiconductor element provided in an epitaxial layer of the epitaxial semiconductor substrate.
8. ェピ夕キシャル層を有する半導体基板と、 該ェビタキシャル層に設けられた 半導体素子を有する半導体装置において、 上記半導体基板の深さ方向の所望の部 分が、 ハロゲン元素を含む領域又はハロゲン元素と炭素元素を含む領域であるこ とを特徴とする半導体装置。  8. In a semiconductor substrate having an epitaxial layer and a semiconductor device having a semiconductor element provided in the epitaxial layer, a desired portion in the depth direction of the semiconductor substrate is a region containing a halogen element or a halogen element. And a carbon element.
9.上記ハロゲン元素を含む領域のハロゲン元素の濃度は、 1 X 1017 a t om s/cm3から lx l 02 1 at o m s / c m3の範囲であることを特徴とする請 求の範囲 8に記載の半導体装置。 9. The concentration of halogen element in the region including the halogen element, 1 X 10 17 at om s / cm 3 from lx l 0 2 1 at oms / cm 3 in the range of billed, which is a range 8 3. The semiconductor device according to claim 1.
10. 上記ハロゲン元素と炭素元素を含む領域のハロゲン元素及び炭素元素の濃 度は、 いずれも l x l 01 7 a t oms/cm3から l x l 02 1 a t oms/c m3の範囲であることを特徴とする請求の範囲 8に記載の半導体装置。 10. The concentration of the halogen element and the carbon element in the region containing the halogen element and the carbon element is in the range of lxl 0 17 at oms / cm 3 to lxl 0 2 1 at oms / cm 3. 9. The semiconductor device according to claim 8, wherein
PCT/JP1998/004000 1997-09-08 1998-09-07 Method of manufacturing epitaxial semiconductor substrate, and semiconductor device WO1999013502A1 (en)

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Publication number Priority date Publication date Assignee Title
JPS5132272A (en) * 1974-09-13 1976-03-18 Hitachi Ltd HANDOTAISOCHINOSEIZOHOHO
JPS61240637A (en) * 1985-04-18 1986-10-25 Fujitsu Ltd Manufacture of semiconductor device
JPH0411736A (en) * 1990-04-28 1992-01-16 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH0661234A (en) * 1992-08-06 1994-03-04 Hitachi Ltd Production of semiconductor device

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Publication number Priority date Publication date Assignee Title
JPS5132272A (en) * 1974-09-13 1976-03-18 Hitachi Ltd HANDOTAISOCHINOSEIZOHOHO
JPS61240637A (en) * 1985-04-18 1986-10-25 Fujitsu Ltd Manufacture of semiconductor device
JPH0411736A (en) * 1990-04-28 1992-01-16 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JPH0661234A (en) * 1992-08-06 1994-03-04 Hitachi Ltd Production of semiconductor device

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