Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S5/00—Semiconductor lasers
  • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
  • H01S5/042—Electrical excitation ; Circuits therefor

Definitions

• the present invention relates to the field of semiconductor laser driver circuits.
• Figure 1 is a simplified schematic of a typical (Maxim MAX3261, Sony CXB1108AQ) integrated bipolar laser driver.
• the output transistors Ql and Q2 switch the modulation current Imod into an external laser depending on the state of the differential data inputs Vin+, Vin- .
• RL represents the typical matching impedance of a high speed laser (e.g., 25 ⁇ ) .
• Emitter follower transistors Q3 and Q4 provide level shifting and current gain to drive the output transistors .
• Additional emitter followers can be included for more level shifting and current gain ("A Versatile Si-Bipolar Driver Circuit with High Output Voltage Swing for External and Direct Laser Modulation in 10 Gb/s Optical-Fiber Links", H.-M. Rein et al . , IEEE Journal of Solid-State Circuits, Vol. 29, No. 9, September 1994) .
• Differential pair Q5 and Q6 provides voltage gain to ensure full switching of the output devices by switching current 13 through Rl or R2 depending on the input data.
• the inputs can be buffered by optional emitter followers (not shown) .
• the circuit of Figure 1 directly couples the output current from the collector of transistor Ql to the laser. Since the supply voltage must be greater than the headroom needed by the current source Imod, plus the output transistor Ql, plus the laser, this topology is not capable of operation with a supply voltage of 3V. For example, transistor Ql and current source Imod both need about IV of headroom for high speed operation, the typical DC laser drop is 1.5V, and a modulation current of 60mA multiplied by the 25 ⁇ of RL is 1.5V. This is a total of 5V, which clearly shows that operation on a single 3V DC supply is not possible.
• the circuit of Figure 2 can be used to AC couple the output current from the collector of transistor Ql to a semiconductor laser.
• an inductor to set the DC voltage at the collector of Ql to be equal to the supply, adequate headroom is achieved.
• the value of the inductor LAC is chosen to limit droop during long consecutive streams of data ones or zeros and the value of the capacitor CAC is chosen to provide the desired high pass cutoff frequency.
• the use of this output topology allows sufficient headroom for 3V operation. This topology is commonly used in RF applications, and it has been previously applied to semiconductor lasers. Similar AC coupling networks with resistive pull-up have been previously implemented.
• a disadvantage of the circuit of Figure 1 is that the emitter follower currents II and 12 must be approximately equal to the peak base current (caused by collector to base capacitance) of the output transistors Ql and Q2. At high data rates and with large modulation current, II and 12 can become very large (10 's of mA) . Transistors Q3 and Q4 must therefore be large devices and will also have significant transient base current. This sets a maximum value for Rl and R2 and can cause the value of current 13 to be larger than desired. The value of current 13 multiplied by Rl (or R2) results in the peak magnitude of the differential voltage signal across the bases of transistors Ql and Q2. This signal must be large enough to fully switch the modulation current at its maximum value . The required amplitude is typically 400mV for 60mA of modulation current.
• a semiconductor laser driver circuit that provides single supply operation over a wide supply voltage range (e.g., 3V to 5.5V), is capable of high speed data transmission, and is programmable over a wide laser modulation current range (such as 5mA to 60mA) is disclosed.
• the circuit includes temperature sensitive circuits to adjust for changes in Vbe over the operating temperature range, and to adjust a bias current to maintain transistor g m in the presence of temperature changes. Also included is an adaptive drive feature to accommodate different laser drive currents.
• Figure 1 is a simplified schematic of a typical prior art integrated bipolar laser driver.
• Figure 2 is illustrates AC coupling of the output current to a semiconductor laser using an inductor to set the DC voltage at the collector of the laser drive transistor to be equal to the supply to achieve adequate headroom.
• Figure 3 is a circuit diagram for a first embodiment of the present invention having a switch driver with differential active pull-down.
• Figure 4 is a circuit similar to the circuit of Figure 3 and includes a resistive level shift R3 controlled by a supply and temperature dependent current source 17.
• Figure 5 is a circuit similar to the circuit of Figure 4 and includes the addition of a level shifting input stage that is directly compatible with standard PECL logic .
• Figure 6 is a circuit similar to the circuit of Figure 4 and includes additional circuit components to implement an adaptive drive feature to accommodate different laser drive currents.
• Figures 7 through 10 present circuits for providing bias currents with various characteristics for the circuit of Figure 6.
• a first embodiment of the present invention may be seen.
• the output transistors Ql and Q2 are driven by two parallel circuits. One circuit pulls the base of the conducting output device high, and the other circuit pulls the base of the non-conducting output device low.
• the first circuit comprised of differential pair Q5 and Q6 , load resistors Rl and R2 , emitter follower transistors Q3 and Q4, and current sources II and 12, is the identical topology as Figure 1.
• the emitter of transistor Q3 or Q4 whichever is higher, pulls up on the base of the conducting output device.
• the additional second circuit is comprised of emitter followers Q9 and Q10, differential pair Q7 and Q8, and switched current source 14.
• transistors Q7 and Q8 are connected such that the current 14 is switched to the base of the non-conducting output device Ql or Q2 , thereby pulling it down.
• the first advantage of the circuit of Figure 3, when compared to the circuit of Figure 1, is improved high frequency performance with lower power consumption.
• the differential data input signal is being switched from a logic zero to a logic one.
• the voltage at the base of transistor Q9 is moving higher and the voltage at the base of transistor Q10 is moving lower.
• the voltage at the collector of transistor Q5 which is connected to the base of transistor Q4, is moving lower because current source 13 is being switched through transistor Q5.
• the voltage at the connection of the collector of transistor Q6 and the base of transistor Q3 is moving higher since 13 is being switched away from transistor Q6.
• the transient voltages at the emitters of transistors Q3 and Q4 are moving in the same direction as the voltages at the bases.
• the base of transistor Q8 is moving higher, and the base of transistor Q7 is moving lower. This action switches current source 14 through transistor Q8 (and away from transistor Q7 ) at the moment that it is most needed to supply the current surge coming from the base of transistor Q2.
• the end result is very fast switching of the modulation current Imod from transistor Q2 to transistor Ql .
• the output current from the collector of transistor Ql flows through the coupling capacitor CAC and increases the laser current, signifying a transition from a logic zero to a logic one.
• the propagation delay of the pull-up signal path consisting of differential pair Q5 and Q6 and emitter followers Q3 and Q4 is similar to the propagation delay of the pull-down signal path consisting of emitter followers Q9 and Q10 and differential pair Q7 and Q8. This delay match results in improved output current edge speed when compared to other active pull-down circuits.
• bias voltages at the coupled emitters of transistors Ql and Q2 are maintained at a constant voltage of about IV.
• This value of IV which results in a voltage of about 1.8V at the bases of transistors Ql and Q2 , allows sufficient headroom for the AC coupled topology of Figure 2 when using a 3V supply, and allows the DC coupled topology of Figure 1 for moderate modulation currents when using a 5V nominal supply.
• Use of the DC coupled topology is desired when possible to eliminate the need for the inductive AC coupling network.
• Figure 4 shows a circuit topology with a resistive level shift R3 controlled by a supply and temperature dependent current source 17.
• a capacitor can be included across resistor R3 to minimize transient voltage variation at the connection of resistors Rl, R2 , R3 and current source 17.
• the voltage across R3 is simply the value of resistor R3 multiplied by the sum of the currents 13 and 17.
• the optimum value of the current 17 is given by:
• VCC is the supply voltage
• Vbe is the base to emitter voltage of a bipolar device on the process being used to implement the circuit, specifically the combination of devices Q3 and Ql, and devices Q4 and Q2
• the IV is the headroom for Imod.
• VCC IRS * R8 + 2Vbe (the Vbes of Q16 and Q17)
• Equation (2) can now be made identical to equation (1) with proper component value selection.
• FIG. 5 shows a circuit containing the circuit of Figure 4 and the addition of a level shifting input stage that is directly compatible with standard PECL logic .
• the circuit of Figure 5 contains input gain stage transistors Q13 and Q14 with current source 112 and load resistors R4 and R5. This stage is buffered by emitter followers Qll and Q12 with bias current sources 110 and 111. The level shift is provided by current sources 18 and 19 through load resistors R6 and R7. Speed-up capacitors Cl and C2 are included to compensate for device and metal interconnect capacitance. Note that 14 has been replaced with a resistor because the additional voltage drop caused by transistors Qll and Q12 reduces the headroom on 14 to a value lower than that required by a transistor current source.
• the current through 14 is set by the voltage at the emitters of transistors Q7 and Q8, which is related to the base to emitter voltages of switch transistors Q7 and Q8, emitter followers Q9 through Q12, and the level shift voltage across resistors R6 and R7.
• the current of 14 it is desired for the current of 14 to increase with temperature. This increasing current compensates for the decreasing transconductance (g m ) of transistors Ql through Q4 and Q7 and Q8 in the final stage, resulting in nearly constant output current rise time over temperature.
• Vcc is the supply voltage
• Vbe is the base to emitter voltage of a bipolar device on the process being used to implement the circuit, this time the combination of devices Q9 and Qll
• the 1.2V is the silicon bandgap voltage (transistor Q8 in the specific path being considered) .
• a major problem associated with the design of high speed semiconductor laser driver circuits is satisfying the need for a wide range of modulation current .
• Emerging laser technologies are achieving greater efficiencies resulting in smaller required modulation currents.
• existing devices require modulation currents of 60mA or more.
• modulation currents of 60mA or more.
• the output device size must be large enough to reliably conduct the largest required modulation current. Large devices obviously will have higher junction and metal interconnect capacitance.
• the signal swing across the bases of the output transistors Ql and Q2 must also be large enough to fully switch the output devices with the maximum modulation current. As mentioned above, this drive signal swing is on the order of about 400mV per side with 60mA of laser modulation current. If the modulation current is reduced by an order of magnitude without adjusting the switch transistor drive characteristics, excessive overshoot and ringing results on the output current waveform. These aberrations are a result of direct current injection through the collector to base capacitance of transistors Ql and Q2 and indirect current injection caused by the capacitance of current source Imod. This second effect is caused by transient common mode voltage swings at the coupled emitter of transistors Ql and Q2.
• the circuit of Figure 6 includes additional circuit components to implement the adaptive drive feature discussed above.
• an additional current source 115 must be introduced to counteract the DC effect of 13 across R3. In other words, 13 is reduced at low modulation current to reduce the signal amplitude across the collectors of transistors Q5 and Q6 , and 115 is increased at low modulation currents to maintain the proper DC level shift across R3 in spite of the reduction in the current 13.
• a current variation could be implemented as part of current sources 18 and 19, or 14 could be directly adjusted if the specific requirements allowed a transistor current source for 14.
• the method described above is preferred to minimize current source complexity because of the available headroom at the collectors of transistors Q13 and Q14. Circuits to provide the required dependent current sources mentioned have been designed using common analog circuit design practices.
• Figure 7 provides the desired supply and temperature dependence of equations (1) , (2) and (3) .
• the relative emitter area of transistors Q15 and Q17 and other component values can be adjusted to achieve DC current gain to minimize bias current power dissipation.
• the circuit of Figure 8 is used to generate a differential voltage that is proportional to modulation current for use in the circuits of Figure 9 and Figure 10.
• the voltage at node DriveH is VCC - 118 * RIO - Vbe and the voltage at DriveL is VCC - (Imod/X) * R9 - Vbe.
• the differential voltage DriveH - DriveL is Imod/X * R9 - (118 * RIO), which is proportional to the modulation current Imod if X is a constant.
• the current source Imod/X can be easily implemented as a current mirror addition to transistor current source Imod.
• Figure 9 is used to derive the level shift currents 113 and 114.
• degeneration resistors Rll and R12 in the emitters of differential amplifier transistors Q20 and Q21, the current through transistor Q21 is inversely proportional to the differential "Drive" signal as desired.
• the current through transistor Q21 is equal to current source 119 at low modulation currents and zero at high modulation currents if the values of resistors Rll and R12 are selected properly.
• resistors Rll and R12 are equal, and DriveH exceeds DriveL by at least 119 * Rll, then all of the current 119 will flow through transistor Q20.
• Figure 10 is used to generate the desired variation of current sources 13 and 115.
• the current through transistor Q22 increases with Imod and the current through transistor Q23 decreases with Imod because of the nature of the differential "Drive" signal.
• current mirror transistors Q24 through Q31 are included to transfer the currents in transistors Q22 and Q23 to the collectors of transistors Q29 and Q31, respectively.
• the collector current of transistor Q29 is approximately proportional to Imod
• 115 at the collector of transistor Q31 is approximately inversely proportional to Imod, as desired.
• Constant current source 121 is included to set the minimum voltage swing across the collectors of transistors Q5 and Q6 in Figure 6.
• Additional emitter followers can be added to buffer the PECL inputs.
• current source 14 could be a transistor current source and varied directly for adaptive drive.
• Additional adaptive drive can be accomplished by directly varying current sources II and 12. However, since the topology allows for significant reduction in the value of these current sources, this is a minor improvement .

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• Physics & Mathematics (AREA)
• Condensed Matter Physics & Semiconductors (AREA)
• General Physics & Mathematics (AREA)
• Electromagnetism (AREA)
• Optics & Photonics (AREA)
• Semiconductor Lasers (AREA)
• Amplifiers (AREA)

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• 1997
  • 1997-07-03 US US08/888,026 patent/US5883910A/en not_active Expired - Fee Related
• 1998
  • 1998-06-24 JP JP50723999A patent/JP2002508116A/ja not_active Ceased
  • 1998-06-24 IL IL13381998A patent/IL133819A/en active IP Right Grant
  • 1998-06-24 CA CA002294753A patent/CA2294753C/en not_active Expired - Fee Related
  • 1998-06-24 WO PCT/US1998/013201 patent/WO1999001914A2/en not_active Ceased
  • 1998-06-24 EP EP98931580A patent/EP0992091A2/en not_active Withdrawn
  • 1998-06-24 KR KR1019997012614A patent/KR20010014427A/ko not_active Withdrawn

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