WO1998044687A1 - Modem utilisant une barriere isolante capacitive et un coupleur insolant, et circuit integre utilise par ce modem - Google Patents

Modem utilisant une barriere isolante capacitive et un coupleur insolant, et circuit integre utilise par ce modem Download PDF

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Publication number
WO1998044687A1
WO1998044687A1 PCT/JP1998/001431 JP9801431W WO9844687A1 WO 1998044687 A1 WO1998044687 A1 WO 1998044687A1 JP 9801431 W JP9801431 W JP 9801431W WO 9844687 A1 WO9844687 A1 WO 9844687A1
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WO
WIPO (PCT)
Prior art keywords
circuit
insulating
signal
bra
input
Prior art date
Application number
PCT/JP1998/001431
Other languages
English (en)
Japanese (ja)
Inventor
Yasuyuki Kojima
Takayuki Oouchi
Noboru Akiyama
Masahiro Iwamura
Atsuo Watanabe
Minehiro Nemoto
Seigou Yukutake
Nobuyasu Kanekawa
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to EP98911091A priority Critical patent/EP0973305A1/fr
Priority to KR1019997008865A priority patent/KR20010005793A/ko
Priority to JP54144598A priority patent/JP4005145B2/ja
Publication of WO1998044687A1 publication Critical patent/WO1998044687A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0266—Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
    • H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0292—Arrangements specific to the receiver end

Definitions

  • the present invention relates to a modem device using a capacitive insulating barrier, an insulating bra, and an integrated circuit used for the modem device.
  • the present invention relates to a semiconductor element, a capacitor formed on the semiconductor element, and particularly to an insulating barrier which is a high withstand voltage capacitor which does not destroy the element even when a high voltage is applied and does not allow a dangerous voltage to pass to the secondary side.
  • Couplers or isolators or insulated amplifiers (hereinafter referred to as insulation bras) that transmit electrical signals using the I / O, and application circuits using the insulation bras, especially line interface circuits such as modem devices and their Ic, and
  • the present invention relates to a modem device and a system using the same. Background art
  • the signal detection part may be necessary to insulate the signal detection part from the signal processing part, such as the sensor and the signal processing circuit. Also known as the signal processing part, such as the sensor and the signal processing circuit. Also known as the signal processing part, such as the sensor and the signal processing circuit.
  • the signal voltage is about 100 OmV, but it is assumed that commercial power supply will come in contact with them, so the common mode noise voltage may be 100 V or more.
  • Insulation power from these points Bras and line interfaces have common issues in terms of high withstand voltage, miniaturization, and cost reduction.
  • -Insulation brassier is the function of the isolation transformer itself, but it has the problem that noise is mixed in the signal transmission.For example, if a large common mode noise voltage from the commercial power supply is added, the transformer for small signal transmission will In some cases, a transformer-type insulating bra using a dedicated pulse transformer is used.
  • an insulation power transformer using an insulation transformer generally has a large mounting form and tends to be expensive.
  • an optical power coupler combining a light emitting element and a light receiving element is used.
  • Isolation amplifiers have been devised.
  • the characteristics of the optical brass-type insulated amplifier are liable to change with temperature and the like, and improvements in the number, arrangement, and circuits of the light emitting and receiving diodes have been proposed for high accuracy, but are expensive.
  • a semiconductor process of other substances for light emission and light reception is required in addition to the silicon semiconductor process. The use of the process is expected to be extremely expensive and cannot be realized in practice.
  • Capacitive insulating bras have been developed for the purpose of miniaturization, high reliability, and low cost.
  • a ceramic capacitor for power or surge protection is known as a high withstand voltage capacitor technology as an individual component of an insulation barrier, and a circuit block for signal transmission using the same is a capacitive insulating amplifier or a capacitive insulating capacitor. It is called a bra and has been used since the 1970s.
  • the PWM method (called the pulse width modulation method or the duty control method) is mainly used as the transmission method when transmitting signals through the capacitive insulating barrier.
  • the capacitive insulation bra uses a duty cycle modulation type insulation method by using a small-capacity capacitor insulation barrier formed on a ceramic substrate and a floating comparator.
  • Amplifiers have been proposed.
  • the transmission waveform is converted to a differential waveform using an insulation barrier as small as 1 to 3 pF, and FM (frequency modulation) and PWM modulation waveforms are reproduced from the differential waveform. After that, the technology of an isolated amplifier for demodulation has been proposed.
  • the technology prior to the 528 patent is a component that is separate from an insulation barrier with high withstand voltage performance, an input circuit that receives input signals to create PWM waveforms, and an output circuit that reproduces and demodulates PWM waveforms.
  • Mounted in combination it is configured as one insulating bra.
  • a capacitive insulating barrier is formed on a ceramic substrate, and two or more semiconductors are mounted on the same package. The chip is mounted to form an insulating bra.
  • the configuration uses many components.
  • a capacitive insulating barrier and a PWM transmission method were used based on a schematic circuit diagram and description of the principle. It is shown that the manufacturing method is to form an insulating bra consisting of a capacitive insulating barrier and a PWM circuit on a monolithic semiconductor using a DI (dielectric isolation) process, and to combine these insulating bras to transmit voice band signals.
  • DI dielectric isolation
  • the conventional technologies described above use a capacitive insulating barrier and a capacitive insulating barrier in realizing a monolithic IC-based insulating power circuit, a monolithic IC-based application circuit, and a monolithic IC-based line interface circuit. It does not disclose any technique for configuring and operating the circuits, their arrangement, and the insulation method between the arranged circuits on a semiconductor substrate. Therefore, when making a monolithic IC, It is not known how to achieve the dielectric strength in this way, or the characteristics of the high withstand voltage capacity created on the semiconductor.
  • An object of the present invention is to realize a small and economical line interface circuit and a modem device while incorporating necessary insulating means between a line and a terminal, and a monolithic insulating barrier required for this purpose. And to realize a monolithic insulating bra using the insulating barrier, and an application circuit IC using the same, particularly a line interface circuit IC.
  • Another object of the present invention is to provide a technique for forming a capacitive insulating barrier on a semiconductor substrate.
  • Still another object of the present invention is to provide a technique for forming an insulating power plug using a capacitive insulating barrier on a semiconductor substrate.
  • Still another object of the present invention is to provide a technique for improving the breakdown resistance of an insulated coupler against surge voltage.
  • Still another object of the present invention is to reduce the size and cost of a modem device and system by using an insulating bra.
  • the following means are used to solve the conventional problem of large size and high cost.
  • an insulating band (hereinafter referred to as an insulating band) reaching the insulating layer is formed on the surface of a semiconductor wafer (SO I wafer) having a buried insulating layer as an inner layer. Forms an insulating barrier between the sidewalls
  • a circuit for receiving a capacitor output is provided with at least an amplifying means for a capacitor output signal such as an amplifier / comparator. 7
  • the line interface circuit of the modem device, etc. shall be provided with a plurality of monolithic insulating bras, a line side circuit and a terminal side circuit.
  • AFE Analog Front End
  • a semiconductor wafer having a buried insulating layer as an inner layer is processed to form an insulating barrier, an insulating bra, an application circuit of the insulating bra, particularly a line interface circuit, and if necessary, a wiring with the insulating layer.
  • a semiconductor IC is formed by stacking layers and further forming a protective layer also serving as insulation. Each circuit is surrounded and insulated by an insulating layer, an insulating band and an insulating protective layer.
  • An insulating band is a band-like insulating pattern with a width of about 1 to 3 microns, for example, reaching the insulating layer from the surface of the semiconductor layer (the thickness is equal to the thickness of the semiconductor layer, for example, 10 to 50 microns).
  • the insulation band is formed by a trench method in which a predetermined pattern of grooves extending from the semiconductor surface to the insulating inner layer is formed and filled with an insulator, or an ion implantation method in which oxygen ions are implanted in the semiconductor layer to create an insulating region.
  • a trench method in which a predetermined pattern of grooves extending from the semiconductor surface to the insulating inner layer is formed and filled with an insulator, or an ion implantation method in which oxygen ions are implanted in the semiconductor layer to create an insulating region.
  • a monolithic line interface having a plurality of capacitive insulating bras, a line side circuit and a terminal side circuit is provided.
  • the timing of the operating clocks of DSP and AFE and these insulation braces is synchronized.
  • the carrier clock of the insulating bra for modem signal reception is recovered from the clock of the power bra for transmitting the DC closing control signal and used.
  • the CMOS switch is driven by a charge pump circuit using an insulating barrier to close the DC.
  • the insulating barrier in the insulating bra of the present invention forms an electrode region surrounded by an insulating band, and a plurality of electrode regions share a part of the insulating band, and a shared length obtains a required capacitance value. Arrange them so that they are the same length to form a capacitor.
  • the shape and arrangement of the insulating band may be set so that three or more electrode regions share two or more insulating regions, that is, a series-connected capacitor may be formed by multiple trenches. .
  • the buried insulating layer has a thickness having an insulating performance corresponding to the width of the insulating band.
  • the insulating bra of the present invention is realized by forming the insulating barrier, the input circuit, and the output circuit on the same wafer. Each circuit is surrounded by an insulation band to insulate it from other parts. Insulation barrier should be placed at the boundary between input circuit area and output circuit area in principle. In addition, these circuit regions and insulating barriers are put together and further surrounded by an insulating band.
  • the input circuit and the output circuit each have a PWM modulation circuit and a PWM demodulation circuit, or, depending on the purpose, other circuits such as a ⁇ ⁇ modulation circuit and a demodulation circuit for audio frequency band signals.
  • the digitized circuit is also included in the axial direction.
  • a protection circuit composed of a non-linear element such as a diode is arranged between the insulation barrier and the input circuit and the output circuit. The protection circuit is located inside the circuit area.
  • the application circuit of the present invention is realized by arranging an application circuit region surrounded by an insulating band on an insulating bra.
  • the insulating barrier may be arranged along the insulating barrier array line.
  • the carrier clock is synchronized as necessary.
  • the insulation brass to the circuit interface circuit in order to include the CMOS circuit in the circuit area, in particular, connect the CMOS circuit area further to the power supply line and connect the PM ⁇ S group to the ground line and the NM ⁇ S They may be divided into groups and separated by insulating bands.
  • the power wiring is laid between multiple insulation bras. Each insulation bra may be surrounded by a power line and a ground line.
  • CMOS circuit has the advantages of voltage control that requires no control current and high off-resistance, but tends to cause latch-up, which is a phenomenon of penetration between PM0S and NMOS, including parasitic transistors.
  • latch-up which is a phenomenon of penetration between PM0S and NMOS, including parasitic transistors.
  • the separation can be made difficult by separating the regions.
  • a high breakdown voltage in the thickness direction is realized, and by forming two electrode regions having an insulating band shared on the same wafer, an extremely small insulating barrier is realized.
  • an extremely small insulating barrier is realized.
  • a very small insulating bra can be realized.
  • stacking electrode regions and connecting capacitors in series to achieve a high withstand voltage in the horizontal direction, even if the width of one insulating band cannot be increased due to process restrictions, a higher withstand voltage can be achieved. .
  • by arranging the intermediate electrode to be floating when arranging the series capacitors it is possible to reduce the number of wires that cross over the strong electric field portion.
  • the uniform insulation performance can be achieved by arranging the capacitive insulating barriers such as electrodes and insulating bands.
  • FIG. 1 is a circuit block diagram of a modem device according to one embodiment of the present invention.
  • FIG. 2 is an operation timing chart of the modem device of FIG.
  • Fig. 3 is a circuit block diagram of the insulation bra in Fig. 1.
  • FIG. 4 is an operation timing chart of the insulating bra of FIG.
  • Figure 5 synchronizes the timing chart of the modem signal processing with the insulation bra.
  • Fig. 6 is a timing chart showing the effect of timing synchronization.
  • FIG. 7 shows the layout of the IC of the line interface circuit in the circuit of FIG.
  • Fig. 8 is a structural diagram of the insulation bra at IC in Fig. 7.
  • FIG. 9 is a structural diagram of the insulating barrier at IC in FIG.
  • FIG. 10 shows a modification of the layout of the line interface IC.
  • FIG. 11 is a circuit block diagram of the insulation bra system applied to the present invention.
  • FIG. 12 is a circuit block diagram of a modem device according to another embodiment of the present invention.
  • FIG. 13 is a timing chart showing the effect of another embodiment of the modem.
  • FIG. 14 is a structural diagram of another embodiment of the IC of the line interface circuit.
  • FIG. 15 is a structural view of another embodiment of the insulating barrier of the present invention.
  • FIG. 16 is a structural view of an embodiment of an insulating bra according to the present invention.
  • FIG. 17 is a structural view of another embodiment of the insulating bra of the present invention.
  • FIG. 18 is a structural view of still another embodiment of the insulating bra of the present invention.
  • FIG. 19 is a structural diagram of a modem device using the line interface IC of the present invention.
  • FIG. 20 is a circuit block diagram of an embodiment of a line interface circuit incorporating a monolithic insulating coupler of the present invention.
  • FIG. 21 is a diagram of the layout of I C (I-AFE) of the line interface circuit of FIG.
  • FIG. 22 is an embodiment of a modem circuit using the I C (I-AFE) of FIG. 21.
  • FIG. 23 shows an embodiment of a modem device using the I C (I-AFE) shown in FIG. 21.
  • FIG. 24 is an embodiment of another communication apparatus using the monolithic insulating bra of the present invention.
  • FIG. 25 shows another embodiment of the monolithic insulating bra of the present invention.
  • FIG. 26 is a circuit block diagram of another embodiment of the monolithic insulating bra of the present invention.
  • Fig. 27 is a detailed circuit diagram of Fig. 26.
  • FIG. 28 is an operation timing chart of the detailed circuit diagram of FIG.
  • FIG. 29 is a circuit block diagram of an embodiment in which a plurality of insulating brass are mounted on the same SOI substrate.
  • FIG. 1 is a circuit block diagram of a modem device according to one embodiment of the present invention.
  • 1 is a modem
  • 2 is a line interface circuit
  • a modem circuit 1 is a DSP (Digital Signal Processor).
  • the line interface circuit 2 is composed of a terminal-side circuit 5, an insulating plug 6, a line-side circuit 7, and a high-voltage circuit 8.
  • DSP 3 and AFE 4 in modem 1 are as follows: DSP 3 handles digital signal processing, and AFE handles the interface between digital and analog circuits.
  • DSP 3 is responsible for most of the modem functions. That is, the DSP 3 exchanges digital information with the terminal, and performs modulation, demodulation, encoding, decoding, and filtering by digital signal processing, and exchanges digital signals with the AFE 4.
  • AFE4 is ADAnal og to
  • the line interface circuit 2 is also referred to as DAA (Direct Access Arrangement), which connects the analog signal of the modem directly to the telephone line, and at the same time, exchanges the signal corresponding to the modem with the line-side circuit 7 and the high-voltage circuit 8
  • DAA Direct Access Arrangement
  • a safety interface function between the exchange and the terminal is required. It is a security boundary.
  • the DSP 3 has ROM (Read Only Memory) 31, PU (Processing Unit) 32, RAM (RAM (RAM (RAM) (ROM (Read Only Memory) 31, PU (Processing Unit) 32, RAM (RAM (RAM (RAM).
  • ROM Read Only Memory
  • PU Processing Unit
  • RAM Random Access Memory
  • Random Access Memory 33, system interface 34, SOR (serial output interface) 35, SIR (serial input interface) 36, I / O (input / output interface) 37, CONT (control unit inside DSP) 38 It is connected by three buses 39-1, 39-2, and 39-3.
  • DSP 3 is controlled by software in the DSP system control circuit CONT38, operates at about 40 MHz, and receives signals from the terminal device through HOST-IF. Operates according to commands and exchanges data.
  • a normal modem has the capability of simultaneous transmission and reception. When input from the HOST-IF, the transmission data is temporarily stored in the RAM 33 and is used for signal conversion and encoding using the data in the ROM 31 and the transmission signals already stored.
  • the I / O 37 has a control signal input / output function for controlling external circuits from the DSP 3.
  • the AFE 4 includes a DA converter 41, a 0 converter 42, and a clock divider 43, and mainly serves as an interface means for the DSP 3, which is responsible for filters and modulation / demodulation processing, to input and output modem signals.
  • the terminal side circuit 5 is a data and clock connection circuit.
  • the insulation bra 6 includes a transmission path 61, a reception path 62, an OFHK path 63, and a Rdet path 64, and details of the internal configuration and operation will be described later.
  • the circuit 7 is composed of a 2-wire Z4 wire conversion circuit 71, a SW control circuit 72, and an OSC (local transmission circuit) 73.
  • the 2-wire Z4 wire conversion circuit 71 has a total of 4 lines for the transmission signal path and the reception path.
  • the high-voltage circuit 8 includes a DC closing circuit 81 and a Ring detection circuit 82 for detecting a ringing signal.
  • the DC closing circuit 81 is connected to two terminals TIP and RING which are connected to a line. This is a means for connecting and forming a DC loop by the path 63 of the control signal OFHK and the SW control circuit 72.
  • the first feature of the configuration of the modem circuit is that the circuit on the line side and the circuit on the terminal side are separated by four insulating brass 6. Naturally, the power supply is also separated, and the line side power supply uses the power supply from the exchange, and the terminal side uses the terminal power supply.
  • the second feature is that the basic clock is supplied from DSP 3.
  • the timing signal is converted from the clock circuit 43 using the clock signal DSPCLK supplied from the CONT 38 of the modem 3 to the AFE AD conversion timing (MCLKS) of the AFE in the modem.
  • DA conversion timing (MCLKR) and data transmission timing of the modem 3 are obtained and supplied to the line interface circuit 2 for transmission to the transmission path 61 of the insulation bra 6 and the OFHK path 63 of the insulation bra for control signal transmission. .
  • the modem signal reception path 62 uses the recovered clock of the OF HK path 63, and the Rdet path 64 of the control signal reception isolation coupler is significant only when receiving the RI NG signal from reception standby. Oscillation shall be controlled. By doing so, the timing other than the Rdet signal path is synchronized with the operation timing of the DSP 3 in the modem 1. By doing so, the following effects can be obtained.
  • FIG. 2 shows an example of a timing chart for transmission (a) and reception (b). At the time of transmission, first, the DSP 3 controls the IO 37 according to a command from the terminal to turn on the DC closing control signal OFHK (T1).
  • a dial signal is transmitted from the line interface circuit 2. This is done by turning the OFHK pin on and off according to the line standard and turning on and off the DC connection. For example, in Japan it is 1 OPPS (pulse per second and below) or 2 OPPS.
  • the terminal waits for the line to be connected to the other modem (T4), activates modem 1, and starts transmission.
  • the modem 1 generates transmission signals TX A + and TXA— through the SOR 35 of the DSP 3 and the DA converter 41 of the AFE 4 according to a predetermined procedure, and starts communication with the other modem.
  • the circuit interface circuit separates the TX A signal from the transmit path 6 of the isolated coupler 6.
  • the signal is supplied to the 2-wire Z-wire conversion circuit 71 through 1.
  • the 2-wire 4-wire conversion circuit 71 reduces the wraparound to the receiving side, and transmits the transmission signal from the TIP and RING terminals to the line through the DC closing circuit 81.
  • the partner modem responds to this transmission signal (T5), the partner modem's signal can be seen on the line, and follows the reverse route.
  • the received signal is selected by the 2-wire 4-wire conversion circuit 71, and the isolated coupler 6
  • the signal is passed to the modem 1 through the receiving path 62, the 80-to-80 converter 42, and the SIR 36 of the DSP 3, and is amplified, filtered, demodulated, and restored by the DSP signal processing. And passes it to the host as received data.
  • the terminal issues a stop command to each modem after exchanging stop information between the terminals using a higher-level protocol of the modem signal (RS off), and the modem stops the signal in response thereto. (T6, ⁇ 7).
  • the OFHK is turned off. In this way, a signal like “between TI and RING” in FIG. 2 appears between the line connection terminals TI and RING corresponding to the timings from ⁇ 1 to ⁇ 8. .
  • the line Upon reception, the line is activated by the RI NG signal from the line side (T 1).
  • the line interface circuit detects this by the RI NG detection circuit 82, the line interface circuit immediately transmits it to the modem 3 through the Rdet path 64 of the insulating coupler 6. I do.
  • the modem 3 knows this through the 1-node circuit 37, and responds to this to output a DC closing control signal ⁇ F HK and perform DC closing similarly to the transmission (T2).
  • the central office stops the RI NG signal (T3), so wait for the line to settle (T4).
  • the other modem sends the modem signal, and this signal is sent to the RXA + and RXA—
  • the receiving modem recognizes that it is a modem signal, it starts transmitting in response to this (T5).
  • T5 When the communication is completed, the sequence ends with T6, T7, and # 8, almost the same sequence as when transmitting. Receive these During operation, a signal (schematically shown) as shown in the figure appears on the line corresponding to each timing from T1 to T8. This operation itself is normally performed according to the standard.
  • FIG. 3 is a circuit block diagram of one path of the insulating coupler 6 in the embodiment of FIG. 1.
  • 9-1 and 9-12 denote a capacitive insulating barrier described later
  • 21 denotes an input circuit
  • 22 denotes an input circuit.
  • I an output circuit, which implements a security boundary between the modem terminal and the exchange by means of this insulating barrier.
  • the input circuit 21 has a terminal 103 as a power supply and a signal input, and is composed of a modulation circuit 104, a drive circuit 105, and a protection circuit 106.
  • the input analog signal is converted and modulated, and a PWM (Puis Width Modulation) signal is input.
  • PWM Pulis Width Modulation
  • the output circuit 22 includes a protection circuit 107, a detection circuit 108, and a demodulation circuit 109. Power is supplied from the terminal 110, a signal coming through the insulation barrier 9 is detected by the detection circuit 108, and integration is performed from the detection signal.
  • the PWM signal is reproduced by the circuit 135 and the comparison circuit 137, and an analog signal corresponding to the input signal is reproduced from the PWM signal. It also has a function to extract timing signals from detected signals and output these signals.
  • the input terminal 103 includes a power supply terminal VDD 1 and VDD 2, a ground terminal VSS 1, a differential input of ten and one as a signal input, and a clock input terminal for modulation timing.
  • the modulation circuit 104 includes a comparison circuit 111 and a carrier generation circuit 112.
  • the driving circuit 105 is an inverter driver including PMOS transistors 113 and 114 and NMOS transistors 117 and 118.
  • the protection circuit 106 includes diodes 121, 122, 123 and 124 and resistors 12 and 130 and prevents the circuit from being destroyed due to a surge voltage entering from the output circuit 22 side.
  • the protection circuit 107 on the output circuit 22 side is a resistor 1 31 , 132, and diodes 125, 126, 127, 128 to protect the gate of the transistor of the detection circuit 108.
  • PMOS 115, 116 and NMOS 119, 120 are inverter-type detection circuits with feedback resistors 133 and 134.
  • the output of the detection circuit 108 is connected to the integration circuit 135.
  • the integration circuit 135 reproduces a PWM waveform from the inverter output signal.
  • 136 is a circuit for reproducing the timing of the carrier wave
  • 137 is a comparison circuit.
  • Terminal 110 on the output circuit side supplies power from the power supply terminals VDD3, VDD4 and VSS2, and outputs the complementary signal output of the processing result and the timing clock.
  • the features of this configuration are (1) the use of two insulating barriers 9-1, 9-12, (2) an external clock input, and (3) a regenerative clock output. Although it is not shown because it is a normal input / output protection circuit, among the terminals 103 in this circuit block diagram, the signal input terminals 10 and the clock input, when used alone as an insulating bra, Provide an input protection circuit. In the description of the circuit configuration, the combination of the PMOS and the NMOS is shown. However, depending on the purpose, a bipolar process or a mixed process may be used. Also, when the purpose is to use a single insulating bra, the clock may be generated internally.
  • FIG. 4 is an operation timing chart of the insulating bra of FIG. 3, and a signal transmission method is a PWM (pulse width modulation) method.
  • the frequency axis of the input signal that is the waveform to be transmitted (here, about 3.4 kHz at maximum) is sufficiently higher (here, 1.2288 MHz: 256 times or more).
  • the magnitude of the input signal is converted to each pulse width t and transmitted.
  • T / T 0.5 when input signal is 0 volts, that is, 50% duty, input signal is large Duty conversion is performed so that the pulse width becomes larger as the value becomes larger and the pulse width becomes smaller as the input signal becomes more negative.
  • the input signal is a differential input with the input signal + and the input signal-to reduce the influence of common mode noise, other input methods may be used depending on the purpose.
  • Fig. 4 schematically shows a case where a sine wave is applied to the +-input terminal.
  • a rectangular clock input from outside the insulating bra is converted into a sawtooth waveform by the carrier generation circuit 112 to obtain a carrier.
  • the modulation circuit 104 is a comparison circuit 111, and receives these input signals and outputs outputs P WM + and P WM ⁇ in which the duty of the pulse is changed.
  • the drive circuit 105 inputs the PWM + and PWM- waveforms to the drive circuit 105, and supplies it to one terminal of the insulation barriers 9-1 and 9-2 through the protection circuit 106.
  • the capacitor value of the insulation barriers 9-1 and 9-2 is about lpF.
  • the protection circuit 106 Since the protection circuit 106 has a constant that is effective for a high-voltage surge waveform of about several tens of ns or less, it hardly affects the drive waveform.
  • the other electrodes of the insulation barriers 9-1 and 9-2 are input to the detection circuit 108 through the protection circuit 107.
  • the detection circuit 108 is an inverter and an integration circuit 135. Since the inverter output has a differential waveform like the detection signal + and 1, and is significantly attenuated due to the stray capacity, it is once amplified by the inverter and input to the integration circuit 135.
  • the integration circuit 135 is an integrator having two inputs of + and 1, and outputs a reproduced PWM signal + and 1 as shown in the figure by using a differential waveform as an input signal.
  • the timing recovery circuit 136 is a PLL circuit that extracts a timing signal component from the reproduced PWM signal. Create a sawtooth waveform using the timing waveform and reproduce it. If sample hold is performed at the timing of the PWM signal, demodulated waveforms such as the output signal + and 1 can be reproduced.
  • a PWM realizing method may be another method.
  • the modulation waveform may be a triangular wave. When a triangular wave is used, the center timing of the modulation waveform becomes constant, so that, for example, a high-precision timing reproduction method such as a PLL can be employed in a demodulation circuit.
  • a set-reset type flip-flop may be arranged instead of the integrating circuit.
  • the rising timing of the differential waveform which is the output of the inverter, is the PWM timing information itself, and can be directly used as the flip-flop control signal by appropriately selecting the characteristics of the load resistance inverter.
  • the output of the flip-flop is the PWM waveform itself.
  • the feature of this operation timing is that three control signal transmissions of a transmission signal, a reception signal, and a line connection control signal are performed in parallel. For this reason, in a line interface using an insulation bra, signal crosstalk becomes noise and degrades the S / N ratio. Thus, in this embodiment, the degradation is suppressed by synchronizing the operation timing of the DSP, the modem processing timing, and the timing of the insulating bra. This will be described with reference to FIG.
  • FIG. 5 (a) and 5 (b) show the timing relationship between the modem signal processing and the operation of the insulating bra.
  • the feature of the circuit configuration of this embodiment is that the operation timing of the line interface circuit is supplied from the modem. That is, the circuit operation inside the IC is synchronized with this clock.
  • FIG. 5 (a) shows the modem signal processing part, and the timing chart is schematic, but has the relationship shown on the right side of the chart. That is, in the modem signal processing part, the DSP is operated at 39.316.16 MHz, and 1.2288 MHz is supplied to the AFE to be used as the DA conversion timing MCLKS and the AD conversion timing MCLKR.
  • (B) relates to the clock timing of the line interface.
  • the modem supplies the clock signal DSPCLK supplied from the DSP as the NCLK S to the transmission signal path 61 and the control signal path 63 of the insulating power cable 6 and the modem. Synchronize with the operation timing. Since the reception signal path NCL KR only needs to operate when the control signal is on, it has a gated waveform as shown in the figure.
  • the timing CLK 2 of the R det path oscillates locally in the circuit on the line side, but is stopped by the control signal OFHK when exchanging signals between modems.
  • FIG. 6 shows the PWM modulation timing when the sawtooth waveform is used as the carrier.
  • a PWM waveform is obtained by integrating a clock signal to create a sawtooth waveform that becomes a carrier waveform and comparing it with the transmission signal.
  • the received signal, the transmitted signal, and the OFHK control signal are shown.
  • the received signal has a small amplitude due to the effects of transmission loss on the line, as shown by RXA +,-in Fig. 1, and is approximately-20 to -45 dBm.
  • the transmission signal has a large amplitude since it is transmitted from the user, and is usually about 16 to 15 dBm.
  • the control signal is a 5V logic level and the maximum value.
  • the transmission / reception signal is AD or DA converted at a predetermined timing, but the clock received from the modem is By synchronizing with this, the effect can be minimized even if the PWM section is sampled at every cycle T (the effect of beat noise is asynchronous).
  • Synchronizing the PWM carrier clock timing has the effect that at least the overlap between the logic level timing and the analog signal timing can be separated as shown in the figure.
  • the timing disturbance is limited to the vicinity of the logic level, so that the effect of the crosstalk is minimized.
  • Fig. 6 (b) shows the PWM modulation timing when applied to a triangular waveform carrier.
  • the carrier wave has a triangular waveform, so that PWM modulation timing appears on both sides of the triangular wave.
  • the same effect can be obtained by using this embodiment.
  • the clock for the insulation bras 105 that transmits the incoming detection signal R det is generated by the oscillator OSC 112 that is arranged on the line side, so the timing does not match the operation of the other insulation plastic plugs. But OFHK system Oscillation is inhibited when a control signal is input, and this action stops the operation of the oscillation circuit before starting modem communication, thereby suppressing the effects of crosstalk. .
  • FIG. 7 is a diagram of the layout of the line interface IC.
  • reference numeral 2 denotes a line interface IC
  • reference numerals 206--1, 206--2, and 206--3 denote insulation bands
  • a line-side terminal area 201 and a line-side circuit respectively. It surrounds the region 202, the terminal-side circuit region 204, and the terminal region 205.
  • Reference numeral 203 denotes an insulating bra array area in which the four insulating plugs shown in FIG.
  • the features of this layout are as follows: (1) The use of four insulating power barriers using a capacitive insulating barrier; and (2) The circuit on the line side and the circuit on the terminal side should be separated with the insulating coupler interposed therebetween. (3) Each of the line-side circuit and the terminal-side circuit is surrounded by an insulating band. Insulation zone means that the circuits on the line side and the terminal side are isolated from each other, and each area can be freely designed without being aware of the withstand voltage between the primary and secondary circuits. At the same time, there is an IJ point that simplifies the evaluation and management of insulation capacity.
  • FIG. 8 (a) is a plan view
  • FIG. 8 (b) is a cross-sectional view, each of which schematically shows only a drive circuit and a detection circuit.
  • reference numeral 203 denotes an insulating coupler area
  • 206 denotes an insulating band
  • 207 denotes an insulating barrier
  • 211 denotes an input circuit area
  • 211 denotes an output circuit area.
  • the insulating band 206 forms many patterns from 2066-1 to 206-6. Note that the sign of the insulating barrier 207 part is complicated. The same is true for some of them.
  • the input circuit region 211 and the output circuit region 212 further include PMOS regions 213, 214, 215, 216 and NMOS regions 217, 218.
  • the input terminals of the input circuit are the two inverter input terminals IN 1 and IN 2 of the drive circuit.
  • the output terminals of the output circuit are the two inverter output terminals OUT1 and OUT2 of the detection circuit.
  • VDD1 to VDD4 are separate power pins
  • VSS1 and VSS2 are separate ground pins.
  • the features of the plan view (a) are that (1) the circuit regions are separated by an insulating band, and (2) the insulating band is formed as a comb-teeth pattern as an insulating barrier to increase the facing area. (3)
  • the four capacitors are connected in series in the horizontal direction to form two sets of insulating barriers. These are driven by complementary PWM digital waveforms as described above. There is little crosstalk between the two sets of insulation barriers, but if the application is problematic, the space between them, ie, the long space in the horizontal direction, the power supply pattern VDD, VSS It is effective to prepare them and place them between insulating barriers to loosen the coupling. The same arrangement is effective when a plurality of insulating bras are used.
  • the PMOS region and the NMOS region are separated by an insulating band. With this separation, even if an unexpected surge voltage is applied to the circuit, short-circuiting and penetration between power supplies due to conduction of the parasitic transistor, that is, latch-up phenomenon does not occur in principle.
  • 231 is a substrate
  • 232 is an insulating layer
  • 233 is a semiconductor layer
  • 234 is a protective layer
  • a semiconductor region is formed by many insulating bands 206.
  • 21 1, insulation barrier 20 7, output circuit area 21 2 are arranged.
  • a silicon wafer (SOI substrate) in which SiO 2 of about 2 ⁇ m thickness is used as an insulating layer as an inner layer is prepared, and a thin film using a photomask is formed thereon. Each region is created using a film process.
  • 2 0 6 - insulating band 1 from 2 0 6 6 is about 1 S i 0 2 layers of 5 mu m width..
  • each region such as an input / output circuit region and an insulating barrier region, is formed on a silicon wafer having an insulating layer as an inner layer by dividing the region by an insulating band 206. It's like 3 4 is piled up. Silicon wafers consist of a single-crystal silicon substrate 2 3 1, a Si 2 -layer, or a multi-layer insulation layer 2 32 with a layer of oxidized polysilicon, and a single-crystal silicon semiconductor layer. Are stacked. In this embodiment, the bonding is performed by a method in which the surface of the silicon oxide film on the polysilicon surface is mirror-polished and superposed, and then bonded by heat treatment at a specific temperature.
  • Insulating strip 2 0 6 is a is Insulator a S i 0 2 layers.
  • Protective layer 2 3 4 is an insulating material such as S I_ ⁇ 2, HLD or S i N includes a wiring layer of polysilicon Ya aluminum in this layer.
  • the capacitor is composed of three electrode regions 2 36, 2 37, 2 38 and an insulating band 206. In this way, even in the case of the trenching method in which the width of the insulating band 206 is limited as compared with the thickness of the insulating layer 232, the withstand voltage can be ensured by connecting the capacitors in series.
  • the input circuit area 2 1 1 and the output circuit area 2 1 2 are 2 35 and 2 39 in cross section, and these are surrounded by two insulating bands, and a high withstand voltage can be obtained. It has a structure.
  • the integrated circuit can be directly adhered to a frame during package mounting, and has an advantage of good heat dissipation.
  • FIG. 9 is a plan view
  • (b) and (c) are ⁇ _ ⁇ ′ sectional views in the plan view (a).
  • 207 is an insulating barrier
  • 206-1, 206-2, and 206-13 are insulating bands made of Si 1.52 with a width of about 1.5 microns
  • 241, 242, and 243 are insulating bands.
  • the electrode regions 244 and 245 surrounded by are terminals which are holes formed in the protective layer above the electrode regions 241 and 242.
  • 231 is a Si substrate about 400 microns thick
  • 232 is an insulating layer about 2 microns thick
  • 233 is a semiconductor layer about 15 microns thick
  • 234 is about 5 microns thick
  • the other symbols are the same as in (a).
  • each region is formed on a silicon wafer having an insulating layer as an inner layer using a thin film process using a photomask.
  • the insulating band is a two- layered Si layer and is an insulator.
  • the insulating band 206 is formed by once digging a trench (trench) and filling it with SiO 2 , or by changing the semiconductor layer to an insulator by irradiating oxygen ions from the upper surface.
  • the capacitor consists of three electrode regions 241, 242, 243 and two insulating zones 206-1, 206-3.
  • the insulating band 206 is patterned so that the band is folded, and the length of contact between the electrodes 241, 242 and 243 is increased, so that a capacitance value can be obtained efficiently with a small semiconductor area.
  • an insulation performance of about 2 pF is obtained for a square of about 160 microns and a withstand voltage of about 750 V per insulation band in a DC withstand voltage test.
  • a high voltage is applied between terminals 244 and 245, but when viewed from outside insulating barrier 207, electrode regions 241, 2 It is a pattern in which 42 is double surrounded by an insulating band.
  • arc-shaped pattern (radius of 2 to 5 microns) is used as much as possible for the folded portion and the corner portion so as not to generate an acute angle pattern.
  • the insulating band 206-6-2 is necessary to insulate and separate from other circuit parts.
  • Fig. 9 (c) is a structural drawing in the case where the thickness per insulating layer cannot be increased. By using two insulating layers, an effective withstand voltage can be obtained.
  • adjusting the thickness of each layer with an insulating layer has the effect of dispersing stress and reducing warpage.
  • FIG. 10 shows another layout concept of the line interface IC.
  • two insulating bras are arranged in the direction perpendicular to each other.
  • a test voltage of 1500 V dc is applied between the line-side circuit and the terminal-side circuit, but each circuit area is placed on an SOI substrate and surrounded by an insulating band.
  • a fairly flexible layout is possible. However, it is limited by the arrangement and size of the wiring and terminals between the regions. Note that this layout has a feature that efficient area arrangement can be performed when there is an imbalance in the circuit area and the number of terminals.
  • FIG. 11 is a block diagram showing various transmission systems from (a) to (f).
  • the insulating barrier is the capacitor of the present invention.
  • the insulated coupler of the present invention uses two insulating barriers and is driven with a complementary waveform so that a signal can be accurately transmitted even when the receiver side is floating.
  • the input circuit receives power from the power supply terminal VDD 1 and the ground terminal VSS 1 and drives the signal received from the input terminal to one terminal of the insulation barrier. And output it.
  • the output circuit receives power from the power supply terminal VDD 2 and the ground terminal VSS 2, detects the waveform appearing at the terminal on the opposite side of the insulation barrier, converts it to an output signal, and outputs it.
  • the converted waveform can use various methods such as PWM (pulse duty conversion) or FM (voltage-frequency conversion), which digitizes only in the amplitude direction, or a digital transmission method in which the time axis is also digitized.
  • FIG. 11 (b) shows the case of the PWM transmission method.
  • the input circuit samples the input analog signal at a constant period T that is several tens of times or more the signal bandwidth, and converts the amplitude into a duty in the time axis direction (0 V input is 50% duty).
  • the transmission and output circuit detects this, converts the duty to an amplitude value again, reproduces the input waveform, and outputs an analog signal.
  • analog processing of the duty a high resolution can be obtained in principle.
  • a digital signal may be transmitted.
  • (c) shows the case of digital transmission according to the present invention.
  • the transmission waveform is subjected to code conversion such as Munchister code so that the same level does not follow the transmission waveform, and then the insulation barrier is driven.
  • the output circuit detects this and performs inverse conversion to perform the original conversion. Play digital signals.
  • code conversion and inverse conversion are performed in synchronization with the transfer frequency of the input digital signal.
  • This method has a feature that it is hardly affected by noise because there is little conversion in the amplitude direction.
  • (d) shows the case where the AD conversion input is performed through the insulation barrier.
  • the analog input signal is AD-converted, and the same sign conversion as in (c) is performed before driving the insulation barrier.
  • the output circuit detects this and outputs a digital signal after performing reverse code conversion.
  • (e) shows the case where the DA conversion output is performed through the insulation barrier.
  • the input circuit converts the digital input signal to the same sign conversion as (c). And then drive the insulation barrier.
  • the output circuit detects this, performs reverse code conversion, and then performs DA conversion to output an analog signal.
  • (f) shows a case in which (d) and (e) are combined to perform analog signal input / output using AD conversion and DA conversion.
  • the signal transmission methods (d) to (f) are suitable for voice signal processing analog front-ends such as modems and line interfaces by connecting digital signals to DSPs.
  • the invention allows these schemes to be integrated into a monolithic IC.
  • the above-described capacitive insulation barrier is a circuit for coupling between two circuits, but has a large stray capacity between the substrate and the input circuit, the output circuit, and the insulation barrier. There is a big difference from creating them separately and combining them. For this reason, the transmission efficiency at the insulation barrier is a fraction of poor.
  • the amplifier circuit is arranged at the first stage of the output circuit, and the detection processing and the demodulation processing are performed later.
  • FIG. 12 is a circuit block diagram of a modem device according to another embodiment of the present invention.
  • reference numeral 251 denotes a line interface IC of this embodiment
  • reference numeral 252 denotes a terminal-side circuit
  • reference numeral 253 denotes an insulating power plug
  • reference numeral 254 denotes a line-side circuit
  • reference numeral 255 denotes a high withstand voltage circuit.
  • the terminal-side circuit 252 includes a DSP interface 256, a modem data output interface SOR261, a modem data compression circuit 262, a transmission-side multiplexer 263, a general-purpose output register master register GORM262, an error correction circuit 265, and a reception-side multiplexer.
  • the transmission path consists of a transmission path insulation bra 6-1 and a reception path insulation bra 6-2.
  • the line side circuit 254 is composed of a transmission path multiplexer 271, transmission modem data.
  • Expansion circuit 272 includes a DC closing circuit 282 and a call signal detecting circuit 284.
  • the feature of this circuit configuration is that, first, the AD converter and the DA converter are arranged on the line side, and the signal passing through the insulation bra is converted into digital data. For this reason, as described later, the noise resistance when passing through the insulating barrier is remarkably improved. Second, the AD conversion signal and the DA conversion signal are once compressed and passed through an insulation bra, and the control signal is error-correction-encoded into the vacant portion, and the insulation bra 6 is connected to the 6-1. And 6-2. Mounting an insulating barrier on a semiconductor substrate requires a large area, so the number of insulating bras can be reduced even if the area of additional circuits such as data compression and expansion and error correction is increased. This is advantageous in reducing the area.
  • the function is almost the same as that of Fig. 1.
  • the internal circuit of the high voltage circuit 255, the 2-wire 4-wire conversion circuit 281, and the SW control circuit 28 3 is exactly the same function.
  • the timing is adjusted by inputting both the recovered clock of the isolated coupler 5-2 and the clock from the DSP to the multiplexer 2666. The timing can be adjusted by arranging a 1-bit or 2-bit buffer memory.
  • the general-purpose I / O registers GOR and GI scale sequentially transfer the contents of the master register to the slave register. It is that you are.
  • compression and error correction and multiplexers may be omitted when noise is low and errors are difficult when the technology advances and the insulation power becomes smaller.
  • Fig. 13 shows the case where a sawtooth waveform is used for the carrier, and (b) shows the case where the triangular wave is used for the carrier.
  • the transmission signal and the reception signal are analog signals.
  • the performance that can withstand transmission errors in the insulation barrier is the best. it can.
  • FIG. 14 shows a case where the line interface IC has a two-chip configuration.
  • reference numeral 2991 denotes a line interface chip
  • reference numeral 292 denotes a terminal interface chip
  • the terminal interface chip 292 has a terminal area 296, a line-side low-voltage circuit area 297, an insulating plastic area 298, and a terminal-side circuit area 299.
  • the terminal area 300 was arranged.
  • a DC closing circuit and a ringing (RING) detection circuit are arranged in the circuit-side high-withstand-voltage circuit area 294.
  • a 2-wire / 4-wire conversion circuit In the line-side low-voltage circuit area 297 of the terminal interface chip 292, a 2-wire / 4-wire conversion circuit, an OFHK switch (SW) control circuit, and a transmission circuit are arranged.
  • an efficient process can be selected by separating the process conditions of the line interface chip 291, which requires a high-voltage circuit element, from the insulation barrier and the circuit of the low-voltage circuit element.
  • reducing the size of one IC chip reduces the effect of overall yield in the process, and has the effect of increasing the number of IC chips obtained per wafer.
  • the line interface chip requires individual components. It may be used as a discrete circuit. By doing so, the terminal interface chip has only the logic signal and the signal at the signal level of the modem, and there is no portion directly connected to the line. It can be applied to the internal circuit of the device, and the effect of expanding the application range is created.
  • FIG. 15 is a structural view of another embodiment of the insulating barrier, wherein (a) is a single insulation, (b) is a double insulation, and (c) is a double insulation another modified embodiment. It is a plan view.
  • 207 is an insulating barrier
  • 206-1, 206-2, and 206-3 are insulating bands
  • 241, 242 are electrode regions surrounded by an insulating band 206
  • 244 and 245 are electrode regions 241 and 242.
  • the terminals, 301-1 and 301-2 which are holes formed in the upper protective layer, are closed.
  • FIGS. 15 (a) and 15 (b) show an embodiment of a pattern having no acute angle in the insulating band, like the embodiment of FIG.
  • the characteristic of the pattern in Fig. 15 (a) is that the electrode regions 241 and 242 having the terminals 244 and 245 are formed by one stroke of the insulating bands 206-1 and 206-6-2.
  • the portion where the insulating bands are connected in a T-shape can be eliminated, which not only improves the efficiency of filling the trench by the trench method, but also has the effect of reducing the concentration of the electric field.
  • Fig. 15 (b) The feature of this pattern is that the electrodes 241 and 242 having the terminals 244 and 245 are formed by one stroke of the insulating bands 206-3 and 206-4, respectively.
  • Fig. 15 (c) is a modified example of the embodiment in Fig. 15 (a) and Fig. 9. If two T-shaped parts are allowed, they are surrounded by an insulating band 206-3. This has the effect of realizing a good area efficiency and an insulating barrier.
  • the method (b) can be expanded efficiently even when the number of series is small.
  • FIG. 16 is a structural view of one embodiment of the insulating power bra of the present invention.
  • the insulating bra 203 in FIG. 16 includes a terminal for an input circuit in the insulating coupler portion of FIG.
  • An area 201 and a terminal area 205 for an output circuit are provided and each terminal is arranged, and has a size of about 2 mm square.
  • a very small analog PWM monolithic insulation bra can be made. This is, of course, mounted in a package in a later process and used, but since it is monolithic, it is extremely small, so it is mounted inside an applied device such as a measuring instrument probe or various medical sensors. This can contribute to the miniaturization and higher performance of these devices.
  • FIG. 17 is a layout conceptual diagram in a case where the two insulating brass shown in FIG. 16 are mounted on one chip.
  • reference numeral 203 denotes a one-chip insulated coupler incorporating two couplers
  • reference numerals 203-3 and 203-3-2 denote a built-in insulating bra 1 and a built-in insulating bra 2, respectively. They are surrounded by insulating bands 206-6-1 and 206-6-2, respectively.
  • the features of this layout are (1) that each insulating bra is surrounded by insulating bands 62-1 and 62-2, and (2) that insulating barriers where the electric field is concentrated are arranged.
  • a withstand voltage can be secured between any two inputs and any two outputs, and each circuit element can be freely arranged while maintaining the withstand voltage. effective. Also, with this structure, unnecessary electric circuit coupling can be minimized, and the range of application can be expanded.
  • FIG. 18 shows still another embodiment of the insulating bra according to the present invention, in which an input circuit and an output circuit each insulated by an insulating band are integrated into a circuit. It shows the structure of an integrated circuit and an insulating bra when a lamic capacitor is combined with an insulating barrier to form an insulating coupler.
  • (a) is an outline of a chip layout
  • (b) is a cross-sectional view of mounting the IC and a ceramic capacitor on a circuit board.
  • 303 is an insulating plastic IC
  • 206-1 and 206-2 are insulating bands surrounding the input circuit area and the output circuit area, respectively.
  • 4 is an external insulation barrier
  • terminal areas 201 and 205 are connection terminals to the external insulation barrier 304, respectively.
  • reference numeral 303 denotes an IC for insulating power
  • reference numerals 304 and 360 denote solder.
  • 307 is a circuit board, which has copper foil 308, 309, 310, 311 circuit connection patterns on both sides, and through holes 312, 313 if necessary. It is provided.
  • the circuit board 307 may have a multilayered copper foil as needed, as long as the insulating property is not impaired.
  • the insulating barrier 304 is a chip capacitor, and is surface-mounted on a circuit board with solder 316 and 317.
  • the insulation barrier which occupies a relatively large area in the semiconductor integrated circuit, is used as a separate chip, but the shape and dimensions of the insulation bra become large, but the price is realistic, and the capacitor value of the insulation barrier is reduced.
  • a configuration method is also possible in which the operation timing frequency can be freely selected by positively increasing it. That is, by increasing the capacitor value, the low-frequency characteristics are improved, so that the waveform transmission becomes easier.
  • a small power transmission can be performed by a charge pump circuit or the like.
  • FIG. 19 is a structural diagram showing the concept of an embodiment in which the monolithic line interface of the present invention is applied to a card modem device.
  • FIG. 19 (a) is an embodiment of the present invention
  • FIG. 19 (b) is It is a conventional card modem.
  • 400 is the entire card modem of this embodiment
  • 401 is the circuit board of this embodiment
  • 402 is the line interface IC of this embodiment
  • 403 is eight? £, 404 for 03, 405 for other ICs, 406 for line-side connectors, 407 for PC-side connectors, 408 for varistors, 409 for high-voltage capacitors, 410 for capacitors and 41
  • Reference numeral 416 denotes other chip components such as resistors and capacitors.
  • 450 is the entire conventional card modem
  • 451 is the conventional circuit board
  • 452 is the line transformer which is the conventional line interface
  • 453 is the AFE
  • 454 is the DSP
  • 455 is other IC
  • 456 is line side connector
  • 457 is PC side connector
  • 458 is varistor
  • 459 is high withstand voltage capacitor
  • 460 is capacitor
  • 461 to 466 is other resistor and capacitor Chip components.
  • This diagram schematically shows the cross section of the card modem.
  • the conventional card modem 450 penetrates the circuit board 451 and has a line transformer 452 in the penetrated part.
  • the line interface IC 402 can be implemented almost in the same manner as the other ICs indicated by 402 to 405. Therefore, there is no need to penetrate the circuit board 401, which is economical. In addition, it may be economical to use no special transformer. Furthermore, since the transformer can be omitted, there is a possibility of further miniaturization.
  • FIG. 20 is a circuit block diagram of one embodiment when the monolithic digital insulating bra of the present invention is applied to an AFE.
  • AF of this embodiment E is for audio band signal processing, analog and digital conversion is oversampled (2MHz) AD and DA conversion, decimator, interpolator temporarily reduces to 32 ksps, and low frequency filter processing by internal DSP And finally input and output digital data at a speed of 8 ksps.
  • reference numeral 500 denotes a monolithic analog front end (I-AFE) incorporating digitally isolated couplers 501 to 506, and I-AFE 500 is an AFE original multiplexer (MUX) 511 and pad amplifier (PDA).
  • I-AFE monolithic analog front end
  • MUX AFE original multiplexer
  • PDA pad amplifier
  • Pre-filter (PF 1) 5 13 3 Oversampled analog-to-digital converter ADC 514, Decimator filter (DCM) 51 5, AD conversion output buffer (ADCR) 516, Built-in (in-) Analog input line consisting of DSP 517, receive output buffer (RXDR) 518, transmit buffer (TXDR) 521, DA conversion input buffer (DACR) 522, interpolator (INT) 523, oversample 'digital' Analog output line consisting of two analog converters D AC 514, post filter (PF 2) 525, and attenuator (ATT) 526, and data input / output transfer control 531, 533 and analog input for in-DS P 517 Output terminal 2 It has a configuration obtained by adding a control circuit to four-wire conversion circuit 533.
  • the AFE 500 is reset and powered down by the control circuit (CONT) 541.
  • the reset signal is transmitted to the circuit on the left side (hereinafter, analog input / output side) through the digital isolation coupler 506, and is combined with the reset signal accompanying the power on / off of the analog input / output side by the reset circuit 542, and the analog input / output side Used as a reset signal for the circuit.
  • An external device uses the control registers (CONTR) 551 and (STATUS) 554 to finely control the I-AFE 500.
  • CONTR551 (STATUS ') 553 ) Is copied to the control register (CONTR ') 551, STATUS 554 of the analog (digital) input / output circuit through the digital isolation couplers 504, 503, and is used to control SW1 to SW3 of the analog input / output circuit and other circuits.
  • GPO general output port
  • the reference voltage generation circuit 563 is a circuit for applying a reference voltage for operating the analog input / output circuit with a single power supply, and generates the reference voltage VREF: (V DDI-VSS 1) 2.
  • the 2-wire 4-wire conversion circuit 533 is a circuit that converts between 2-wire public line and internal 4-wire transmission / reception when the I-AFE500 is used as a modem device. Has an amplifier function.
  • the analog input signal goes through the 2-wire 4-wire conversion circuit 533 or is directly input from the I N + and I N- terminals, but the MUX 511 is switched in advance by the signal SWl according to either of them.
  • the PDA512 can switch the gain of O dB and 6 dB to the signal SW2.
  • the PF 1513 is an analog filter for removing unnecessary frequency band signals before AD conversion.
  • the PF 1513 is a second-order low-pass filter having a cut-off frequency of 48 kHz.
  • the ADC514 is a second-order modulator that operates at 2Msps and outputs 2-bit AD conversion results every 0.5 / s. This AD conversion output is transmitted to the DCM 515 and thinned out to 32 ksps.
  • the output of DF1 515 is 16 bitZw Since the speed is as low as 32 ksps, this is serially converted to 2 Msps, and transmitted to the in-DSP 517 via the insulating bra 502 along with the timing signal via the ADC 516 of the digital input / output circuit.
  • the in-DSP517 performs flatness correction and LPF processing of 4 kHz or less on this decimator output by IIR and FIR digital signal processing.
  • the processing result is transmitted to the ex-DSP 236 serially through the reception buffer 518 as 16-bit Zw data every 8 ksps.
  • the analog output line receives the data to be output from the ex-DSP 536 every 8 ksps from the transmit buffer TXDR21 1 and the in-DSP 517 performs the same filtering as the analog input.
  • the result is passed to the interpolation filter (INT) 523 at a speed of 32 ksps while interpolating the 16-bit / w data via the DA output buffer (DACR) 522. Via force bra 501.
  • the INT 523 further performs an interpolation process, passes the data to the DAC 514 at a speed of 2 Mps as 6-bit / w data, and outputs an analog value.
  • the aliasing component remaining after processing by DSP 517 and INT 523 is removed by post filter PF2552, and output via ATT226, which can switch between O dB, 16 dB, and 10 dB.
  • the operation timing of these analog output lines uses the timing of the analog input line.
  • the timing of these processes is basically the same as the 2 MHz timing, the same timing of the ⁇ modulator / demodulator, the interpolator and decimator processing timing for input / output at 2 Msps and 32 ksps, and 32 ksps and 8 ksps. It is time to assign the DSP processing timing for input and output in an orderly manner.
  • the analog input / output side circuit and the digital input / output side circuit are separated in the insulating couplers 201 to 205, but it is essential to operate them in synchronization. This is where the importance of isolator settings dedicated to switching is placed.
  • ex-DSP 5 36 6 I — AFE 500 is an analog signal input / output circuit, but its sample timing is important. Therefore, most modems use the most discrimination judgment at the time of demodulation. Adjust the ADC 514 sample timing to get the best timing. For this purpose, ex-DSP 536 to I-AFE 500 are notified of the timing advance or delay by the MC LK. That is, if you want to advance the timing, add A f, and if you want to delay it, add 1 A f to notify I — AFE 500. This process is performed every several 10 Oms or several 10 Oms.
  • I-AF E500 operates at arbitrary timing, it will not match the timing required by ex-DSP 536, so data will be over / shortage, processing timing will be broken, and large noise will be generated. .
  • PLL is placed inside I-AFE 500 to synchronize the internal timing.
  • the timing accuracy demands allow, there is a method of complementing by using the timing error of the automatic equalization means in the modem. In this case, the circuit timing adjustment is not performed.
  • the data transfer between the decimator, the interpolator and the in-DSP is performed by serial high-speed transfer, which has the effect of reducing the number of insulating brushes. Since the modem includes multiple standards, there may be cases where multiple sample timings are required.To deal with this, the division ratio of the PLL 561 and the timing circuit 562 can be controlled by the CONTR 562. I have to. Further, by applying the above-described error correction means to the insulating brass for transmitting these control signals, the operation can be stabilized.
  • the configuration in which the digital filter performs signal processing by the internal DSP 517 is shown. However, the processing of the internal DSP is a dedicated processing for AD conversion and DA conversion. However, it may be formed with appropriate dedicated logic.
  • FIG. 21 shows the concept of the layout on the integrated circuit of the circuit of FIG. 20.
  • reference numeral 600 denotes the entire AFE integrated circuit, which is formed on an SOI substrate.
  • the insulation band 601 indicates the analog input / output circuit area
  • the insulation band 602 indicates the insulation force puller (indicated by Isolators 501 to 506)
  • the insulation band 603 indicates the digital input / output circuit area.
  • the insulating band 604 is a means for insulating between the other chip area on the wafer and the area, and the insulating band 604 is a means for preventing circuit coupling with the substrate through the scribe end face. is there.
  • the names given to the more subdivided areas in each area correspond to those in FIG.
  • each circuit area is further surrounded by trenches, and the analog input / output side circuit area 601, insulating power area 602, digital input / output side circuit area 603, This means that double trenches are used to provide insulation between the regions, and (2) the whole is surrounded by trenches 604 to provide insulation between chips.
  • the trench 604 is a multi-trench.
  • each circuit block in the circuit regions 601 to 603 is surrounded by trenches to provide insulation and element isolation between circuits.However, these are further formed into multiple trenches and grounding between the trenches. A noise shield due to mutual interference can be formed.
  • the multiplicity of the trench in the circuit area is one step higher than the multiplicity of the trench in the high breakdown voltage capacitor section, the insulation coordination is performed so that the destruction mode is limited to the capacitor section. Is considered. This has the effect that a system can be constructed with limited damage even when a high voltage higher than the standard is applied.
  • FIG. 22 is a circuit diagram of an embodiment of a DSP modem to which the I-AFE of FIG. 20 is applied.
  • 500 is an I-AFE
  • 700 is an eX-DSP.
  • the terminals to be connected are connected to the TIP and RING, with resistors 701 and 702, capacitors 703 and 704, and surge protection.
  • protection circuit composed of element 705.
  • Reference numerals 706 and 707 denote SWs formed by NMOS transistors, which are connected to light receiving elements (for example, solar cells) 708.
  • the light receiving element 708 receives the light of the light emitting diode 709, turns on and off 706 and 707, and supplies power supplied through TIP and RNG to the circuit on the right side of this switch.
  • the light emission of the light emitting diode 709 is controlled by a switch circuit including a transistor 710 and resistors 71 1 and 71 2.
  • the control signal of this switch is POWER @N.
  • the diodes 713, 714, 715, and 716 constitute a bridge, and have a function of making the direction of current constant regardless of the direction of DC voltage applied to TIP and RING.
  • the circuit consisting of 717, 718, capacitance 719, transistors 720, 721, resistor 722, and NMOS transistor 723 is a DC closed circuit.
  • the NMOS transistor When the control output terminal GPO of the I-AFE 500 goes high, the NMOS transistor is turned off. When turned on, the Darlington transistor circuits 720 and 721 operate according to the bias of the resistors 717 and 718, and a loop (closed) current flows in a state balanced with the feedback resistor 722.
  • the circuit consisting of the resistors 724 and 18 V Zener diode 725 is a protection circuit that prevents excessive voltage application to the three-terminal regulator 726 and I-AFE 500.
  • the capacitance 727 is a smoothing capacitor, and the capacitances 728 and 740 are the I-AFE output circuit and signal coupling capacitor.
  • a modem When transmitting with a modem, first generate a POWER ON signal Turn on the NMOS switches 706 and 707 to connect the three-terminal regulator 726 to the line to supply current to the AFE. Then, set the GPO to high level from TXD through CONTR and turn on the NMOS switch 723 to turn on the loop current. To inform the central office that the modem has been connected to the line. Next, the modem sends a dial signal to the I-AFE 500 through the capacity 728, 440, and waits for the exchange to connect the other modem. Since the connected modems generate normal modem signals, they communicate with each other through the AFE.
  • Capacitance 729, Zener diodes 730, 731 are sensitivity adjustment circuits that do not respond to incoming signals below a certain voltage.
  • Resistor 732 is the current limiting resistor for diode 733 or light emitting diode 734.
  • Phototransistor 735 is resistor 736.
  • the POWER ON pin turns on the NMOS switches 706, 707 and 723 to turn on the power by supplying a loop current, and the modems 728 and 740 Returns a response signal. Transmission and reception of modem signals after this are almost the same as at the time of transmission.
  • the first feature is that all the analog input / output circuits, including the circuits of the individual components on the left side, are insulated from the digital input / output circuits on the right side of the I-AFE insulating camera array. Conventionally, the insulation is provided on the right side by using an insulating transformer. The transformer can be eliminated by the I-AFE of this embodiment, and a compact modem device can be constructed.
  • the second characteristic is that power is supplied from the station to the analog input / output side circuit of the I-AFE to supply power. Supply from the side This eliminates the need and contributes to a reduction in overall power consumption.
  • the third feature is that the switches of the individual parts are divided into the POWER ON switches 706 and 707 and the loop current switch 723, so that power is supplied to the AFE without flowing the loop current at the start of line connection.
  • it can be used for exchanging signals between modems and modems, such as caller ID notification.
  • the insertion position of the insulation bra in the AFE may be changed from that in Fig. 20.
  • an insulating plastic is placed between the ADC and DAC and the decimator and interpolator. Since the data transfer speed of this part is as fast as 2bit / wX2Msps or 6bit / wX2Msps, the insulated couplers are used in parallel, so that the delay time due to the transfer operation can be almost ignored. For this reason, for example, when the echo canceller or the termination is processed by the in-DSP, there is an advantage that the processing performance is less restricted than in the case of FIG.
  • a charge pump circuit may be used as the on / off control circuit of the NMOS switches 706 and 707.
  • the charge pump circuit includes a plurality of capacitors, a driver for supplying electric charges to the capacitors, and a plurality of switches and powers for controlling the supply of electric charges.
  • the driver and the switches supply electric charges to a certain capacitor, and then switch the switches.
  • This circuit obtains a voltage across another capacitor by repeating the operation of switching and transferring charges to another capacitor at high speed.
  • an on / off control circuit can be constituted only by silicon semiconductor elements by adding the insulation barrier according to the present invention, an inverter driver and a switching diode. Therefore, since the on / off control circuit can be integrated on the SOI substrate together with the I-AFE, the number of components of the modem device can be further reduced.
  • the chip layout has the effect of making the area smaller than 10% of the entire AFE.
  • the effect of significantly reducing the size is not changed as compared with the case where an insulating transformer or an insulating coupler using an external high withstand voltage capacitor is used.
  • Another characteristic of this integrated circuit is that it is economical because it is suitable for mass production.
  • FIG. 23 is a configuration diagram of an embodiment of a communication system in which a dem device and a host (PC) are combined.
  • reference numeral 810 is, for example, a discrete circuit portion described in FIG. 22, which includes a protection element, a connection switch, a DC closing circuit, a DC closing switch (DC loop), a call signal detection circuit, and the like.
  • DA A (Direct Access Arengment) means including: 81 1 is an isolation and filter such as I-AFE, AD and DA means, 81 2 is a modulation and demodulation means such as DSP, and 81 3 is a transmission control means consisting of 1 ⁇ [? 11, memory, software, etc. Yes, and these make up the modem section 800.
  • Reference numeral 801 denotes an application control means such as a PC, which includes an internal host CPU such as a WS, a PC, a PDA, a dedicated DSP, or a collective modem. This is the body control CPU, and is called the PC basic unit or host here.
  • an application control means such as a PC, which includes an internal host CPU such as a WS, a PC, a PDA, a dedicated DSP, or a collective modem. This is the body control CPU, and is called the PC basic unit or host here.
  • Fig. 23 (a) shows an embodiment in which signal processing is hierarchically divided among DSP, MPU, and PC, that is, an embodiment using I-AFE in a conventional modem configuration.
  • the expensive and large-sized insulating transformer in the DAA has been eliminated, reducing the number of photocobras, contributing to downsizing and economical equipment.
  • the monolithic insulating bra is built in the AFE, it can be combined with other parts if necessary. Further, the I-AFE and the DSP may be integrated so as to be integrated.
  • FIG. 23 (b) is a configuration diagram of one embodiment of a soft modem device using I-AFE.
  • the same reference numerals as those in FIG. 23 (a) have the same names
  • 822 is an interface (IZF) means for connecting the modulation / demodulation means 81 1 and the application control means 803. Includes 5Mbyte buffer memory and other control logic.
  • the feature of this configuration is that the modulation and demodulation means and transmission control means are batch-processed by the host CPU, thereby reducing the hardware of the modulation and demodulation means (DSP) 812 and the transmission control means (MPU) 913, and significantly reducing the number of modem devices. It achieves downsizing and economy.
  • the monolithic insulation bra may be combined with anything other than AFE.
  • the main function of the IZF means is to temporarily store AD and DA conversion data. If integrated with the I-AFE and integrated, the size of the modem device will be further reduced.
  • the 1 / means 822 may be integrated with the application control means 803. In modems such as notebook PCs, PDAs, collective modems, etc., where the modem and PC are integrated, Divisions are sparse and can be arranged according to other requirements.
  • I-AFE that is, the use of a monolithic insulating plug eliminates the insulating transformer, reduces the number of photocobblers, and reduces the size and cost. It is clear that this can be achieved.
  • the boundary between the modem section and the PC section includes a parallel bus such as the PCI standard and a serial bus such as IEEE1394 and USB, and the configuration of the present invention conforms to these. It is effective in expanding the application, and has the effect of downsizing and economy.
  • FIG. 24 is a system configuration diagram of still another embodiment.
  • 850 is a controller
  • 860 to 862 is an insulating plastic
  • 850 is a transceiver
  • 852 is a power regulator
  • 841 is an internal station that does not disclose but is another station, not shown, but further assumes a plurality of other stations, and these stations are a signal bus 871 and a power bus 87 2 and a control signal bus (not shown) and a network bus 870 including a power supply 880 are connected in parallel.
  • These stations consist of a controller and application circuit (controller-side circuit part) 850, a transceiver 851, and a power regulator 852 (network-side circuit part).
  • the transceiver 851 is connected to the controller and application circuit 8 through insulating brass 860 to 862 so that the network side circuit section is powered by the power bus 872. 50 and the signal bus 871 are connected.
  • the insulation bra connects the controller and application circuit 850 to the transceiver 851, and controls the standby operation of the transceiver 851.
  • a transceiver To communicate between one station 840 and another station, a transceiver must be By releasing the standby state and monitoring the received signal R, the signal bus 871 is found to be empty, and the transmission signal T addressed to another station is transmitted. Other stations sometimes release the transceiver from standby and monitor the received signal R, or monitor the status of the network bus control signal bus (not shown) to determine whether the signal is addressed to their own station.
  • control to continue receiving signals are merely examples, and modifications are possible.
  • the common thing about these devices connected to the network is the isolation of the network and the station. In other words, similarly to modems, it is essential that the network and the terminal do not spread the abnormal voltage even if it occurs due to other abnormal situations. Conventionally, expensive transformer photobras are required. It was used as this insulating means. For this reason, there was a problem of miniaturization and economy.
  • a monolithic insulating bra By applying a monolithic insulating bra, not only can the system be reduced in size and economy, but also it can be integrated into a IC by appropriately combining it with a controller circuit, transceiver circuit, etc. It also has the advantage of downsizing and economy.
  • Fig. 25 is a layout diagram of the insulation coupler corresponding to Fig. 16 when the insulator is not a one-stroke but allows a T-shaped or Y-shaped connection as shown in Fig. 15 (c). is there.
  • 201 to 207 are It has the same name as Figure 16.
  • the insulation band 206 which is a circle, has a Y-shaped connection at six locations, which insulate and isolate one input circuit area, two insulation barriers, and one output circuit area. are doing.
  • FIG. 26 is a block diagram of a digital insulating bra according to an embodiment of the present invention.
  • the primary circuit area, the insulation barrier, and the secondary circuit area are insulated and separated on the same semiconductor substrate.
  • P 1 s ⁇ in and P 1 s_out are an input pulse signal and an output pulse signal of the insulating bra, respectively.
  • Reference numeral 91 denotes a differential width circuit that generates a complementary pulse signal based on the input pulse signal P 1 s ⁇ in.
  • Reference numeral 902 denotes a capacitive insulating barrier that couples the complementary pulse signal driven by the differential amplifier circuit 91 with a high withstand voltage to the secondary side.
  • 90 3 is a differentiating circuit for differentiating the signal coupled from the primary side by the insulating barrier 90 2.
  • Reference numeral 944 denotes a transition detection circuit which receives the signal pair differentiated by the differentiation circuit 903, detects each edge of the differentiated signal pair, and amplifies it.
  • Reference numeral 905 denotes a pulse reproduction (demodulation) means for reproducing (demodulating) the input pulse signal P 1 s_in using the output signal of the transition detection circuit 4 and outputting the output pulse signal P 1 s_out.
  • all circuits including the insulating barrier 2 are configured in a monolithic IC, and the primary circuit region, the insulating barrier and the secondary circuit region are insulated and formed on the same semiconductor substrate.
  • Digital insulation bras can be downsized.
  • FIG. 27 is a specific circuit diagram of a digital insulation bra according to an embodiment of the present invention.
  • FIG. 28 is a diagram showing operation waveforms of the circuit of FIG. The operation of the circuit as a specific embodiment of the digital insulating bra according to the present invention will be described with reference to FIGS. 27 and 28.
  • reference numeral 910 denotes a differential amplifier circuit which receives an input pulse signal P 1 s-in and outputs a complementary pulse signal pair P 1 s-1.
  • the first stage consists of a CMOS differential amplifier, and outputs the result of comparison between the reference voltage Vref and the input pulse signal P1s_in as a complementary signal.
  • the driver of the next stage is composed of a CMOS inverter, and outputs a complementary pulse signal pair (output of differential amplifier circuit) P is-1 having an amplitude substantially equal to the power supply voltage.
  • 920 is a capacitive insulating barrier having a withstand voltage between the primary side and the secondary side.
  • the primary and secondary terminals are connected in the opposite direction to the high-potential power supply (VDD1 or VDD2) and to the low-potential power supply (VSS1 or VSS2), respectively.
  • a connection diode is provided to absorb surges due to noise and other factors.
  • the insulating barrier itself is also configured using a high withstand voltage capacitor (capacitor) formed in the same semiconductor integrated device.
  • Reference numeral 930 denotes a load resistor that constitutes differentiating means provided for outputting a differential waveform to the secondary terminal by capacitive coupling from the primary side.
  • the load resistance is provided so as to short-circuit the high-potential power supply VDD 2 and the terminal on the secondary side.
  • the secondary terminal is constantly fixed to the potential of the high-potential power supply VDD2, and when the primary terminal transitions from the “Hi” level to the “Lo” level, the “Lo” level Be A spike-like differential waveform is generated.
  • the 940 receives the differential signal pair P 1 s- 3, detects the rising edge and the falling edge of the input pulse signal P 1 s-in, and generates a one-shot pulse P 1 s- 4. Circuit.
  • a pair of CMOS differential amplifiers is used in which the differential signal pair P 1 s ⁇ 3 is connected in reverse to each other and used as an input signal.
  • Each pair of CMOS differential amplifiers outputs a single-ended signal. Since the input signal of the CMOS differential amplifier is constantly at the same level, the load was configured with a PMOS current mirror.
  • the CMOS differential amplifier outputs a differential output (individual CMOS differential amplifier) corresponding to the potential difference only when a potential difference occurs between the differential signal pair P 1 s-3 (the input pulse signal P 1 s-in transitions). Outputs single-ended output) PI s-40 is output. Therefore, the output P 1 s__40 of the pair of CMOS differential amplifiers is constantly at the same level. For this reason, it is necessary to design the output of the next-stage PMOS input level conversion circuit so as not to output an intermediate level (a level near the logic threshold value of the next-stage gate) when the input signal is at the same level.
  • the pulse regeneration (demodulation) circuit composed of the flip-flop at the next stage is received by the NAND gate of the CMOS, so that when the PI s-40 is at the same level, the “H i” level is output.
  • the gate width of the MOS of the level conversion circuit is designed. Therefore, the level conversion circuit calculates the ratio of the gate width Wp 1 of the PMOS 1 on the input side to the gate width Wn 1 of the NMOS 1 and the gate width Wp 2 of the PMOS 2 on the output side and the gate width Wn of the NMOS 2 The ratio of 2 should not be the same. Both outputs of the transition detection circuit 940 are normally at the “H i” level.
  • the output is switched to one at the rising edge and to the other at the falling edge.
  • Generates a level one-shot pulse. 950 reproduces the input pulse signal P 1 sin to the secondary side based on the output signal P 1 s— 4 of the transition detection circuit and outputs the output pulse P 1 s—
  • This is a pulse reproduction circuit composed of flip-flops that output ont.
  • the present embodiment is an example in which a pulse regeneration circuit is configured by a flip prop composed of two sets of CMOS-NAND gates and a driver of one set of CMOS inverters. If necessary, a means for resetting the flip-flop can be incorporated.
  • the output stage CMOS inverter of the differential amplifier circuit 910 sets the transition time of the falling edge when the logic threshold VLT is set lower than (VDD-VSS) 2 as in a CMOS inverter, for example. And the variation in timing can be suppressed.
  • the delay time of the circuit is not particularly mentioned, but the delay time of the circuit is sufficiently smaller / compared to the pulse width of the input pulse signal or the like related to the description of the operation. Although there is a delay time, no special consideration is given.
  • CMRR is an abbreviation for Coup on Mode Rejection Rate, which is the so-called common-mode signal rejection ratio.
  • the circuit is composed of simple CMOS gates, it can sufficiently cope with low voltages of 5 or less (up to about 1.8) and has the effect of reducing power consumption.
  • the SOI wafer substrate is normally used by grounding, the substrate is set to a floating potential so that the input circuit and the output circuit are doubled.
  • a buried insulating layer is included, so that higher withstand voltage can be achieved.
  • Fig. 29 shows how to reduce the effect of crosstalk between insulating bras, which can be a problem when the substrate is set at a floating potential, when multiple insulating bras are mounted on the same SOI semiconductor substrate. Means are shown.
  • Terminals POWER 1 and POWER 2 are power supply terminals for supplying the primary and secondary circuits of the insulating bra, respectively, and are connected to the substrate 965 of the SOI wafer by capacitors 963 and 964, respectively.
  • the capacitances 966 and 967 are stray capacitances existing between the insulating plugs 961 and 962 and the substrate 965, and most are coupling capacitances between the insulating barrier and the substrate.
  • the capacities 963 and 964 are described as separate components from the semiconductor.
  • the circuit area other than the insulating bra is large, such as IAFE, and as a result, the primary circuit and No additional capacitance is required if the combined doses of the secondary circuit and the substrate are large.
  • the same operation and effect can be obtained even when the plurality of insulating bras face different directions.
  • the above external capacitor can also be used as a crosstalk countermeasure. It is also possible to use a surge absorbing element as this capacitance, and in this case, in addition to the above-described effects, a surge suppression effect can be obtained.

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Abstract

Un circuit d'interface de transmission peut devenir monolithique par formation d'un coupleur isolant, pourvu d'une barrière isolante capacitive sur un substrat silicium sur isolant (SOI), et par synchronisation du cadencement du traitement numérique de signaux, de circuits d'entrée analogiques et dudit coupleur isolant, au moyen d'une horloge régissant le traitement numérique des signaux. On peut ainsi fabriquer un modem à la fois rentable et de petite taille.
PCT/JP1998/001431 1997-03-31 1998-03-30 Modem utilisant une barriere isolante capacitive et un coupleur insolant, et circuit integre utilise par ce modem WO1998044687A1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP98911091A EP0973305A1 (fr) 1997-03-31 1998-03-30 Modem utilisant une barriere isolante capacitive et un coupleur insolant, et circuit integre utilise par ce modem
KR1019997008865A KR20010005793A (ko) 1997-03-31 1998-03-30 용량성 절연 배리어를 사용하는 모뎀장치 및 절연커플러와 모뎀장치에 사용되는 집적회로
JP54144598A JP4005145B2 (ja) 1997-03-31 1998-03-30 容量性絶縁バリヤを用いるモデム装置及び絶縁カプラ並びにモデム装置に用いられる集積回路

Applications Claiming Priority (10)

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JP9/79551 1997-03-31
JP7955197 1997-03-31
JP29819097 1997-10-30
JP9/298190 1997-10-30
JP29816697 1997-10-30
JP29818997 1997-10-30
JP9/298166 1997-10-30
JP9/298189 1997-10-30
JP10/46827 1998-02-27
JP4682798 1998-02-27

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Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2799912A1 (fr) * 1999-10-19 2001-04-20 St Microelectronics Sa Transmission d'une horloge par une barriere d'isolement capacitive
EP1197028A1 (fr) * 1999-07-23 2002-04-17 Silicon Laboratories, Inc. Modem integre et circuits d'isolation de ligne, et procede associe
US6662238B1 (en) 1999-07-23 2003-12-09 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry with command mode and data mode control and associated method
US6724891B1 (en) 1998-03-04 2004-04-20 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry and associated method powering caller ID circuitry with power provided across an isolation barrier
US6735246B1 (en) 1999-07-23 2004-05-11 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry with data flow control and associated method
US6826225B1 (en) 1999-07-23 2004-11-30 Silicon Laboratories, Inc. Integrated modem and line-isolation circuitry with selective raw data or modem data communication and associated method
US6977522B1 (en) 1999-12-15 2005-12-20 Hitachi, Ltd. Interface device and information processing system
US7020187B1 (en) 1999-07-23 2006-03-28 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry with HDLC framing and associated method
US7161264B2 (en) * 2001-02-15 2007-01-09 Hitachi, Ltd. Semiconductor circuit having drivers of different withstand voltage within the same chip
JP2007080288A (ja) * 2006-11-14 2007-03-29 Hitachi Ltd インタフェース装置
JP2008259103A (ja) * 2007-04-09 2008-10-23 Hitachi Ltd 搬送波周波数の異常検知手段
JP2008277941A (ja) * 2007-04-26 2008-11-13 Nec Electronics Corp インタフェース回路
JP2009147297A (ja) * 2007-11-20 2009-07-02 Denso Corp Ｓｏｉ基板を用いた半導体装置およびその製造方法
JP2014075499A (ja) * 2012-10-05 2014-04-24 Panasonic Corp 半導体装置および当該半導体装置を用いた半導体リレー
JP2014523556A (ja) * 2011-05-25 2014-09-11 ザ シラナ グループ プロプライエタリー リミテッド Ｕｓｂ２．０高速モードを有するｕｓｂアイソレータ集積回路および自動速度検出
JP2015503306A (ja) * 2011-12-19 2015-01-29 ヴァレオ システム ドゥ コントロール モトゥール 少なくとも１つの第１のシステムと少なくとも１つの第２のシステムとの間での通信方法
JP2020511827A (ja) * 2017-03-01 2020-04-16 ローズマウント インコーポレイテッド 容量性結合による本質的に安全な離間
JP2020536470A (ja) * 2017-09-26 2020-12-10 スピナー ゲーエムベーハー ２つの物理インターフェース間におけるデータ伝送装置および方法
JP2021042996A (ja) * 2019-09-06 2021-03-18 株式会社東芝 電子回路、電流計測装置、および方法
WO2022210551A1 (fr) * 2021-03-29 2022-10-06 ローム株式会社 Isolateur, module isolant et circuit d'attaque de grille

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546594A (en) * 1978-09-28 1980-04-01 Siemens Ag Monolithic integrated circuit with high dielectric strength
JPS5586144A (en) * 1978-12-25 1980-06-28 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
JPS5720059A (en) * 1980-07-09 1982-02-02 Matsushita Electric Ind Co Ltd Insulating transmitter for digital signal
JPS63107358A (ja) * 1986-10-24 1988-05-12 Nec Corp 音声とデ−タの同時通信方式
JPH0223664A (ja) * 1988-07-12 1990-01-25 Seiko Epson Corp 半導体装置の製造方法
JPH0685963A (ja) * 1992-06-09 1994-03-25 Rockwell Internatl Corp モデムサージ保護回路およびサージ保護方法
JPH06205131A (ja) * 1992-10-14 1994-07-22 Philips Electron Nv モデムを有する電話装置
JPH06284155A (ja) * 1992-11-25 1994-10-07 Yamaha Corp 変調装置及び復調装置
JPH0774611A (ja) * 1993-08-31 1995-03-17 Fujitsu Ltd 入力回路
JPH0794679A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd 半導体装置
JPH07154503A (ja) * 1993-11-29 1995-06-16 Toshiba Corp 呼出信号変換装置及び同装置を用いた通信システム
JPH07235638A (ja) * 1994-02-23 1995-09-05 Toshiba Corp 半導体装置
JPH07297273A (ja) * 1994-04-20 1995-11-10 Hitachi Ltd 半導体集積回路装置
JPH0851493A (ja) * 1994-08-05 1996-02-20 Fujitsu Ltd 電話機
JPH08335684A (ja) * 1995-06-08 1996-12-17 Toshiba Corp 半導体装置

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5546594A (en) * 1978-09-28 1980-04-01 Siemens Ag Monolithic integrated circuit with high dielectric strength
JPS5586144A (en) * 1978-12-25 1980-06-28 Chiyou Lsi Gijutsu Kenkyu Kumiai Semiconductor device
JPS5720059A (en) * 1980-07-09 1982-02-02 Matsushita Electric Ind Co Ltd Insulating transmitter for digital signal
JPS63107358A (ja) * 1986-10-24 1988-05-12 Nec Corp 音声とデ−タの同時通信方式
JPH0223664A (ja) * 1988-07-12 1990-01-25 Seiko Epson Corp 半導体装置の製造方法
JPH0685963A (ja) * 1992-06-09 1994-03-25 Rockwell Internatl Corp モデムサージ保護回路およびサージ保護方法
JPH06205131A (ja) * 1992-10-14 1994-07-22 Philips Electron Nv モデムを有する電話装置
JPH06284155A (ja) * 1992-11-25 1994-10-07 Yamaha Corp 変調装置及び復調装置
JPH0774611A (ja) * 1993-08-31 1995-03-17 Fujitsu Ltd 入力回路
JPH0794679A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd 半導体装置
JPH07154503A (ja) * 1993-11-29 1995-06-16 Toshiba Corp 呼出信号変換装置及び同装置を用いた通信システム
JPH07235638A (ja) * 1994-02-23 1995-09-05 Toshiba Corp 半導体装置
JPH07297273A (ja) * 1994-04-20 1995-11-10 Hitachi Ltd 半導体集積回路装置
JPH0851493A (ja) * 1994-08-05 1996-02-20 Fujitsu Ltd 電話機
JPH08335684A (ja) * 1995-06-08 1996-12-17 Toshiba Corp 半導体装置

Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724891B1 (en) 1998-03-04 2004-04-20 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry and associated method powering caller ID circuitry with power provided across an isolation barrier
US6819710B1 (en) 1999-07-23 2004-11-16 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry and associated method having intrusion detection
US6826225B1 (en) 1999-07-23 2004-11-30 Silicon Laboratories, Inc. Integrated modem and line-isolation circuitry with selective raw data or modem data communication and associated method
US6662238B1 (en) 1999-07-23 2003-12-09 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry with command mode and data mode control and associated method
US6714590B1 (en) 1999-07-23 2004-03-30 Silicon Laboratories, Inc. Integrated modem and line-isolation circuitry and associated method
EP1197028A1 (fr) * 1999-07-23 2002-04-17 Silicon Laboratories, Inc. Modem integre et circuits d'isolation de ligne, et procede associe
US6735246B1 (en) 1999-07-23 2004-05-11 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry with data flow control and associated method
EP1197028A4 (fr) * 1999-07-23 2002-10-23 Silicon Lab Inc Modem integre et circuits d'isolation de ligne, et procede associe
US7020187B1 (en) 1999-07-23 2006-03-28 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry with HDLC framing and associated method
US6771696B1 (en) 1999-07-23 2004-08-03 Silicon Laboratories Inc. Integrated modem and line-isolation circuitry and associated method utilizing a DC termination pin to monitor line voltage
FR2799912A1 (fr) * 1999-10-19 2001-04-20 St Microelectronics Sa Transmission d'une horloge par une barriere d'isolement capacitive
US6977522B1 (en) 1999-12-15 2005-12-20 Hitachi, Ltd. Interface device and information processing system
US7479804B2 (en) 1999-12-15 2009-01-20 Hitachi, Ltd. Interface device and information processing system
US7102388B2 (en) 1999-12-15 2006-09-05 Hitachi, Ltd. Interface device and information processing system
US7759975B2 (en) 1999-12-15 2010-07-20 Hitachi, Ltd. Interface device and information processing system
US7161264B2 (en) * 2001-02-15 2007-01-09 Hitachi, Ltd. Semiconductor circuit having drivers of different withstand voltage within the same chip
JP2007080288A (ja) * 2006-11-14 2007-03-29 Hitachi Ltd インタフェース装置
JP4560030B2 (ja) * 2006-11-14 2010-10-13 株式会社日立製作所 インタフェース装置
JP2008259103A (ja) * 2007-04-09 2008-10-23 Hitachi Ltd 搬送波周波数の異常検知手段
JP2008277941A (ja) * 2007-04-26 2008-11-13 Nec Electronics Corp インタフェース回路
JP2009147297A (ja) * 2007-11-20 2009-07-02 Denso Corp Ｓｏｉ基板を用いた半導体装置およびその製造方法
JP4737255B2 (ja) * 2007-11-20 2011-07-27 株式会社デンソー Ｓｏｉ基板を用いた半導体装置
JP2014523556A (ja) * 2011-05-25 2014-09-11 ザ シラナ グループ プロプライエタリー リミテッド Ｕｓｂ２．０高速モードを有するｕｓｂアイソレータ集積回路および自動速度検出
JP2015503306A (ja) * 2011-12-19 2015-01-29 ヴァレオ システム ドゥ コントロール モトゥール 少なくとも１つの第１のシステムと少なくとも１つの第２のシステムとの間での通信方法
JP2014075499A (ja) * 2012-10-05 2014-04-24 Panasonic Corp 半導体装置および当該半導体装置を用いた半導体リレー
JP2020511827A (ja) * 2017-03-01 2020-04-16 ローズマウント インコーポレイテッド 容量性結合による本質的に安全な離間
JP7035071B2 (ja) 2017-03-01 2022-03-14 ローズマウント インコーポレイテッド 容量性結合による本質的に安全な離間
JP2020536470A (ja) * 2017-09-26 2020-12-10 スピナー ゲーエムベーハー ２つの物理インターフェース間におけるデータ伝送装置および方法
JP2021042996A (ja) * 2019-09-06 2021-03-18 株式会社東芝 電子回路、電流計測装置、および方法
WO2022210551A1 (fr) * 2021-03-29 2022-10-06 ローム株式会社 Isolateur, module isolant et circuit d'attaque de grille

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