WO1998041987A1 - Dispositif et procede de production d'un signal numerique a l'aide d'une memoire a largeur de bus variable et dispositif et procede d'enregistrement du signal numerique - Google Patents

Dispositif et procede de production d'un signal numerique a l'aide d'une memoire a largeur de bus variable et dispositif et procede d'enregistrement du signal numerique Download PDF

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Publication number
WO1998041987A1
WO1998041987A1 PCT/JP1997/000910 JP9700910W WO9841987A1 WO 1998041987 A1 WO1998041987 A1 WO 1998041987A1 JP 9700910 W JP9700910 W JP 9700910W WO 9841987 A1 WO9841987 A1 WO 9841987A1
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WIPO (PCT)
Prior art keywords
data
memory
bits
address
access
Prior art date
Application number
PCT/JP1997/000910
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English (en)
Japanese (ja)
Inventor
Hiroshi Hirayama
Toshifumi Takeuchi
Yutaka Nagai
Osamu Kawamae
Taku Hoshizawa
Kenji Akahoshi
Original Assignee
Hitachi, Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Hitachi, Ltd. filed Critical Hitachi, Ltd.
Priority to PCT/JP1997/000910 priority Critical patent/WO1998041987A1/fr
Publication of WO1998041987A1 publication Critical patent/WO1998041987A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Definitions

  • the present invention relates to a digital signal reproducing apparatus using a variable bus width memory, a reproducing method, a recording apparatus, and a recording method.
  • the present invention relates to a digital signal reproducing device, a reproducing method, a recording device, and a recording method.
  • a digital signal is arranged in a predetermined arrangement, and By reading a data sequence for executing a predetermined process such as error correction and a data sequence after a predetermined process is completed, a reproduction process or a recording process for a digital signal is performed.
  • the present invention relates to a digital signal reproducing device, a reproducing method, a recording device, and a recording method. Background art
  • CD Compact Disc
  • This CD is converted to sampled 16-bit audio data, as in the technology described in “CD—From Audio to Nokonone, edited by Fujio Marito and edited by Kenji Hayashi, Corona Publishing, p.13 to p.14”.
  • the upper and lower bits are divided into 8-bit (1 symbol) units, and one frame is composed of multiple symbol data.
  • a C2 correction code is added as an error correction code, and interleaving between frames is performed.
  • EFM Eight to Fourteen Modulation
  • the signal read from the disc is subjected to demodulation processing, error correction processing by decoding Cl and C2 correction codes, and deinterleaving processing in the reverse order. As a result, playback data for the original audio data is obtained.
  • Access is made to the memory means in the playback device in symbol units, and the playback is performed by writing demodulated data, reading out the demodulated data to be subjected to error correction, and reading out the reproduced data in a chronologically continuous order. Is performed.
  • RAM Random Access Memory
  • the power consumption becomes large especially when the logic circuit and the memory operate at a high speed.
  • the access performance cannot be utilized and the data transfer rate at the time of reading the reproduced data is reduced.
  • DRAM digital signal processing requires a large-capacity memory and large-scale logic circuits in DVD, which is being developed in recent years.
  • DRAM is advantageous in terms of large-capacity memory, and in order to access this large-capacity memory and perform digital signal processing at high speed, DRAM and logic circuits must be mounted on the same semiconductor chip using the above-mentioned DRAM mixed technology. In this case, the power consumption of the entire semiconductor chip becomes prominent in terms of the number of memory accesses and high-speed operation.
  • an object of the present invention is to provide a digital signal reproducing apparatus and a reproducing method capable of easily controlling an address at the time of accessing a memory, reducing the number of times of memory access, and improving the transfer speed of transfer data. And a recording device and a recording method.
  • the processing means and the memory are provided on the same semiconductor chip, the power consumption of the entire semiconductor chip can be reduced and the digital signal processing can be performed at high speed. It provides a digital signal processing system on a semiconductor chip that performs high-speed data transfer. Disclosure of the invention
  • At least a demodulation means for demodulating a read signal from a recording medium and outputting demodulated data in n-bit units, and a data array for error correction processing in n-bit units Selects the error correction processing means for processing, the output processing means for processing the data array of the reproduced data in nxm bit units, and the data bus of the above means for the data bus of the memory means
  • a means for generating a control instruction for the memory means, the connection means, and the address generation means are examples of the memory means.
  • the memory means has an access bit width of n bits and n bits. It has a bus width variable means that can be accessed by switching to xm bits, and a control means for accessing the memory means is provided.
  • the control means is capable of transferring data to the output processing means in units of nxm bits. This is done by setting the bus width to nxm bits when reading.
  • the number of accesses to the memory can be reduced, and the data transfer speed can be improved.
  • the memory means having a variable access bit width When the memory means having a variable access bit width, the connection means, the memory control means, and the processing means are provided on the same semiconductor chip, the type of the variable access bit width (n bits Width and n x m bit width), the memory means that can set the access bit width variably are provided on the semiconductor chip, and the large-capacity memory means is used for the semiconductor chip. If necessary, a dynamic memory that requires a refresh operation in a fixed time is used as the memory means.
  • the logic circuits and the memory provided on the same semiconductor chip provide the access bit width and width required for digital processing. It can be configured freely according to storage capacity and storage capacity. That is, each logic circuit required for a predetermined process can be configured to be advantageous in terms of processing efficiency, and a memory that can access the logic circuit according to the required access bit width can be configured. become.
  • FIG. 1 is a block diagram showing a configuration of a first embodiment according to the present invention.
  • FIG. 2 is a flowchart showing a process of controlling access to the memory cell A in the embodiment of FIG.
  • FIG. 3 is a diagram showing an access sequence of each processing required up to output interpolation and filter processing, and a method of controlling an address of the memory cell A.
  • FIG. 4 is a block diagram showing an example of the configuration of a memory cell A in which the access bit width is variable, such as 8 bits and 16 bits.
  • FIG. 5 is a diagram showing a frame structure of data recorded on the optical disc 1 in the embodiment shown in FIG.
  • FIG. 6 is a diagram showing an inter-frame delay in each process for symbol data after demodulation from the optical disc 1 in the embodiment shown in FIG.
  • FIG. 7 is a block diagram showing a configuration of a second embodiment according to the present invention.
  • FIG. 8 is a flowchart showing a process of controlling access to the memory cell B in the embodiment of FIG.
  • FIG. 9 is a diagram showing a configuration of one sector composed of data read from the memory cell A in the embodiment shown in FIG.
  • FIG. 10 shows the embodiment shown in FIG. FIG. 9 is a diagram showing an access sequence of each processing required until data transfer and an address control method of a memory cell B.
  • FIG. 11 is a block diagram showing the configuration of the third embodiment according to the present invention.
  • FIG. 12 is a block diagram showing an example of the configuration of a memory cell C having variable access bit widths of 8, 32 bits.
  • FIG. 13 is a diagram showing an access sequence of each processing required until data transfer to the interface circuit and an address control method of the memory cell C in the embodiment shown in FIG.
  • FIG. 14 is a flowchart showing a process of controlling access to the memory cell C in the embodiment of FIG.
  • FIG. 15 is a block diagram showing the configuration of the fourth embodiment according to the present invention.
  • FIG. 16 is a flowchart showing a process of controlling access to the memory cell C in the embodiment of FIG.
  • FIG. 17 is a block diagram showing the configuration of the fifth embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a block diagram showing a configuration of a reproducing apparatus and a reproducing method according to a first embodiment of the present invention.
  • reference numeral 1 denotes an optical disk on which a 16-bit digital audio signal to be recorded is recorded with a digital signal obtained by encoding the data in a predetermined format
  • reference numeral 2 denotes a signal recorded on the optical disk 1.
  • a pickup for reading the read signal, 3 is a preamplifier
  • 4 is a frame sync detection circuit that detects a sync signal indicating the beginning of a frame composed of signals read from the optical disc 1
  • 5 is a modulated and recorded signal.
  • EFM demodulation circuit that demodulates the read signal from disk 1 into the original 8-bit, 1-symbol data, and 6 decodes the correction code added to the signal for errors that occurred during disk read.
  • C1 and C2 correction circuits that perform error correction in symbol units that are present in the signal, and perform processing in units of 16 bits, 2 symbols.
  • Target 8 bits Selector A which connects the data bus to the direct, and for 16-bit access, directly connects the 16-bit data bus of memory cell A directly to the direct Access selection instruction to control selection, memory read, write switching instruction, 8-bit, 16-bit switching instruction, address sequence for accessing memory cell A (demodulation system, C1, C2 Correction system, playback system)
  • the access control circuits A and 12 that generate selection instructions respectively generate the addresses to be accessed according to the address sequence selection instruction, and the address generation circuits A and 13 that generate the addresses are generated.
  • the address decoder A decodes the address to the address of the memory cell A.
  • the digital audio signal to be reproduced recorded on the optical disc 1 is read out from the pickup 2, and the frame synchronization signal included in the read signal is detected by the frame synchronization of 4. This is performed by the detection circuit 4.
  • Fig. 5 shows the structure of the frame, which is the processing unit of the digital signal stored in the optical disc 1
  • Fig. 6 shows the structure required for obtaining the reproduced data. The processing will be described.
  • the structure of frame 501 which is the unit to be recorded on optical disc 1, records a synchronization signal 502 indicating the beginning of the frame, and playback time information and the like for that frame.
  • the subcode and frame data are composed of 8 bits as one symbol, and the frame data is composed of 24 data symbols, C1, and C2.
  • the correction code consists of 4 symbols each, for a total of 32 symbols.
  • C1 correction is performed on a frame sequence as shown by reference numeral 602 in the figure where odd-numbered symbol data is delayed by one frame.
  • Fig. 1 shows the processing for each series of frame data as described above, and the arrangement of symbol data to facilitate output interpolation and readout of reproduced data to the filter circuit 7 in units of two symbols (one symbol). , And the method of controlling the memory address will be described with reference to FIG.
  • reference numerals 304 and 305 denote symbol arrangement examples in which the readout control of reproduced data can be easily performed and the access unit can be set to 1 unit.
  • 4 is the reproduced data sequence from the 0th to 11th symbol in the (n-3) th frame
  • 305 is the reproduced data sequence from the 16th to 27th symbol in the (n-3) th frame. is there. Playback data in such an arrangement
  • the C2 correction sequence is given by the frame delay of the relationship shown by the C2 correction sequence 603 and the reproduction sequence 604, 605 described in FIG. These are 0 to 15 symbols in the reproduced data sequence and 16 to 27 symbols in the reproduced data sequence delayed by 2 frames.
  • the C2 correction sequence for the reproduced sequence in this case is arranged in a line as shown in 303 (in Fig. 3, 303 is the C2 correction sequence of the (n-1) th frame). Series).
  • the C2 correction sequence has a maximum frame delay of 108 frames with respect to the C1 correction sequence, and the delay of 4 frames increases for each symbol.
  • the arrangement is as shown in 2. (302 in the figure indicates the C1 correction sequence of the (n-1) th frame).
  • the demodulation sequence is arranged like 301 (in the figure, 301 is the demodulation sequence of the nth frame) Is shown).
  • the address control method when accessing the symbol arrangement of each series with the memory is as follows.To facilitate address control, for example, 16 symbols in the horizontal direction and 4 64 bytes in the vertical direction are assigned.
  • One unit of control one bank (306 in the figure) is used as the basic unit for address control.
  • Reference numeral 307 denotes a column address indicating a vertical address of one link
  • reference numeral 308 denotes a row address indicating a horizontal address.
  • the access control circuit A 11 is connected to the selector A 10 and memory cells A 9 and 12 of memory 9.
  • Each control instruction is generated for each control target of the dress generation circuit A.
  • 10 selector A is connected to the 8-bit data bus from the EFM demodulation circuit of 5 and the lower 8 bits of the 16-bit data bus of memory cell A according to the access selection instruction
  • memory cell A of 9 is 8 bits and 16
  • the circuit A is set so as to generate the address of the demodulation sequence in accordance with the address sequence selection instruction (step 201).
  • the EFM demodulation processing is started, and the address generation circuit A of FIG. 12 follows the address designation method described in FIG. 3 to specify the demodulation sequence address, column address, row bank, A column address is generated for each symbol write, and the address of decoder 13 is decoded to the address of memory cell A and written to memory cell A for each symbol (step 20). 3).
  • Figure 4 shows an example of the configuration of memory cell A. It has two memory links 410 and 402 that can be accessed in 8-bit units, and the memory bank can be specified by specifying addresses in the row and column directions. Is accessible.
  • Reference numeral 403 denotes a bank switching selector which can select a memory bank in 8-bit access according to a bank selection signal.
  • 404 is the upper 8 bits of the 8-bit bus of memory bank 1 and the lower 8 bits of the 8-bit bus of memory link 2, for a total of 16-bit data.
  • the lower 8 bits are the 8-bit data of memory bank 1 or 2 selected by selector 403, and the upper 8 bits are read. It is a selector that selects "16 bit data" by adding "0" as bit data.
  • Reference numeral 405 denotes an IZO buffer that determines a transfer direction in accordance with a read / write switching instruction. With such a configuration, the memory cell A is configured, and the access bit width can be switched. Note that instead of physically switching the buses, all the buses are physically connected, but only the bus of the bus width used at that time may be used.
  • the access control circuit A reads the C1 correction sequence frame from the memory cell A for each control target. Generate instructions for loading. Selector A is an 8-bit data bus to the C1 and C2 correction circuits and one of memory cells A so that the symbol data of the C1 correction sequence can be read to the C1 and C2 correction circuits. Connect the lower 8 bits of the 6-bit data bus, select memory cell A to read, and set address generation circuit A to generate the C1 correction sequence address (step 2). 0 5). When the memory access selection for the C 1 correction processing is completed, the address generation circuit A generates the row, column, mouth unlock, and power bank address of the C 1 correction sequence for each symbol read.
  • the address decoder A decodes the address of the memory cell A, and one correction sequence data is read from the memory cell A for each symbol (step 206), and the read C 1 correction is performed. Correction of errors occurring during the sequence is performed on the frames of the sequence (step 207).
  • the access control circuit A When the processing of the C 1 correction sequence is completed, the access control circuit A generates an instruction for reading a frame of the C 2 correction sequence from the memory cell A for each control target.
  • the address generation circuit A is set to generate the address of the C2 correction sequence (step 208), and the row, column, mouth link, and column bank address of the C2 correction sequence are represented by one symbol.
  • Decoder A Generated for each lead, add Decoder A decodes the address of memory cell A, reads C2 correction sequence data for each symbol from memory cell A (step 209), and reads the read C2 correction sequence. Correction of errors that occurred during the sequence for the frame is performed (step 210).
  • the access control circuit A When the processing of the C2 correction sequence is completed, the access control circuit A generates an instruction for reading the reproduced data sequence from the memory cell A in units of one word (two symbols) for each control target. Selector A performs processing in units of 1 bit.Output interpolation, connects 16-bit data bus to filter circuit 7 and 16-bit data bus of memory cell A, output interpolation, 1-byte unit to filter circuit 7. Data transfer is enabled, memory cell A selects the access bit width to 16 bits, and end address generation circuit A is set to generate the address of the reproduced data sequence (step 211 1).
  • step 2 12 Decode and read the playback data (step 2 12).
  • the read playback data is subjected to interpolation processing if correction is not possible, and is output from the output terminal 8 after filtering. If the reproduction is to be continued, the processing is restarted from step 201 (step 211).
  • the demodulation method for the serial data read from the optical disc 1 and digitized is the same as that for the 17 bit clocks transmitted in synchronization with the serial data.
  • the output interpolation and data transfer to the filter circuit are performed in units of 8 bits at a time, two transfers are required to transfer the same 16-bit data amount.
  • the output transfer frequency Fo is 1/68, F0, and 1Z34 for the bit clock frequency 1, and the data transfer rate is higher than when using a memory with a variable access bit width. Transfer efficiency decreases.
  • the writing of data in symbol units after demodulation processing is performed by configuring one bank in units of a set of multiple symbols and performing access control by specifying the row and column addresses in one link, and the row and column addresses for the link. Address control becomes easy.
  • the access bit width of memory cell A when reading the reproduction data series can be set to 16 bits and the read unit can be set to 1 ⁇ , the number of memory accesses is reduced, and the power consumption of the entire reproduction device is reduced. It leads to reduction.
  • the memory cell A each processing circuit, Even when the control circuit is provided on the same semiconductor chip, the number of memory accesses is reduced, which leads to a reduction in power consumption of the entire semiconductor chip.
  • FIG. 7 is a block diagram showing a second embodiment of a reproducing apparatus and a reproducing method according to the present invention, wherein reference numeral 1 denotes an optical disk on which digital data to be processed by a host computer is recorded.
  • 14 is a sector synchronization signal detection circuit that detects the beginning of a sector composed of read data read from memory cell A in 1-byte units, and 15 is a decoder that decodes the correction code contained in one sector.
  • a P and Q correction circuit that corrects errors that occur in the sector.
  • 16 is an interface circuit that transfers data in units of 2 words (32 bits) between the host computer and the playback device. 7 is variably accessible with an access bit width of 1 word (16 bits) and 2 words (32 bits).
  • the access control circuit B When controlling the access to memory cell B, in the case of 16-bit access, the lower 16 bits of the 32-bit data bus of memory cell B and the 16-bit data to be accessed are controlled.
  • the selector B connects the direct bus to the direct, and in the case of 32 bit access, the 32 bit data bus of the memory cell B is directly connected to the direct.
  • the selectors B and 19 are access selection instructions, read, and so on of the memory cell B.
  • La Instruction to switch the bit width, 16-bit, 32-bit access bit width, and memory cell B address series vector data system, P, Q correction system, host transfer system
  • the generated access control circuits B and 20 follow the address sequence selection instruction,
  • An address generation circuit B, 21 for generating an address for data of a unit of one-line of each series, is an address decoder B for decoding the generated address to an address of the memory cell B.
  • the structure of one sector 901 which is read from memory cell A, is composed of a 12-byte sector synchronization signal 902 indicating the beginning of the sector and an optical signal in which the sector exists.
  • 4-byte (2-word) sector ID that stores information such as addresses on the disk, user data to be transferred to the host computer 904, correction of errors that occurred during the sector It is composed of 288-note P and Q correction codes for performing With respect to the sector having such a configuration, the address control for the remaining data (time series serial numbers 0 to 1169 in word units of 906) for which the sector synchronization signal is detected is based on the first control. As shown in Fig.
  • memory access control is performed by the sector data address control method shown in FIG. 10, and data is transferred to the host computer via the interface circuit in units of two bits.
  • step 801 when an access command from the host convenience is received by the interface circuit 16, signal reading is started from the optical disk 1, and each access by the memory cell A is performed. The processing is performed, and sector data in units of one lead is read (step 801).
  • the sector synchronization detection circuit of 14 detects the sector synchronization signal included in the read sector data, 1
  • the sector ID included in the sector is detected by the 31 sector ID detection circuit (step 812).
  • the host access user access instruction includes a transfer start sector ID for starting data transfer, and when a match between the transfer start sector ID and the detected sector ID is detected, each control by the access control circuit B of 19 is performed.
  • the setting for the target is started, and if they do not match, the sector ID match detection is continued (step 802).
  • the 19 access control circuit B makes the 18 selectors B and 17 For each controlled object of the memory cell B and the address generation circuit B of 20, a command for writing sector data from the transfer start sector ID to the memory cell B is generated.
  • Synchronization detection circuit Connects the 1st data bus to the lower 1st of the 2nd data bus of memory cell B, 16 bits and 32 bits for memory cell B.
  • the switch command Section after synchronization detection in units of ⁇ ) (16 bits)
  • To write evening data set the access bit width to 16 bits, select the write according to the read / write switching instruction, and the address generation circuit B uses the sector data system according to the address series selection instruction.
  • the address is set to be generated (step 802).
  • the sector data after the detection of the sector synchronization signal is sent in word units, and the address generation circuit B follows the address control method of the sector data shown in FIG. A row address and a column address are generated for each word, and the address of the memory cell B is decoded by the address decoder B of 21 and written to the memory cell B for each step (step 8). 0 3).
  • access control circuit B When sector data is written in units of one sector up to the storage capacity of memory cell B (step 804), access control circuit B reads a P correction sequence from memory cell B for each control target.
  • C selector B that generates an instruction for connecting the 1st data bus to the P and Q correction circuits and the lower 1 byte data bus of the memory cell B, selects the lead for the memory cell B, and the address generation circuit B Is set to generate the row and column addresses of the P correction sequence (step 805).
  • the end address generation circuit B When the memory access selection for the P correction sequence is completed, the end address generation circuit B generates an address of the P correction sequence for each address, and the end address decoder B decodes the address of the memory cell B to the address.
  • the P correction sequence data is read from the memory cell B every 1 mode. Correction of an error that has occurred in the sequence is performed on the read P-correction sequence (step 806).
  • the access control circuit B When the processing of the P correction sequence is completed, the access control circuit B generates an instruction for reading the Q correction sequence from the memory cell B for each control target.
  • the address generation circuit B is set so as to generate an address of the Q correction sequence (step 807), and generates a row and a column address of the Q correction sequence for each one-lead, and the end is generated by the address decoder B. Decode to the address of memory cell B
  • the Q correction sequence data is read from memory cell B every 1 mode. Correction of an error occurring in the read Q correction sequence is performed (step 808).
  • the access control circuit B When the correction process of the Q correction sequence is completed, the access control circuit B generates an instruction for reading the host transfer data sequence from the memory cell B for each control target. Selector B connects the 2-word data bus (32 bits) to the interface circuit 16 and the 2-word data bus of memory cell B, and memory cell B has an access bit width of 3 bits. Selected as 2 bits, the address generation circuit B is set to generate the address of the host transfer data sequence (step 809), and the first one of the two-word unit host transfer data sequence is set. A row and column address for a word are generated every two words, and a row and column address for the first word of 2-word data are specified.
  • the address decoder B decodes the generated 2-address unit start address to the address of the memory cell B, and reads and interfaces in 2-access units per access.
  • the data is transferred to 16 (step 810), and the interface circuit transfers data to the host computer in units of 2 leads. If the number of sectors requested to be transferred from the host computer is less than the number of sectors (step 811), the process is repeated from step 802. If the number of sectors is reached, the process is terminated.
  • the demodulation method for serial data read from the optical disc 1 and digitized is a bit clock 17 bit synchronously transmitted with the serial data.
  • the EFM demodulation circuit converts from the serial data of one minute (demodulated data — serially transferred in units of 14 bits and a margin of 3 bits) to parallel data in units of 8 bits.
  • the relationship between the number of bit clocks indicating the number of transfers and the number of transfers when performing data transfer from the interface circuit in units of 32 bits is as follows. If a memory with a variable access bit width is used and the redundancy is set to 100% in consideration of redundancy such as an error correction code, 8 bits for (17 + 17) bit clocks can be used.
  • the ratio becomes 34: 1, and when the redundancy is 0, the relationship becomes 17: 1. Therefore, since the redundancy is generally smaller than 100% and larger than 0%, the output transfer frequency Fo is 1/3 4 ⁇ FO ⁇ 1 Z 1 for the bit clock frequency 1. It becomes 7.
  • the data transfer from the interface circuit is 16 bits at a time, the same amount of data of 32 bits needs to be transferred twice.
  • the output transfer frequency F 0 is 1/688, F o, and 1 ⁇ 34 for a bit clock frequency of 1.
  • the data transfer from the interface circuit or the data transfer from the memory means to the interface circuit is performed in units of 8 bits, it is necessary to transfer the data amount of 32 bits to the interface circuit. Transfer from the circuit or memory access is required four times, and under the same conditions as above, a data amount of 32 bits must be transferred for every four bit clocks (17 + 17).
  • the relationship (1 36 to 68): 1 is satisfied, and for a bit clock frequency of 1, the output transfer frequency Fo is 1/136 ⁇ FO ⁇ 1Z688, and the data transfer efficiency is low. It decreases significantly. Therefore, in this embodiment, necessary processing is performed on a sector composed of data in units of one word read from memory cell A, and data is transferred to the host computer through the interface circuit. In this case, data transfer can be performed in units of two words, so that the data transfer speed to the host computer is improved.
  • FIG. 11 is a block diagram showing a third embodiment of a reproducing apparatus and a reproducing method according to the present invention, wherein reference numeral 1 indicates that digital data to be processed by a host computer is recorded,
  • the optical disk recorded by the modulation method and encoding method different from the optical disk in Fig. 1 and Fig. 7, and 23 is the original 8-bit unit for the signal of the different modulation method recorded on the optical disk 1.
  • a data demodulation circuit that demodulates the data to 24 bits is a correction block consisting of data in a plurality of sectors after demodulation, and corrects errors occurring in the block when reading from the optical disc.
  • the PI and PO correction circuits that perform this operation 26 are memory cells C whose access bit width is 8 bits and 32 bits are variably accessible, and 27 controls the access target of memory cell C, and 8 bits. For success, Connect the lower 8 bits of the 32-bit data bus of memory cell C to the 8-bit data bus to be accessed, and connect the 32-bit data bus of memory cell C for 32-bit access.
  • the selectors C and 28 that connect the bus directly to the direct are the memory cell C access selection instructions, read and write switching instructions, and 8-bit and 32-bit access bit width switching instructions.
  • An address generation circuit C, 30 for generating an address is an address decoder C for decoding the generated address to the address of the memory cell C.
  • the same reference numerals as in FIG. 7 denote the same parts, and a description thereof will be omitted.
  • the interface circuit 16 receives an access command from the host computer, the signal recorded on the optical disk 1 is read by the pickup 2, and the sector synchronization detection circuit 14 detects the sector. The top is detected and sent to 23 data demodulation circuits.
  • the data demodulation circuit 23 demodulates the data according to the modulation method recorded on the optical disc 1.
  • FIG. 13 shows an arrangement of data for performing address control, and shows a configuration of a correction block for performing error correction processing.
  • it consists of 13G demodulated sector data, 13H PI correction code for correcting sector data in the row direction, and P ⁇ correction code 13I for correcting sector data in the column direction. Error correction is performed within this correction block unit.
  • the 13G sector data consists of 172 bytes X12 as one unit, and consists of 4 bytes of sector ID, main data 1 to 12 and additional data in the sector data. Is done.
  • the correction block it is arranged in the unit of one sector data.
  • 13A is an 8-bit sector data sequence after synchronization signal detection and data demodulation processing, and 1.3B is a 10-byte 13H PI correction code in the row direction.
  • 13 C indicates a PI correction sequence for performing correction, and 13 C indicates a PO correction sequence for performing correction in the column direction using 16 13 I PO correction codes.
  • 130 is the read direction when transferring the 1 and P 0 corrected sector data 13 G to the host computer.
  • Fig. 12 shows an example of the configuration of memory cell C in Fig. 11, which has four memories 12A, 12B, 12C, and 12D that can be accessed in 8-bit units. By specifying the address in the row and column directions, it is possible to access each memory bank.
  • 12E is a bank switching selector that can select a memory 12A to 12D for 8-bit access according to the bank selection signal.
  • the 12F selector is a selector that switches the access bit width in accordance with the 8 and 32 bit width switching instruction.When 32 bits are accessed, the 8 bit bus of memory 1 is connected as shown in 12H in the figure.
  • the 8-bit buses of memories 2 and 3 are treated as the middle 8 bits, respectively, and the 8-bit bus of memory bank 4 is treated as the least significant 8 bits, for a total of 32 bits.
  • the 8-bit data of the memories 1 to 4 selected by the bank selector 12E is used as the lower 8 bits, and at the time of reading, "0" is added as the upper 24 bits of data.
  • 12 G is an I / O buffer that determines the data transfer direction according to the read / write switching instruction. With such a configuration, the memory cell C is configured, and the access bit width can be accessed in units of 8 bits or 32 bits.
  • the memory access control is executed by the data arrangement method shown in FIG. 13, the access is performed using the memory cell C having the configuration shown in FIG. 12, and the interface circuit is implemented.
  • the manner in which data is transferred to the host computer via the PC will be described with reference to the flowchart of FIG.
  • FIGS. 11 and 14 when a host access instruction from the host computer is received in the interface circuit 16 and the signal reading from the optical disk 1 is started, the signal is output. Beyond the included sector The synchronization signal indicating the head is detected by the 14 sector synchronization detection circuit, demodulated into 8-bit data by the 23 data demodulation circuit, and the sector ID in the demodulated data is detected by the 31 sector ID Performed by circuit.
  • the access instruction of the host computer includes the transfer start sector ID for starting the transfer, and if the requested sector ID and the detected sector ID match, 28 access control circuits are used. Each setting for access to the memory cell C by C is started, and if they do not match, the detection of the match of the sector ID is continued (step 14B).
  • the access control circuit C 28 includes a transfer start sector ID for each control target of the selector C 27, the memory cell C 26, and the address generation circuit C 29 according to the detection of the sector ID match. Generates an instruction to write sector data to memory cell C. Selector C responds to the access selection instruction by the 8-bit data bus from data demodulation circuit 23 and the 32-bit data bus of memory cell C—the lower 8 bits of the evening bus In accordance with the 8-bit / 32-bit switching instruction, memory cell C writes sector data after data demodulation in 8-bit units, so the access bit width is set to 8-bit, A write is selected in accordance with the instruction for switching the address and the write, and the address generation circuit C is set so as to generate the demodulated sector sequence address in accordance with the address sequence selection instruction (step 14C).
  • the demodulated sector data is sent, and the address generation circuit C reads the row address and column address of the demodulated sector data sequence in 8-bit units. Generated every time, the address of memory cell C is decoded by 30 address decoder C, and the sector data is written to memory cell C in 8-bit units (step 14D).
  • the access control circuit C sets a P for each control target. Generates an instruction to read the I correction sequence from memory cell C. Selector C connects PI, P ⁇ 8-bit data to the correction circuit and the lower 8-bit data bus of memory cell C, selects memory cell C for lead, and address generation circuit C for PI The sequence of the correction sequence is set to generate a column address (step 14F). When the memory access selection for PI correction processing is completed, the address generation circuit C generates the address of the PI correction sequence, and the address is decoded to the address of the memory cell C by the address decoder C, 8 bits. The PI correction sequence data is read from memory cell C in units. The error correction that occurred in the sequence is performed on the read PI correction sequence (Step 14G).
  • the access control circuit C When the processing of the PI correction sequence is completed, the access control circuit C generates an instruction for reading the P0 correction sequence from the memory cell C for each control target.
  • the address generation circuit C is set to generate the address of the P0 correction sequence (step 14H), and generates the row and column addresses of the PO correction sequence for each 8-bit unit read and address.
  • the decoder C decodes the address of the memory cell C, and the P0 correction sequence data is read from the memory cell C in 8-bit units. Correction of an error that has occurred in the read P0 correction sequence is performed (step 14I).
  • the access control circuit C When the correction processing of the P0 correction sequence is completed, the access control circuit C generates an instruction for reading the host transfer data sequence from the memory cell C for each control target.
  • the selector C connects the 32-bit bus to the interface circuit 16 and the 32-bit data bus of the memory cell C, and the memory cell C selects the access bit width to 32 bits and generates the end address.
  • Circuit B generates data to be transferred to the host, and generates a host transfer data overnight address of main data 1 to 12 in one sector data as shown in 13G in Fig. 13. (Step 14J), and the row of the host transfer data sequence is set to 2 ⁇
  • step 14 ⁇ If the number of sectors requested to be transferred from the host computer is not enough (step 14L), the process is repeated from step 14C, and if the number of sectors requested is reached, the process ends.
  • the demodulation method for the serial data read from the optical disc 1 and digitized is the same as that for 16 bit clocks transmitted in synchronization with the serial data.
  • serial data is converted from 8-bit parallel data to 8-bit parallel data by the data demodulation circuit, the number of bit clocks indicating the number of serial data transfers and the data transfer from the interface circuit in 32-bit units are performed.
  • the relationship between the number of transfers and the number of transfers is as follows: When a memory with a variable access bit width is used, if the redundancy is set to 100% in consideration of the redundant portion such as an error correction code, the bit clock ( For 16 + 16) data, a data transfer of 32 bits from the memory written in 8 bits is performed at one time, so that it becomes 32: 1, and the redundancy is 0. Case 16: 1 with Relationship That. Therefore, since the redundancy is generally smaller than 100% and larger than 0%, the output transfer frequency F ⁇ is 1 Z 3 2 o F 0 Z 1 Z 1 for the bit clock frequency 1. It becomes 6.
  • the output transfer frequency F0 is 1Z64, F0, and 1Z32 for the bit clock frequency 1.
  • data transfer from the interface circuit or memory If data transfer to the interface circuit is performed in units of 8 bits, transfer of 32 bits of data requires 4 transfers or memory access from the interface circuit. Under the same conditions, the output transfer frequency F 0 becomes 1/128 and F o ⁇ lZ 64 with respect to the bit clock frequency 1, and the data transfer efficiency is significantly reduced.
  • the third embodiment necessary processing is performed on the signal read from the optical disk, and when data is transferred to the host computer via the interface circuit, By doing this in units of 32 bits, the data transfer speed to the host computer is improved.
  • the power consumption of the entire reproducing apparatus including the large-capacity memory cell C necessary for temporarily storing the plurality of correction blocks described above is reduced.
  • FIG. 15 is a block diagram showing a fourth embodiment of the present invention, which is an example applied to a disc recording apparatus.
  • Reference numeral 1 is an optical disc that can record digital data transferred from the host computer. The section sync signal and physical ID are recorded in advance to indicate the position to be recorded on the disc.
  • the optical disc 2 is a pickup that can read and write the modulation signal to the optical disc 1, and the pickup 2 is capable of detecting the physical ID recorded in advance on the optical disc 1 and starts recording the detected ID.
  • 33 is a physical ID detection circuit that detects a match with the physical ID to be corrected
  • 33 is a correction code generation circuit that generates PI and P0 correction codes that constitute one correction block
  • 34 is an optical disk 1
  • 35 is an additional data generation circuit that adds the additional data and sector ID included in one sector data overnight to the main data. Common parts are denoted by the same reference numerals and description thereof is omitted.
  • the method of arranging the transfer data from the host computer, the correction sequence, the data modulation sequence, and the address control method in this embodiment are the same as those of the correction block of FIG. 13 described in the third embodiment.
  • transfer data is allocated to main data 1 to 12 as shown in 13G, sector ID and additional data are added respectively to make up one sector data, and arranged in the direction shown in 13D .
  • a P0 correction code is generated and added to the sequence in the 13C direction with respect to the collected data, and a PI correction code is generated and added to the sequence in the 13B direction. I do.
  • the data read sequence for performing the modulation process is performed in the direction of 13 A.
  • Address control is similarly performed by specifying the 13F low address and 13E column address.
  • the memory access control is executed by the data array method described with reference to FIG. 13, the access is performed in the memory cell C, and the optical disk 1 receives the transfer data from the host computer. The recording will be described with reference to the flowchart of FIG.
  • a recording request instruction from the host computer is received by the interface circuit 16 and the transfer data in units of 32 bits from the host computer is transferred to the interface.
  • the access control circuit C of 28 receives the selector C of 27, the memory cell C of 26, and the address generator of 29 in accordance with the recording request instruction.
  • an instruction is generated to write the transfer data from the in-university-uniform circuit to the memory cell C, and the selector C sends an instruction from the additional data generation circuit 35 according to the access selection instruction.
  • the 32-bit data bus is connected to the 32-bit data bus of memory cell C.
  • Memory cell C is sent in 32-bit units after adding additional data according to the 8-bit / 32-bit switching instruction.
  • the access bit width is set to 32 bits
  • the write is selected according to the read / write switching instruction
  • the address generation circuit C is additional data according to the address series selection instruction.
  • Sector data from the generator is set to generate an evening-sequence address (step 16B).
  • step 16C When the preparation for access to the memory cell C is completed, additional data is added to the transfer data sent to the interface circuit to form one sector data (step 16C).
  • the row address and column address of the series shown in 13D are generated for each 32-bit unit read, and the address is decoded to the address of the memory cell C by the address decoder C of 30.
  • Sector data is written to memory cell C in bit units (step 16D).
  • the access control circuit C reads the P0 correction sequence from the memory cell C for each control target. Generate instructions for loading.
  • the selector C connects the 8-bit data bus to the correction code generation circuit and the lower 8-bit data bus of the memo and recell C, the memory cell C selects the read, and the address generation circuit C is the row and column of the PO correction sequence.
  • the address is set to generate (step 16F).
  • the address generation circuit C When the selection of the memory access for the P0 correction processing is completed, the address generation circuit C generates the address of the P0 correction sequence, and the address decoder C decodes the address of the memory cell C to 8 bits.
  • the P0 correction sequence data is read from the memory cell C in units. Read A P0 correction code is generated for the P0 correction sequence, and the P0 correction code is written to an address corresponding to the area of the P0 correction code in the memory cell C (step 16G).
  • the access control circuit C When the generation and addition of the PO correction code are completed, the access control circuit C generates an instruction for reading the PI correction sequence from the memory cell C for each control target.
  • the address generation circuit C is set to generate the address of the PI correction sequence (Step 16H), and the address of the PI correction sequence and the column address are read every 8-bit unit.
  • the address is decoded to the address of memory cell C by address decoder C, and PI correction sequence data is read from memory cell C in 8-bit units.
  • a PI correction code is generated for the read PI correction sequence, and the PI correction code is written to an address corresponding to the area of the PI correction code in the memory cell C (step 16I).
  • the access control circuit C When the generation and addition of the PI correction code are completed, the access control circuit C generates an instruction for reading the modulated data sequence from the memory cell C for each control target.
  • the selector C connects the 8-bit bus to the data modulation circuit 34 and the lower 8-bit data bus of the memory cell C, and the address generation circuit B transfers the data to the data modulation circuit. It is set so as to generate the address of the data series shown in A (step 16J).
  • step 16K When the preparation of the recording data on the optical disc 1 is completed, the signal is read from the optical disc 1 and the physical ID recorded in advance is detected by the 32 physical ID detecting circuit (step 16K). If the physical ID for starting recording on the optical disc 1 matches the detected physical ID (step 16L), the address control by the address generation circuit C of 29 is started, and the modulation data is output. The row and column addresses of the series are generated for each 8-bit read, and the address decoder C decodes the generated 32-bit start address to the address of the memory cell C and demodulates the data. Circuit 1 6 After data modulation, the data is recorded on optical disc 1 (step 16M). If the number of sectors requested by the host computer is less than the number of sectors (step 16N), the process is repeated from step 16B. If the number of requested sectors has been recorded, the process ends.
  • data when data is recorded on the optical disc 1, data is transferred in units of 32 bits in one transfer to the interface circuit and then recorded on the recording medium. After performing modulation processing on 16-bit data for 8-bit data to be performed, serial data is generated, and the number of transfers represented by 16 operation clocks of the modulation means at that time, or When serial data is recorded on a recording medium in accordance with a signal that is equivalent to 16 transfer counts, 32 bit data transfer per transfer to the interface means is required.
  • the data transfer from the interface circuit to the memory means is performed in units of 16 bits without using the memory having the variable access bit width.
  • the data transfer from the interface circuit to the memory means is performed in units of 16 bits without using the memory having the variable access bit width.
  • two 16-bit memory accesses are required, and in the same manner as above, one memory access requires a serial access to the recording medium.
  • the number of transfer times S i of the full data is 32 2, S i, and 64.
  • the data transferred from the host computer is subjected to encoding processing necessary for recording on the optical disc 1, and when recording, the transferred data is 32 bits.
  • Writing to the memory cell C in units reduces the time required for data transfer, and improves the processing speed for encoding digital signals to the optical disc on which recording is performed.
  • the power consumption of the entire recording apparatus including the large-capacity memory cells C necessary for temporarily storing the generated correction blocks is reduced.
  • the transfer data is written to the memory cell C in units of 32 bits. As a result, the time required for data transfer is reduced, the processing speed for encoding digital signals to the optical disc for recording is improved, the number of memory accesses is reduced, and the entire semiconductor chip is consumed. It leads to power reduction.
  • FIG. 17 is a block diagram showing a fifth embodiment of the reproducing apparatus and the reproducing method according to the present invention, in which the same processing as in the second embodiment described with reference to FIG. 7 is performed.
  • This shows a case where a playback device is configured with one memory cell D.
  • Reference numeral 36 controls memory cell D whose access bit width is 8 bits, I 6 bits, 32 bits and variably accessible memory cells, and 37 controls an object to access memory cell D.
  • the lower 8 bits of the 32-bit data bus of memory cell D and the 8-bit data bus to be accessed are connected directly.
  • memory cell D is connected.
  • the 16-bit data bus to be accessed and the lower 16 bits of the 32-bit data bus are connected to the direct.
  • the 32-bit data bus of memory cell D is directly connected to the direct.
  • Selectors D and 38 are access selection instructions for memory cell D, read and write switching instructions, 8-bit, 16-bit, and 32-bit access bit width switching instructions, and memory cells.
  • a of D Access control circuits D and 39 which generate selection instructions for addressless sequences (demodulation data system, C1, C2 correction system, playback data frame system, PI, P0 correction system, and host transfer system), are address sequences.
  • An address generation circuit D for generating an address for each access sequence in accordance with the selection instruction, and an address decoder D for decoding the generated address to an address of the memory cell D, are shown in FIG.
  • the parts corresponding to are denoted by the same reference numerals, and redundant description is omitted.
  • the interface circuit 16 receives an access command from the host computer, the pickup 2 starts at a position near the disk where data to be transferred to the host computer is recorded.
  • the signal recorded on the optical disk 1 starts to be read, and after the frame synchronization signal is detected by the frame synchronization detection circuit 4, the demodulated data in 8-bit units is output by the EFM demodulation circuit 5. Is demodulated.
  • the access control circuit D 8 has 8 bits (1 symbol) for each of the control targets of the selector 37 of 37, the memory cell D of 36, and the address generation circuit D of 39. Control to write to demodulator memory cell D sent in units.
  • the address control method for accessing the memory cell D is performed by the control method described in FIG. 3 (specifying the row, column address, mouth address, and column address).
  • the address is generated by the address generation circuit D, decoded by the address decoder D to the actual address of the memory cell D, and the demodulated data is written to the memory cell D according to the decoded address.
  • the access control circuit D When the demodulated data that can be transferred to the host computer or for the storage capacity of the memory cell D and the C2 correctable demodulated data is written, the access control circuit D On the other hand, control is performed so that the data sequence for C1 correction in units of 8 bits (one symbol) is read from memory cell D.
  • the access control circuit D sends a data sequence for C2 correction in units of 8 bits (1 symbol) to each control target. Control to read from memory cell D.
  • the access control circuit D reproduces the data to be controlled in units of 16 bits (1 word) for each control target. It is controlled to read the overnight sequence and transferred to the 14 sector synchronization detection circuit.
  • the read playback sequence forms the data in sector units shown in Fig. 9, and detects the sector synchronization signal included in the playback data sequence, and the sector ID recorded in the 2-bit data immediately after the synchronization signal. Is performed by the 31-sector ID detection circuit.
  • the access control circuit D When the detection processing of the sector synchronization signal is completed, the access control circuit D performs an error correction processing for the P correction sequence included in the array of the sector data other than the sector synchronization signal for each control target. Control is performed so that the data sequence for the correction sequence is read from memory cell D.
  • the access control circuit D When the error correction processing for the P correction sequence is completed, the access control circuit D performs error correction processing for the Q correction sequence included in the array of the section data other than the section synchronization signal for each control target. Then, control is performed so that the data sequence for the Q correction sequence is read from memory cell D.
  • the access control circuit D controls each control target so that the data sequence to be transferred to the host computer is read from the memory cell D in units of 32 bits.
  • the access instruction of the host computer includes a transfer start section ID for starting data transfer, and a memory cell! When a sector synchronization signal is detected. ID is detected for the section data stored in (). For the host transfer data series included in the sector for the subsequent sector IDs, including the section where the transfer start sector ID and the detected sector ID match, the memory cell D and other data are read. The data is transferred to the interface circuit 16 in 32-bit (2-word) units, and transferred to the host computer.
  • serial data 14 bits of demodulated data and 3 bits of margin data
  • the relationship between the bit clock that indicates the number of transfers (serial transfer) and the number of transfers when performing the data transfer in units of 32 bits from the interface circuit is determined by the variable access bit width.
  • the output transfer frequency F • is 1 Z34, Fo, and 1 Z17 for a bit clock frequency of 1.
  • the data transfer from the interface circuit is in units of 16 bits at a time, 1 Z68 ⁇ F0 ⁇ 134, and the data transfer from the interface circuit or If the data transfer from the memory means to the interface circuit is performed in units of 8 bits, lZ136 ⁇ Fo, 1/68, and the data transfer efficiency is significantly reduced. .
  • memory access for arranging the demodulated data in an array of 8-bit demodulated data, and C1, C2 correction processing are performed.
  • One memory cell D provides access to the data sequence, access to the sequence for detecting the sector synchronization signal, access to the data sequence for P and Q correction processing, and access to the transfer data sequence to the interface circuit.
  • the control circuit When the memory cell D, the processing circuits required for processing, and the control circuit are provided on the same semiconductor chip, the configuration of the reproducing apparatus shown in FIG. The effect of reducing the power consumption of the entire semiconductor chip is great, and the size of the semiconductor chip can be suppressed, which is advantageous in terms of semiconductor manufacturing costs.
  • the recording medium for storing data is not limited to the optical disc of this embodiment, and the digital signal to be handled is stored in a memory or other means for temporarily storing data.
  • a digital signal processing system configured to store, perform predetermined processing, and output transfer data, for example, a recording / reproducing apparatus for a tape-shaped recording medium, a recording / reproducing apparatus for a magnetic disk recording medium, or a data transfer system; It can also be applied to communication systems, etc., and the storage means such as memory with variable access bit width required for processing in these digital signal processing systems and the peripheral circuits and processing means required for executing predetermined processing are the same.
  • the present invention can also be applied to the case where it is provided on a semiconductor chip.
  • control means for controlling the memory having the variable access bit width may be realized by using a microprocessor programmed to realize the same control function, and the variable access bit may be changed by changing the program.
  • the processing may be performed such that the width can be changed according to the bit width of the digital signal to be processed, and in this case, a predetermined processing including a memory and a microprocessor having a variable access bit width is performed. This is realized by providing the means on the same semiconductor chip.
  • the memory When memory with variable access bit width is provided on the same semiconductor chip, the memory is a dynamic memory that needs to be rewritten at regular time intervals, or a static memory that does not require a rewrite operation. It can be realized by either memory. Further, the configuration of the memory cell used in the first to fifth embodiments is not limited to this embodiment, but may be a memory in which the access bit width can be made variable according to the processing means performing the access. Any configuration is acceptable as long as it is a cell.
  • the configuration of one link which is a unit of the address control in the first embodiment, is not limited to this embodiment, but is recorded in temporary storage means such as a memory, and after performing a predetermined process.
  • a one-bank configuration is adopted to make it easier to access the transfer data.
  • an address control method for accessing a data series necessary for performing each process is described in the embodiment of FIG. This may be performed by specifying the row address, column address, mouth address for column, and column bank address for one bank in one bank unit as described above.
  • the interface circuit for transferring data to and from the host computer in the second, third, fourth, and fifth embodiments is not limited to this embodiment.
  • the access bus width may be 64 bits or more.
  • the memory cell performs data transfer with an access bit width of 64 bits or more between the interface circuit and the memory cell corresponding to each access bit width.
  • a selector for controlling an access target is prepared.
  • the method of detecting a physical ID recorded in advance on the recordable optical disc 1 in the fourth embodiment is not limited to this embodiment, but may be a method for detecting a recording ID in an optical disc. It is also applicable to the recording of optical discs that record objects that can be used as ID substitutes. In this case, ID detection is performed, for example, by measuring a frequency change due to undulation of a track by a physical ID detection circuit, and recognizing the address as an address on an optical disk, and performing processing.
  • the type of the variable access bit width of the memory means used in all the embodiments described above is not limited to this embodiment, but may be different from the data array stored in the memory means. Thus, any number of types may be switched according to the processing means to access so that the means for executing the processing can perform the processing most efficiently.
  • a memory cell necessary for realizing all the embodiments described, a processing circuit, a control circuit, or a microprocessor which executes processing equivalent to the processing circuit and the control circuit by program control is the same semiconductor.
  • the same processing as that of the reproducing device and the recording device can be realized by providing them on the chip.
  • the data read from the optical disk is written in data of one symbol (8 bits) after the data demodulation processing, and the data is reproduced in two symbols (16 bits) in units of one symbol (16 bits).
  • the address control up to reading is configured as a single link in units of multiple symbols, and the port and column addresses in one bank, and the port address and column address in one bank are stored.
  • the address control is facilitated by accessing the data in units of 1 or 2 symbols by specifying.
  • the arrangement of the reproduced data sequence when performing address control is devised, and the address is controlled by arranging the Cl, C2 correction sequence, and demodulation sequence for that. It is easy to transfer two symbols.
  • the access bit width for reading the reproduced data sequence is 16 bits or 32 bits, the reproduced data can be accessed only once.
  • the data can be transferred in 6-bit or 32-bit units, and the data transfer speed to the means for performing interpolation and filter processing on the playback data and the means for interface with the host computer has been improved. From the means to the host computer —The data transfer speed in the evening is also improved. Also, the number of memory accesses required for performing a series of digital signal processing can be reduced.
  • each processing circuit, and the control circuit are provided on the same semiconductor chip, access bits to the memory means necessary for efficient processing are provided. It is configured so that processing can be performed in units of width.
  • the EFM demodulation circuit is configured to output demodulated data in 8-bit units, the output interpolation for 16-bit digital audio playback data, and the filter processing circuit in 16-bit units according to the data unit.
  • the interface circuit that performs data processing and transfers data to and from the host computer is a host combination: 16 bits, 32 bits, or 32 bits depending on the interface bus width with the host interface. Is configured to perform data transfer with memory means with a bus width larger than that.
  • the memory means is customized to enable access according to the type of variable access bit width, and the access bit width is set variably according to the access target Possible memory means are provided on the semiconductor chip.
  • the means necessary for a series of digital signal processing and the memory means customized so that the access bit width can be set variably are realized on the same semiconductor chip, the number of memory accesses is reduced. As a result, the power consumption of the entire semiconductor chip can be reduced, high-speed processing of a series of digital signals can be realized, and the transfer speed of reproduced data output from the semiconductor chip can be improved.
  • the memory means customized to have variable access bit width is composed of dynamic memory, a digital signal processing system requiring large-capacity memory can be implemented on the same semiconductor chip. It can achieve the effects of reducing power consumption, high-speed signal processing, and improving the data transfer speed from the semiconductor chip.

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Abstract

La présente invention concerne des données numériques stockées dans un dispositif de mémoire, selon un arrangement de données prescrit. Lorsqu'on lit une donnée à corriger à cause d'une erreur contenue dans ledit arrangement ou un arrangement de données à reproduire, la commande d'accès au dispositif de mémoire est rendue plus facile, le nombre d'accès au dispositif de mémoire est réduit et une vitesse de transfert de données est accrue réduisant ainsi la consommation de puissance lorsqu'on utilise une puce de semi-conducteur contenant le dispositif de mémoire. La présente invention concerne également le dispositif de mémoire qui peut commuter la largeur de bit d'accès entre (n) bits et (n x m) bits (n et m étant des nombres naturels), un dispositif de commutation en largeur de bus qui peut commuter la largeur de bit d'accès mémoire entre (n) bits et (n x m) bits et un dispositif de gestion qui gère l'accès. Etant donné que le dispositif de commande gère l'accès de sorte que la largeur de bande de bus peut être commutée en largeur de bande de (n x m) bits au moment de la lecture des données à reproduire dans le dispositif de mémoire, on réduit le nombre d'accès et on améliore la vitesse de transfert des données reproduites. Lorsque le dispositif de mémoire peut être changé en largeur de bit d'accès, on fournnit un dispositif nécessaire à l'exécution du traitement sur la même puce de semi-conducteur, le dispositif de mémoire étant adapté de sorte que la largeur de bande de bit d'accès puisse être réglée en fonction de chaque dispositif nécessaire.
PCT/JP1997/000910 1997-03-19 1997-03-19 Dispositif et procede de production d'un signal numerique a l'aide d'une memoire a largeur de bus variable et dispositif et procede d'enregistrement du signal numerique WO1998041987A1 (fr)

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US7278033B2 (en) 2002-03-27 2007-10-02 Nokia Corporation Method and a system for determining the power consumption in connection with an electronic device, and an electronic device
USRE45542E1 (en) 2002-03-27 2015-06-02 Memory Technologies Llc Method and a system for determining the power consumption in connection with an electronic device, and an electronic device

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