WO1998033211A1 - Procede de mise sous boitier de circuits de commande integres - Google Patents

Procede de mise sous boitier de circuits de commande integres Download PDF

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Publication number
WO1998033211A1
WO1998033211A1 PCT/EP1998/000260 EP9800260W WO9833211A1 WO 1998033211 A1 WO1998033211 A1 WO 1998033211A1 EP 9800260 W EP9800260 W EP 9800260W WO 9833211 A1 WO9833211 A1 WO 9833211A1
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WO
WIPO (PCT)
Prior art keywords
main surface
carrier substrate
front main
connection
carrier
Prior art date
Application number
PCT/EP1998/000260
Other languages
German (de)
English (en)
Inventor
Michael Feil
Original Assignee
Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. filed Critical Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Publication of WO1998033211A1 publication Critical patent/WO1998033211A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to a method for packaging integrated circuits (ICs) which enables the production of packaged integrated circuits in chip size (chip size package).
  • ICs integrated circuits
  • Integrated circuits are typically marketed in ceramic or plastic packages.
  • the space requirement of the housing in relation to the chip size is very unfavorable. Therefore, in particular with multi-pole ICs, there are strong efforts to reduce the housing size to the chip size (chip size package, abbreviation: CSP).
  • the finished silicon wafers (silicon wafers) have generally been cut into individual chips in a first step using a saw and then further processed on a chip basis.
  • the further work steps differ depending on the type of housing.
  • the chips When pressing into plastic housings (transfer molds), the chips are attached to a lead frame with an adhesive. The electrical connections from the chip to the carrier frame are made by wire bonding. The parts are then given a plastic coating in an injection press. The final steps are deburring, punching and bending the connecting legs, as well as labeling.
  • the housing When using ceramic housings, the housing is already prefabricated. The chips are usually glued into a recess provided for this purpose. The electrical Contacting is again done by wire bonding. The last step is to solder a housing cover. A hermetically sealed housing is thus achieved
  • Another, hermetically sealed housing is the metal housing.
  • the working steps are similar to the procedure for the ceramic housing.
  • the housing cover is usually welded onto the metal housing.
  • a method for housing integrated circuits which reduces the area requirement of the housing approximately to chip size.
  • a silicon substrate with integrated circuits and pads is first connected to the front of a carrier substrate. After the connection, solder bumps are attached to the back of the carrier substrate and electrical connections are made between the solder bumps and the electrical connections of the integrated circuits through the carrier substrate.
  • US-A-5,535,101 a method for connecting a single chip to a carrier is known.
  • the carrier is preferably larger than the chip.
  • the carrier is also substantially larger than the chip. No full-wafer connection technology is therefore used in either method.
  • the invention has for its object to provide a method for packaging ICs in chip size, which can be carried out without the risk of a reduction in yield.
  • the present invention now relates to a method for housing integrated circuits with the following method steps:
  • - Providing a semiconductor wafer with a plurality of integrated circuits, which has electrical connection areas on a front main surface, and; - Providing a carrier substrate with a front and a rear main surface having the electrical connection surfaces, electrical connection surfaces of the front main surface being electrically conductively connected to electrical connection surfaces of the rear main surface via vias;
  • a completely processed semiconductor substrate with one or more integrated circuits is initially provided.
  • This semiconductor substrate has electrical connection surfaces on a front main surface.
  • the main surface on the front side is to be understood as the side of the semiconductor substrate on which the integrated circuits are located.
  • a carrier substrate is provided which has electrical connection surfaces on its front and rear main surface.
  • the electrical connection surfaces on the front side are already electrically conductively connected to the electrical connection surfaces on the rear side via vias.
  • Vias refer to any type of electrically conductive connection through the carrier substrate.
  • the vias can therefore be direct or indirect, e.g. over metallization levels in the carrier substrate.
  • the two substrates provided, the semiconductor substrate and the carrier substrate, are finally adjusted with respect to one another with their respective front-side main surface in such a way that the connection surfaces which have to be connected lie opposite one another.
  • the front connection surfaces of the semiconductor substrate and of the carrier substrate will therefore generally match each other in mirror image.
  • the two main surfaces on the front are connected to one another, so that there is both a mechanical connection between the semiconductor substrate and the carrier substrate, and also an electrically conductive connection between the mutually aligned connection surfaces.
  • a housing size can be realized which is equal to the chip size. Since the semiconductor substrate and carrier substrate are connected, after both substrates have been processed independently of one another, no further process steps after the connection are necessary, which could reduce the yield.
  • the connection between the semiconductor substrate and the carrier substrate that is to say the mechanical fastening and the electrical connection, can moreover take place in a single work step, as will be described below.
  • the method can also be carried out advantageously at the wafer level. Since a large number of chips can be housed in the wafer network and the process steps can be simplified, this enables a drastic reduction in costs. After the method according to the invention has been carried out, there are thus finished housed components.
  • the method can be carried out with a semiconductor substrate, the electrical connection areas of which have been placed on active areas, so that a further area saving (i.e. more ICs per wafer) and thus cost reduction is achieved.
  • Another advantage is that, due to the freedom in the manufacture of the carrier substrate, different connection grids and pin assignments can be realized on the front and rear of the carrier substrate.
  • FIG. 1 an example of the side view of a unit made from the semiconductor wafer and carrier substrate produced by the method according to the invention
  • Figure 2 the side view of a portion of a unit according to Figure 1, in which
  • Semiconductor wafers and carrier substrates are connected via double-sided metallic bumps and a non-conductive adhesive;
  • FIG. 3 shows the side view of a region of a unit according to FIG. 1, in which the semiconductor wafer and carrier substrate are connected to one another by an anisotropic adhesive;
  • Figure 4a the side view of a portion of a unit according to Figure 1, in which
  • FIG. 4b a top view of an isolated chip from FIG. 4a;
  • FIG. 5 an example of the side view of a region of a carrier substrate, as is used in the method according to the invention.
  • a silicon wafer is used as the semiconductor substrate (1).
  • the further process steps are carried out at the wafer level.
  • a connection of the entire surface of the wafer (1) to the carrier (4) is carried out. This is shown in Figure 1.
  • the front main surface (2) of the semiconductor wafer (1) and the front main surface (5) of the carrier substrate (4) with the respective connection surfaces (3, 7) are adjusted to one another and connected to one another.
  • the connection patterns which are formed by the arrangement of the electrical connection surfaces (3, 7) on the front main surfaces (2, 5) match each other in mirror image.
  • the mechanical fastening and the production of the electrical connections from the wafer to the carrier are achieved simultaneously in one work step.
  • the following options are available for the design of the connecting means.
  • both on the wafer (2) and on the carrier side (5) are reinforced by electrically conductive, usually metallic bumps (bumps 11).
  • An electrically non-conductive adhesive (12) is applied to the entire surface (e.g. by spinning or
  • an anisotropically conductive adhesive (13) is used for the connection.
  • Anisotropically conductive adhesives are filled with metal or metallized plastic balls in such a way that an electrically conductive connection (14) is formed only under pressure in the direction perpendicular to the joint surface.
  • This adhesive is also applied over the entire surface to one or both joining partners. In addition to the methods mentioned under a), this can also be in the form of a laminated on
  • underfill As a rule on the saw, to prevent water or saw dust from entering between the chip and carrier, an underfill on a plastic basis (underfill) must be provided.
  • underfill a very thin epoxy resin is used at the wafer level, which is drawn into the spaces between the wafer and the carrier by capillary forces.
  • This underfilling also serves to compensate for mechanical stresses between the wafer and the carrier. Such stresses arise in particular when using carrier materials that are not adapted to the thermal expansion coefficient of the silicon wafer (e.g. printed circuit boards or flex materials).
  • FIGS. 4a and b A further, very advantageous design of the connecting means is shown in FIGS. 4a and b.
  • the methods known from flip chip technology for producing solder bumps and matching metallizations are also used here.
  • the solder bumps (15) can (as in c)) be applied to the connection surfaces (3, 7) on one or both front main surfaces (2, 5).
  • soldering bumps (15), which are later on a common chip (10) after being separated, are enclosed by a soldering frame (16).
  • the solder frame has roughly the outline of the chip. However, the shape can vary as long as the purpose of the soldering frame to prevent water or saw dust from entering between the chip and the carrier is fulfilled.
  • FIG. 4b shows a top view of an isolated chip (10) with soldering bumps (15) and soldering frame (16).
  • the saw cuts (18) for separating the chips (10) from the wafer (1) are shown in FIG. 4a.
  • the soldering frames can be produced during the processing of the carrier substrate or the silicon wafer in the same process step as the application of the solder bumps (e.g. by screen printing or electroplating). Only a different layout configuration is required. Here, too, the wafer and carrier are connected (as in c) by mutual adjustment and subsequent soldering process at the wafer level.
  • the use of semiconductor wafers or carrier substrates with solder frames has the particular advantage that a hermetically sealed housing is achieved, which is not possible with adhesives.
  • the aforementioned methods advantageously enable mechanical attachment between the wafer and carrier and the electrical connection of the connection surfaces in a single work step.
  • connection from the front (5) to the rear (6) of the carrier is implemented via plated-through holes (9) which were already produced before the connection to the silicon wafer. These can either directly on the connection surfaces (7, 8)
  • connection surfaces should be distributed over the respective main surfaces in particular in case d) for a more uniform distribution of the mechanical stresses. Since today's ICs almost exclusively have an arrangement of the connections on the edges, these must be redistributed beforehand. In cases a) and b) this can also be achieved on the carrier side, since mechanical stresses are already absorbed by the adhesive.
  • the connection patterns on the two carrier sides can, but do not have to be identical. A certain asymmetry in the connection pattern is advantageous for an unambiguous assignment of the connections or a right-sided use of the carrier, as is indicated, for example, in FIG. 4b.
  • the wafer with the connected carrier substrate is finally separated into chips, so that a package the size of a chip is achieved. This can be done by sawing, as already indicated with the saw cuts (18) in FIGS. 1 to 4.
  • connection surfaces (8) of the carrier are provided on their underside (6) with ⁇ -balls (17).
  • ⁇ -balls are metallic bumps with significantly smaller dimensions than ball grid arrays.
  • a suitable choice of the ⁇ -ball metallization can ensure SMD capability ( ⁇ -ball grid array).
  • the metallization can be carried out, for example, from a Sn / Pb solder (as a solder bump) or from a Cu / Ni / Au alloy (as a hard plug contact).
  • FIG. 5 shows an example of a carrier substrate (4).
  • the carrier can for example consist of materials such as Si, glass, ceramics, printed circuit board materials (eg FR4) or flex materials.
  • the openings for the plated-through holes (9) are first created in the carrier. Depending on the carrier material, this can be done using different methods, such as standard drilling, laser drilling, ultrasonic drilling or etching. In the case of conductive substrates, such as Si, the surfaces and drilling walls must be insulated.
  • the metallizations are carried out in standard processes such as electroless deposition, electroplating, Sputtering, vapor deposition or thick film technology applied. This applies to all parts to be metallized, i.e.
  • the vias should be completely filled. Either the holes are so small that they can be completely filled during the metallization, or they have to be closed subsequently, for example with a synthetic resin drop.
  • the plated-through holes (9) are placed next to the connections (15, 17) on both sides. However, it is also conceivable to place both or one of the two connections (15, 17) on the plated-through holes (9).
  • a multi-layer carrier with an internal wiring level multilayer circuit board or ceramic
  • the finished chip can be covered with a plastic film for mechanical protection if necessary. This can be done either before further assembly at component level, or after assembly similar to a "globe-top" (e.g. synthetic resin drops over the chip) in chip-on-board technology. At the same time, this measure in cases a, b and c provides better protection against moisture penetrating into the joint between the Si chip and the carrier.
  • a plastic film for mechanical protection if necessary. This can be done either before further assembly at component level, or after assembly similar to a "globe-top" (e.g. synthetic resin drops over the chip) in chip-on-board technology.
  • this measure in cases a, b and c provides better protection against moisture penetrating into the joint between the Si chip and the carrier.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

L'invention concerne un procédé de mise sous boîtier de circuits de commande intégrés (ICs), qui permet de produire des ICS sous boîtier en format puce (chip size package) et de procéder sur plan de tranche de silicium. Ce procédé se caractérise en ce que dans un premier temps, un substrat à semi-conducteur (1) traité fini et un substrat porteur (4) traité fini sont mis à disposition. Le substrat porteur présente déjà au recto et au verso, des surfaces de connexion transversales. Les deux substrats sont réunis, la fixation mécanique et la connexion électrique intervenant dans une section de travail. Le système global est ensuite séparé en puces individuelles.
PCT/EP1998/000260 1997-01-23 1998-01-19 Procede de mise sous boitier de circuits de commande integres WO1998033211A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE1997102186 DE19702186C2 (de) 1997-01-23 1997-01-23 Verfahren zur Gehäusung von integrierten Schaltkreisen
DE19702186.7 1997-01-23

Publications (1)

Publication Number Publication Date
WO1998033211A1 true WO1998033211A1 (fr) 1998-07-30

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US6251703B1 (en) 1998-12-14 2001-06-26 Ela Medical S.A. CMS coated microelectronic component and its method of manufacture
US6429530B1 (en) * 1998-11-02 2002-08-06 International Business Machines Corporation Miniaturized chip scale ball grid array semiconductor package
US6596964B2 (en) 2001-07-10 2003-07-22 Koninklijke Philips Electronics N.V. Method of attaching a component to a connection support by welding without the addition of material
US6730989B1 (en) 2000-06-16 2004-05-04 Infineon Technologies Ag Semiconductor package and method

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KR20020053809A (ko) * 1999-09-10 2002-07-05 가마이 고로 이방성 도전성 필름 부착 반도체 웨이퍼 및 그 제조 방법
US6388335B1 (en) * 1999-12-14 2002-05-14 Atmel Corporation Integrated circuit package formed at a wafer level
US6281046B1 (en) * 2000-04-25 2001-08-28 Atmel Corporation Method of forming an integrated circuit package at a wafer level
DE10029269B4 (de) * 2000-06-14 2005-10-13 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteiles aus gehäusebildenden Substraten
DE10227342B4 (de) * 2002-06-19 2008-06-05 Qimonda Ag Verfahren zur Verbindung einer integrierten Schaltung mit einem Substrat und entsprechende Schaltungsanordnung

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US6251703B1 (en) 1998-12-14 2001-06-26 Ela Medical S.A. CMS coated microelectronic component and its method of manufacture
US6730989B1 (en) 2000-06-16 2004-05-04 Infineon Technologies Ag Semiconductor package and method
US6596964B2 (en) 2001-07-10 2003-07-22 Koninklijke Philips Electronics N.V. Method of attaching a component to a connection support by welding without the addition of material

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