WO1998005036A1 - Dispositif a semi-conducteur - Google Patents
Dispositif a semi-conducteur Download PDFInfo
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- WO1998005036A1 WO1998005036A1 PCT/JP1997/002564 JP9702564W WO9805036A1 WO 1998005036 A1 WO1998005036 A1 WO 1998005036A1 JP 9702564 W JP9702564 W JP 9702564W WO 9805036 A1 WO9805036 A1 WO 9805036A1
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/16—Modifications for eliminating interference voltages or currents
- H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
- H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Definitions
- the present invention relates to a semiconductor device having an output buffer.
- the present invention relates to a semiconductor device that generates less noise when the output buffer circuit operates, and an I ⁇ semiconductor device in which the operation of other circuit units is less affected by the noise.
- This output buffer circuit includes an output terminal 0 UT 1 where output data appears, a P-channel MOS transistor (hereinafter, referred to as PM 0 S), which is an output transistor, 12 9 and N channel M 0 S transistor (hereinafter referred to as NMOS) 130.
- PM 0 S P-channel MOS transistor
- NMOS N channel M 0 S transistor
- An output transistor control circuit that controls the operation of the PMOS 129 and the NMOS 130 is connected to the gate electrodes of the PMOS 129 and the NMOS 130.
- This output / J transistor control [Port 1 is an inverter (hereinafter referred to as I NV.) 1 2 0, 1 2 2, 1 2 5 and 1 3 3 and non-logical This is called a NAND circuit.) It is composed of 123 and 127.
- the output transistor and the inverter in the output transistor control circuit and the NAND circuit are connected as follows.
- the input terminal / of the inverter 120 is supplied with the read command signal IN 1, and the output terminal is connected to the node 121.
- INV 1 2 2 input A node 121 is connected to the input terminal, and a node 110 is connected to the output terminal.
- the input terminal of INV 13 3 is connected to the output signal node 13 1 to which the signal corresponding to the data to be output from the output terminal OUT 1 is input, and the node 13 2 is connected to the output terminal. It is connected.
- the input terminal of the NAND circuit 123 is connected to the node 110 and the node 132, and the output terminal is connected to the node 124.
- the input terminal of NAND 127 is connected to node 110 and node 131, and the output terminal is connected to node 128.
- the input terminal of INV 125 is connected to node 124, and the output terminal is connected to node 126.
- the source of PMOS 129 is connected to ⁇
- the power supply with a high potential level is generally called VCC.
- the gate of PMOS 129 is connected to node 128, and the drain is connected to output terminal 0UT1.
- the source of the NMOS 130 is connected to the ground GN having a potential level of 0 V, for example, through the parasitic reactance L1 of the power supply line (parasitic reactance in the path from the package terminal to the wiring in the chip).
- D power supplies with low potential levels are commonly referred to as VSS or GND).
- the gate of NMOS 130 is connected to node 126, and the drain is connected to the output terminal; TOU ⁇ 1.
- the input terminal 110 of the inverter 110 has a plurality of external human input signals such as ZRAS (Row Address Strobe Signal), / CAS (Column Address Strobe Signal), / OE (Output Enable Signal), and / WE
- the control circuit CONT1 that outputs the read command IN1 corresponding to the state of (Write Enable Signal) is connected.
- This control circuit is in the state of ZWE (Write Enable Signal) power; "H” level, and the state of ZRAS (Row Address Strobe Signal), ZCAS (Column Address Strobe Signal), / OE (Output Enable Signal) is " Outputs the read command signal IN 1 that changes from “L” level to “H” level when it changes from “H” level to “L” level.
- a capacitor C 1 (typically 100 pF) is connected between the output terminal OUT 1 and ground GND. This capacitor C1 is provided outside the chip.
- a resistor R1 is connected between the output terminal OUT1 and the reference voltage supply that supplies the reference voltage ffiV2 (typically 4 V).
- the resistor Rl and the reference power fr: supply unit are also provided outside the chip.
- a resistor R1, a capacitor C1, and a reference voltage supply unit provided outside the chip are necessary for operating the output cover and the sofa path.
- the read command signal IN 1 changes from “H” level to “L” level
- nodes 1 2 8 "PM 0 S 1 29 is turned off because of the level.
- the potential level of the output terminal 0 UT 1 gradually decreases and finally reaches the “Hi-Z” level (the potential level of the output terminal 0 UT 1 becomes “Hi”. — Since you return to the 7 'level, this action is hereinafter referred to as outgoing set.)
- the read command signal I N1 changes from “H” level to “L” level.
- the read command signal I N1 level transitions from the “ ⁇ ” * level to the “L” level, the node 126 level changes to “L” level, so ⁇ ⁇ 0 S130 turns off.
- the NMOS 130 turns off, the potential level of the output terminal O UT 1 gradually rises and finally reaches the “Hi-Z” level (the potential level of the output terminal 0 UT 1 becomes “Hi”. Since this is K at the —Z ”level, this operation is hereinafter referred to as output reset.)
- the output terminal OUT 1 outputs an “H” level (lower diagram in Fig. 3)
- the output line resets the parasitic reactance L 2 of the power supply line. Due to the effect, the potential level applied to the power supply VCC wiring inside the chip; the potential level instantaneously rises to VCC or higher.
- the control circuit CONT 1 that outputs the read command signal IN 1 outputs multiple external input signals (ZRAS, / CAS , ⁇ 0 ⁇ , / WE) may be recognized as m.
- ZRAS, / CAS , ⁇ 0 ⁇ , / WE multiple external input signals
- the present invention has been made to solve the above-described problems, and a typical one thereof is a control for outputting a read command signal for a first period in response to a plurality of control signals.
- FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
- FIG. 2 is a circuit diagram showing a conventional output buffer circuit.
- FIG. 3 is a timing chart illustrating the operation of the circuit of FIG.
- FIG. 4 is a timing chart illustrating the operation of the circuit of FIG.
- FIG. 5 is a circuit diagram showing a second embodiment of the present invention.
- FIG. 6 is a timing chart for explaining the operation of the circuit of FIG.
- FIG. 7 is a timing chart for explaining the operation of the circuit of FIG.
- FIG. 8 is a circuit diagram showing a third embodiment of the present invention.
- FIG. 9 is a timing chart for explaining the operation of the circuit of FIG.
- FIG. 10 is a circuit diagram showing a fourth embodiment of the present invention.
- FIG. 11 is a timing chart for explaining the operation of the circuit of FIG.
- FIG. 12 is a timing chart for explaining the operation of the circuit shown in FIG.
- FIG. 13 is a circuit diagram showing a fifth embodiment of the present invention.
- FIG. 14 is a timing chart illustrating the operation of the circuit of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- the semiconductor device of the present invention includes a control circuit C 0 N T 1 and an output buffer circuit.
- This output buffer circuit includes a drive unit including two output transistors, an output terminal, and an output transistor control circuit that controls a state of the drive unit.
- the drive section includes an output terminal 0 UT 1 where output data appears, a P-channel MOS transistor (hereinafter referred to as PM 0 S) as an output transistor, and an N-channel MOS transistor (hereinafter referred to as PM 0 S). This is referred to as NMOS.
- PM 0 S P-channel MOS transistor
- NMOS N-channel MOS transistor
- Connected to the gate electrodes of PMOS 129 and NMOS 130 Is connected to an output transistor control circuit for controlling the operation of the PMOS 129 and the NMOS 130.
- This output transistor control circuit is composed of inverters (hereinafter referred to as I NV) 125 and 133 and non-logical product (hereinafter referred to as NAND circuit) 1 2 3 and 1 2 7 It is composed of The inverter and the NAND circuit in the output transistor and output transistor control circuits are connected as follows.
- the input terminal of INV 13 3 is connected to the output node 13 1 from which a data signal corresponding to the data to be output by the output terminal OUT 1 is connected, and the output terminal is connected to the node 1 3 2 Is connected.
- the input terminals of the NAD circuit 123 are connected to the nodes 110 and 132, and the output terminals are connected to the nodes 124.
- An input terminal of A N ⁇ 127 is connected to nodes 110 and 131, and an output terminal is connected to node 128.
- a node 124 is connected to the input terminal of I ⁇ V125, and a node 126 is connected to the output terminal.
- an enable signal for turning the output transistor control circuit into an enable state / disable state is obtained.
- the source of PMOS129 has a potential level of, for example, 3.3 V via the parasitic reactance L2 of the power supply line (parasitic reactance that can form a path from the package terminal to the wiring inside the chip).
- the power supply is connected to VCC (power supplies with high potential levels are commonly referred to as VCC).
- VCC power supplies with high potential levels are commonly referred to as VCC.
- ⁇ ⁇ 0 The gate of S129 is connected to node 128, and the drain is connected to output terminal OUT1.
- the source of NMOS 130 is connected to the ground GND (low potential, for example) with a potential level of 0 V via the parasitic reactance L 1 of the power supply line (parasitic reactance that can form a path from the package terminal to the wiring inside the chip). Resources with levels are generally VSS or Is called GND. ) It is connected to the.
- the gate of the NMOS 130 is connected to the node 126, and the drain is connected to the output terminal OUT1.
- the control circuit CONT 1 has multiple external input signals: / RAS (Row Address Strobe Signal), / CAS (Column Address Strobe Signal), / 0E (Output Enable Signal), and / WE (Write Enable Signal). Outputs the read command signal IN 1 corresponding to.
- control circuit CON 1 is in a state of WE (Write Enable Signal) power; "H” level, ZRA S (Row Address Strobe Signal), / CA S (Column Address Strobe Signal), / OE
- WE Write Enable Signal
- ZRA S Row Address Strobe Signal
- CA S Cold Address Strobe Signal
- OE OE
- a capacitor C1 (usually 100 pF) is connected between the output terminal OUT1 and the ground GND. This capacitor C1 is provided outside the chip. Furthermore, a resistor R1 is connected between the output terminal / -0UT1 and a reference ⁇ power supply for supplying a reference voltage V2 (usually 4V). This resistor R 1 and the reference voltage supply are also provided outside the chip. A resistor R1, a capacitor C1, and a reference voltage supply unit provided outside the chip are necessary for operating this output buffer circuit.
- the semiconductor device of the present invention includes an enable signal generation circuit including an NV 120 ′, a NAND circuit 141, and a delay circuit (hereinafter, referred to as a DELAY) 1. have.
- DE LAY 1 composed of an even number of inverters has an input terminal connected to nodes 12 ⁇ and an output terminal connected to node 140 1. Has a power terminal.
- the NAND circuit 141 has two input terminals to which the node 12 1 ′ and the node 140 are connected, and an output terminal to which the node 110 is connected.
- FIG. 4 is a timing chart comparing the operation of the circuit shown in FIG. 1 with the operation of the circuit shown in FIG.
- the output buffer circuit outputs the “L” level
- control circuit C 0 NT 1 ′ the external input ⁇ 1 , ZRAS, / CAS and OE all transition from “H” level to “L” level, and ZWE is “H” level. Detect that there is.
- the control circuit C 0 NT 1 outputs a pulsed read command signal IN 1 to the input terminal of the inverter I NV 12 0 ′.
- a data # 4 output circuit (not shown) outputs an “L” level data signal to the node 13 1.
- the delay 1 delays the signal given to the node 1 2 1 ′ for a predetermined time. Therefore, the node 140 changes to the “L” level after changing to the “L” level, and then changes to the “L” level after a predetermined time has elapsed.
- the NAND circuit 141 outputs an "H" level to the node 110 regardless of the level of the node 121 '. In other words, although the read command signal IN 1 'changes from the “H” level to the “L” level, the node 110 maintains the “H” level. 0 is on continuously for a sufficient time.
- NMOS 130 If NMOS 130 is turned on continuously for a sufficient time, it eventually becomes VDS-0 V, and the potential level of the output terminal 0UT1 is completely at the GND level. At this time, almost no current flows between the source and the drain of the NM0S130 because there is no potential difference. In this state. Even if the NMOS 130 is turned off, the temporal change rate of the current is almost zero. After a lapse of a predetermined time, the node 140 changes from the “L” level to the “H” level, which is either the node 121 ′ or the “H”, and the node 140 force; Since it is "H", the NAND circuit 141 outputs "[NO '" to the node 110.
- the pulse-like read command signal I N1 turns off the NMOS 130 before the potential level of the output terminal OUT 1 reaches the GND level.
- the enable signal having a width longer than the pulse width of the read command signal IN1 ( (A signal given to node 110).
- the NM 0 S 130 can be turned on for a longer time, so that the VDS of the source and drain of NM 0 S 130 can be brought close to 0 V, and the NMO S 1 The current flowing when 30 is turned off can be made smaller.
- the control circuit C 0 NT 1 that outputs the read command signal IN 1; It is possible to prevent erroneous recognition of the signal (/ RAS, / CAS, / OE, / WE) potential level. Therefore, the appearance of the "H" level read command signal IN1 in a period other than the read period can be prevented.
- the first embodiment of the present invention is to reduce noise generated when an output buffer circuit operates.
- the second and subsequent embodiments described below even if noise occurs when the output buffer circuit operates, Z and other circuits malfunction so as not to affect other circuits.
- the circuit was devised so as not to make it.
- a data read operation is executed again by a noise (output reset noise) generated when the output buffer circuit operates.
- a noise output reset noise
- FIG. 5 is a circuit diagram showing a second embodiment of the present invention, and the same elements as those in FIG. 2 are denoted by the same reference numerals.
- the semiconductor device of the present invention includes a control circuit CONT1, an output buffer circuit, and a data-in buffer circuit.
- the output terminal OUT 1 will be described as the input / output terminal OUT ⁇ .
- the data-in buffer circuit is connected to the input / output terminal 0 U T 1. More specifically, an input / output terminal OUT1 is connected to the input terminal of the INV201, and a node 210 is connected to the output terminal.
- the source of PMOS 202 is connected to node 210 power; the gate is connected to node 211 power; and the drain is connected to node 211 power.
- the source of NM0S203 is connected to node 211; the gate is connected to node 211; the drain is connected to node 210.
- the node 211 is connected to the human terminal of the INV 205, and the node 220 is connected to the output terminal. Node 220 is connected to the input terminal of INV206, and node 211 is connected to the output terminal.
- the input terminal of the inverter 216 is connected to a control circuit CONT 1 which outputs a plurality of external human input signals / RAS, / CAS, / OE, and a write data latch signal I2 corresponding to the state of WE. Have been.
- This control circuit C 0 NT 1 is in the state of ZWE power; “H” level.
- a read instruction signal IN1 that transitions from “L” level to “H” level.
- / 0 E is in "H” level state, and / RAS, / CAS, and / WE state is “H”.
- Outputs the write data latch signal IN2 which transitions from “H” level to "L” level when transitioning from "level” to "same” level.
- Node 217 is connected to the output terminal of INV 216.
- the input terminal of 204 has node 17 ', and the output terminal has node 2 1 2 Each is connected.
- the difference between the output buffer circuit of FIG. 5 and FIG. 1 is the configuration of the output transistor control circuit that controls the state of the drive unit.
- the configuration of this different part will be described below.
- the input terminal of the NAND circuit 25 1 is connected to the input terminal IN 1 and the node 26 5; the output terminal is connected to the node 26 1.
- the input terminal of INV252 is connected to node 261, and the output terminal is connected to node 262.
- the input terminal of DELAY2 composed of an odd number of stages of inverters is connected to the node 262 power; the output terminal is connected to the node 263 power ';
- Non-OR hereinafter abbreviated as NOR
- the input terminal of 25 3 is connected to node 26 2 and node 26 3 power; the output terminal is connected to node 26 4 power; .
- the input terminal of the INV254 is connected to the node 264, and the output terminal is connected to the node 265iS.
- the node 265 is connected to the node 265 and the output terminal is connected to the node 266 and the output terminal is connected to the node 266 and the output terminal.
- a node 2666 is connected to the input terminal of INV122 ', and a node 110 is connected to the output terminal.
- FIG. 6 is a timing chart for explaining a cycle in which a write operation is performed immediately after a read operation.
- FIG. 7 shows a read instruction signal I N
- control circuit C 0 N T 1 force ' is an external input signal / R A S, / C A
- the control circuit C 0 NT 1 outputs a pulse-like read command signal IN 1 to the NAND circuit 25 1 and the NAND circuit 255.
- a data signal output circuit (not shown) outputs a “L” or “H” level data signal to the node 13 1.
- the data force is L ".
- the node 262 changes from “L” level to "H” level.
- the node 263 changes from the “L” level to the “H” level after changing from the "L” level to the "H” level, and then changes from the "H” level to the "L” level after a predetermined period of time.
- the N0R circuit 25 3 is at the “H” level because of the node 26 2 or the node 26 3 level; therefore, regardless of the change of the read command signal IN 1, the node 2 64 “L” is output. Output level. Therefore, the level of node 2 G5 does not change.
- the node 2 63 becomes L level, so that the NOR circuit 25 3 outputs a signal of “H” level to the node 2 64.
- the output of the NAND circuit 255 does not change because the node 256 is at the “I” level. In other words, even if an output reset noise occurs, the "H" level read command signal IN1 is generated, and if it occurs again, the read operation is prohibited from being performed again.
- the write operation is to be performed, but if the read operation is performed again at this point, the data is read out to the input / output terminal 0 UT 1 and the input / output terminal 0 UT 1 It will collide with the obtained write data.
- the write data latch f, j-IN2 forces the transition from the “H” level to the “L” level.
- the transfer gates PMO S 202 and NMO S 203 are both turned off, and a latch operation is performed. Therefore, write data correctly. Means that it cannot be embedded.
- the read operation is prohibited during a certain period after the original read operation, so that even if the write operation is performed after the read operation, the read data and the write data do not collide. No.
- a data write operation is erroneously executed due to noise (output reset noise) generated when an output buffer circuit operates. It is related to a circuit that prevents such a situation.
- FIG. 8 is a circuit diagram showing a third embodiment of the present invention, and the same elements as those in FIG. 2 are denoted by the same reference numerals. The description of the same elements as those in FIG. 2 is omitted.
- the semiconductor device of the present invention includes a control circuit CNT1, an output buffer circuit, and a data buffer circuit.
- the semiconductor device of the present invention is particularly characterized by a data buffer circuit.
- FIG. 8 (a) will be described.
- the input terminal of N 0 R 341 is connected to IN 2 and the node 340, and the output terminal is connected to node 342 ′.
- Node 342 power is connected to the human input terminal of I NV 204, and node 212 power 'is connected to the output terminal.
- the source of PMOS 202 is connected to node 210; the gate is connected to node 342; and the drain is connected to node 211.
- the source of NMOS 203 is connected to node 211, the gate is connected to node 211, and the drain is connected to node 210; P TJP 4
- FIG. 8 (b) or FIG. 8 (c) described below is connected to the node 340 in FIG. 8 (a). Have been.
- the input terminal of NOR 351 is connected to IN 1 and the node 350 power; and the output terminal is connected to node 340 '; .
- the DELAY 3 composed of odd-numbered inverters is connected to IN 1 power to the human input terminal and 350 power to the output terminal.
- the NAND 355 human input terminal has a node 353 and a node 354 output '; and the output terminal has a node 340 output'. ;, Each connected.
- the input terminal of the INV 352 is connected to the input terminal 1 N 1, and the output terminal is connected to the node 353 ′.
- the input terminal of the DEL AY4 composed of even-numbered inverters is connected to the input terminal IN; and the output terminal is connected to the node 354 terminal.
- FIG. 9 is a timing chart illustrating a cycle in which a read operation is performed immediately after a read operation.
- control circuit CONT 1 detects that all of the external input signals ZRAS, / CAS, and / OE transition from “H” level to “L” level, and that ZWE is at “H” level. .
- the control circuit CON T1 outputs a read command signal IN 1 in the form of a pulse to the NAND circuits 25 1 and 255.
- a data signal output circuit (not shown) outputs an “L” or “H” level data signal to the node 13 1 .
- the data force is "L”. If changes to the "H" level from the read command signal IN 1 month I Roh 'level changes from Node 1 1 0 force 5 "L" level to the "H” level.
- the NAND circuit 1 2 3 When the node 1 1 0 changes to the “H” level, the NAND circuit 1 2 3 outputs an “L” level to the node 1 24. When the node 1 2 4 changes to the “L” level, NM 0 S130 turns on and the output terminal 0UT1 gradually drops to the ground level.
- the NOR circuit 351 outputs the “H” level to the node 340. This is because the level of the node 350 is maintained at the “L” level until a predetermined interval after the read command signal IN 1 changes to the “L” level due to the influence of the delay 3. It is.
- the signal changes from the “L” level to the “H” level.
- a signal that maintains this "H” level is output to the node 340 from the falling edge until a predetermined period has elapsed.
- a signal obtained by NOR processing this signal and the write data latch signal I N2 is used as a control signal for a transfer gate.
- the write data latch signal IN 2 is changed to “L” level; the node 340 is at the “H” level for a predetermined period, so that the node 342 is also for a predetermined period.
- the L "level is maintained. Therefore, the data D is not latched because the PMOs 202 and the NMOs 203 constituting the transfer gate maintain the on state.
- the write data latch signal IN 2 force the force that changes to the “L” level; Since the node 340 is at the “H” level for a predetermined period, the node 342 also maintains the “L” level for a predetermined period. Is done. Therefore, since the PMOS 202 and the NMOS 203 forming the transfer gate maintain the on state, the data / D is not latched.
- the control circuit C0NT1 is controlled by the write data latch due to the influence of the output reset noise. Even if the signal IN 2 is output, the latch of write data is prohibited in a certain section, so that erroneous writing of data can be prevented.
- latching of write data is inhibited from the beginning of the data reading period, so that not only output reset noise but also data reset noise is reduced. Occurs early in reading TJP9 2564
- a data write operation is erroneously performed due to noise (output reset noise) generated when an output buffer circuit operates. It relates to a circuit that prevents execution.
- FIG. 10 shows a light control circuit of the present invention.
- the input terminals of INV401 are ZRAS, / CAS, and / WE all power; when "H” changes to "L”, write instruction changes from “L” to "H”
- the node to which the signal is applied is connected to the node 460, and the output terminal is connected to the node 421.
- the NAND 402 and the NAND 403 are connected to the frit.
- a flip-flop circuit is formed, and the human power terminal of NAND 402 is connected to node 421 and node 431 power; the output terminal is connected to node 422 power;
- the input terminals of the NAND 403 are connected to the nodes 425 and 422, respectively, and the output terminal is connected to the node 431.
- Each node consists of an odd number of inverters.
- the input terminal of the DELAY 1 is connected to the node 422, and the output terminal is connected to the node 425.
- the input terminal of the NOR circuit 442 is connected to IN 1 and the node 441, and the output terminal is connected to the node 440.
- a delay 6 composed of even-numbered inverters is connected between one input terminal and the other input terminal of the NOR circuit 442.
- the input terminal of the NAND 405 is connected to the node 440 and the node 422, and the output terminal is connected to the node 424.
- the input terminal of NV406 is connected to the node 424, and the output terminal is connected to the node 426. Have been.
- the input terminal of the NAND 407 is connected to the node 426 and the column address selection signal CL 1, and the output terminal is connected to the node 427.
- the input terminal of INV409 is connected to the node 427, and the output terminal is connected to the node 430.
- the input terminal of the NV408 is connected to the node 428 for writing data; the output terminal is connected to the node 429 for the node.
- the source of the NMOS 410 is connected to the bit line (BL), the gate is connected to the node 430, and the drain is connected to the node 428.
- the source of NMOS 411 is connected to the bit line (/ BL), the gate is connected to node 430, and the drain is connected to node 429.
- the NOR link 442 When the read command signal IN 1 becomes “H”, the NOR link 442 outputs the “L” level to the node 440.
- the DELAY 6 outputs the read command signal IN 1; After the change, the “H” level is output after the elapse of a predetermined period, so that the NOR circuit 442 changes to the read command signal IN 1 ′; Maintain the same level until it changes to "L”.
- the read operation may cause output reset noise as described above.
- the control circuit CON T 1 is not Is "H” / WE is determined to be “L”.
- the control circuit CONT 1 outputs a “H” level write command signal to the node 460.
- DELAY 5 After a predetermined time, DELAY 5 outputs an “L” level to node 425. When node 4 25 goes to “L” level, node 4 3 1 force goes to “H” level. When the node 4 31 1 is at the “H” level, a level corresponding to the write command signal appears on the node 4 22.
- the read command signal I1 changes from “H” to “L” at the rising edge of "H” from “L”, and after this change, maintains the "L” level until a predetermined period elapses.
- Signal is output to the node 440. Therefore, even if the node is at the “H” level, the node 440 is at the “L” level, so the node is at the “L” level. 4 2 4 does not go to “L” level If node 4 2 4 does not go to “L” level, the transistors 4 10 and 4 1 1 do not turn on, so data cannot be written to the bit line. Absent.
- the signal becomes the low level, and the control circuit C 0 NT 1 outputs a “H” level write command signal to the node 460.
- node 4 60 or "H" level is reached, node 4 2 2 force ';"H” level as described above.
- the node 424 is at the "I" level.
- the NAND circuit 407 outputs an “L” level signal to the node 427, so that the transistors 4 1 0, 4 1 1 turns on. Therefore, the data force applied to node 428 is written to bit line BL, ZBL.
- the fifth embodiment of the present invention prevents the column address buffer circuit from malfunctioning due to noise (output reset noise) generated when the output buffer circuit operates in a semiconductor memory device, particularly, I) RAM. Circuit.
- the semiconductor device of the present invention is particularly characterized by a column address buffer circuit.
- FIG. 13 (a) will be described.
- the input terminal of the INV 501 is connected to an address pad (Ai PAD), and the output terminal is connected to the node 501 '.
- the source of the PMOS 502 is connected to the node 510; the gate is connected to the node 513; the drain is connected to the node 511;
- the source of NMO ⁇ 0 3 is connected to node 5 11 force; the gate is connected to node 5 12 force; and the drain is connected to node 5 10 force.
- the input terminal of the NAND circuit 513 is supplied with a node address latch signal that transitions from “H” to “L” when both ZRAS and CAS transition from “H” to “L”.
- the node 540 is connected, and the node 532 is connected to the output terminal.
- the input terminal of INV504 is connected to a node 532 ', and the output terminal is connected to a node 512'.
- the input terminal of the INV505 is connected to the node 511; the output terminal is connected to the node 500 '.
- the input terminal of INV506 is connected to a node 52 ', and the output terminal is connected to node 51'.
- the node 540 in FIG. 13 (a) is added to the node 13 in FIG. 13 (b) or FIG. 13 (c) described below. Circuit is connected.
- the input terminals of N0R542 are IN1 and the node 541, and the output terminal? Are connected to each other;
- a node 543 is connected to the input terminal of the INV 544, and a node 540 is connected to the output terminal.
- the input terminal of DELAY7 which is composed of odd-numbered inverters, is connected to the input terminal of IN1; the output terminal is connected to node 541 of the terminal.
- the input terminal of N 0 R 551 has IN 1 and a node 550 force; and the output terminal has a node 540 force '; It is connected.
- the output signal is composed of an even number of inverters of the human power signal.
- the input terminal of DELAY8 is connected to the input terminal IN1, and the output terminal is connected to the node terminal 550.
- FIG. 14 is a timing chart illustrating a cycle in which a write operation is performed immediately after a read operation.
- the control circuit CONT 1 and the external input signals ZRAS, / CAS, and OE all transition from the "H" level to the "L” level, and / WE is at the "H” level. Detect that.
- the control circuit CONT 1 outputs a pulsed read command signal IN 1.
- control circuit C0NT1 outputs a "L" level column address latch signal to the node 500.
- the NAND circuit 531 When the node 500 goes to the “L” level, the NAND circuit 531 outputs an “L” level signal to the node 532 regardless of the level of the node 540. Node 5 3 2 force; When the level becomes “L”, the transfer gate composed of PMO S 502 and NMO S 503 is turned off. The input address ⁇ is latched.
- the data read operation is executed as described above based on the latched address ⁇ .
- the read command signal IN 1 changes from the “H” level to the “L” level.
- the read command signal IN 1 changes from the “H” level to the “L” level, and the parentheses are used.
- a signal that maintains this “L” level is output to the node 540 until a predetermined period has elapsed from the falling edge.
- a signal obtained by subjecting this signal and the column address latch signal to NAND processing is used as a transfer gate control signal. Therefore, the write column address latch signal changes to the "H” level, and the node 540 is at the "L" level for a predetermined period, so that the node 5332 also maintains the "H” level for a predetermined period. Is done. Therefore, the PM0S502 and NM0S503 that constitute the transfer gate maintain the off state, so that the column address Y is not taken in.
- the N 0 R circuit 55 1 when the read command signal IN 1 is at the “H” level, the N 0 R circuit 55 1 outputs “L” to the node 5 40. "Output level. This is because the level of node 550 changes to the read command signal IN 1 H level due to the effect of DE LAY 8. This is because the "H” level is maintained until after a predetermined period has elapsed.
- the read command signal IN 1 at the rising edge of the read command signal IN 1 from the “L” level to the “H” level, the read command signal IN 1 changes from the “H” level to the “L” level, The ⁇ sign that maintains this "L” level is output to node 540 until after the period of. Furthermore, a signal obtained by performing a NAND process on this signal and the column address latch signal is used as a control signal for the transfer gate.
- the control circuit C 0 NT 1 is not affected by the output reset noise. Even if a "H" level column address latch signal is output, fetching of the column address signal is prohibited in a certain section, so that erroneous data writing can be prevented.
- the output reset reset is performed to inhibit the capture of the column address latch signal from the beginning of the data write period. It is effective not only for noise but also for malfunctions caused by noise that occurs at the beginning of data reading. Industrial applicability
- the semiconductor device of the present invention is useful for a semiconductor device in which a large change occurs in the potentials applied to the power supply VCC wiring and the GND wiring (noise is generated). is there.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Logic Circuits (AREA)
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69728850T DE69728850T2 (de) | 1996-07-26 | 1997-07-24 | Halbleiteranordnung |
EP97933006A EP0855719B1 (en) | 1996-07-26 | 1997-07-24 | Semiconductor device |
US09/043,151 US6201743B1 (en) | 1996-07-26 | 1997-07-24 | Semiconductor device having delay circuit for receiving read instruction signal |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8/197150 | 1996-07-26 | ||
JP19715096 | 1996-07-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998005036A1 true WO1998005036A1 (fr) | 1998-02-05 |
Family
ID=16369605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1997/002564 WO1998005036A1 (fr) | 1996-07-26 | 1997-07-24 | Dispositif a semi-conducteur |
Country Status (6)
Country | Link |
---|---|
US (1) | US6201743B1 (ja) |
EP (1) | EP0855719B1 (ja) |
KR (1) | KR100399110B1 (ja) |
DE (1) | DE69728850T2 (ja) |
TW (1) | TW328661B (ja) |
WO (1) | WO1998005036A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020084872A1 (ja) * | 2018-10-24 | 2020-04-30 | ソニーセミコンダクタソリューションズ株式会社 | 半導体回路および半導体システム |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3425890B2 (ja) * | 1999-04-08 | 2003-07-14 | Necエレクトロニクス株式会社 | バッファ回路 |
US6784647B2 (en) * | 2002-07-15 | 2004-08-31 | Intel Corporation | Method and apparatus for operating a voltage regulator based on operation of a timer |
KR100666484B1 (ko) * | 2005-02-04 | 2007-01-09 | 삼성전자주식회사 | 반도체 메모리 장치의 입출력 회로 및 입출력 방법 |
US7714618B2 (en) * | 2007-12-13 | 2010-05-11 | Macronix International Co. Ltd | Output driver circuit with output preset circuit and controlling method thereof having lower power consumption |
US7948269B1 (en) * | 2009-01-20 | 2011-05-24 | Xilinx, Inc. | System and method for open drain/open collector structures in an integrated circuit |
JP5509123B2 (ja) * | 2011-03-01 | 2014-06-04 | ルネサスエレクトロニクス株式会社 | 半導体装置及びデータ取込方法 |
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JPS6352513A (ja) * | 1986-08-22 | 1988-03-05 | Hitachi Micro Comput Eng Ltd | 半導体集積回路 |
JPH04214290A (ja) * | 1990-12-12 | 1992-08-05 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH0574174A (ja) * | 1991-09-13 | 1993-03-26 | Seiko Epson Corp | 半導体記憶装置 |
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JPS5634186A (en) * | 1979-08-29 | 1981-04-06 | Hitachi Ltd | Bipolar memory circuit |
JPS60115092A (ja) * | 1983-11-28 | 1985-06-21 | Nec Corp | 半導体記憶回路 |
JPS6353513A (ja) | 1986-08-25 | 1988-03-07 | Hitachi Ltd | 光偏向装置 |
JPH0474386A (ja) * | 1990-07-17 | 1992-03-09 | Hitachi Ltd | 半導体記憶装置 |
JPH0562467A (ja) * | 1991-09-05 | 1993-03-12 | Hitachi Ltd | センスアンプ駆動回路 |
KR950012019B1 (ko) * | 1992-10-02 | 1995-10-13 | 삼성전자주식회사 | 반도체메모리장치의 데이타출력버퍼 |
JPH07192470A (ja) * | 1993-03-08 | 1995-07-28 | Nec Ic Microcomput Syst Ltd | 半導体メモリの出力回路 |
US5488581A (en) * | 1993-10-28 | 1996-01-30 | Fujitsu Limited | Semiconductor memory device |
JPH07182864A (ja) | 1993-12-21 | 1995-07-21 | Mitsubishi Electric Corp | 半導体記憶装置 |
US5585744A (en) * | 1995-10-13 | 1996-12-17 | Cirrus Logic, Inc. | Circuits systems and methods for reducing power loss during transfer of data across a conductive line |
KR100206922B1 (ko) * | 1996-07-22 | 1999-07-01 | 구본준 | 라이트 제어회로 |
-
1997
- 1997-07-19 TW TW086110243A patent/TW328661B/zh active
- 1997-07-24 KR KR10-1998-0701867A patent/KR100399110B1/ko not_active IP Right Cessation
- 1997-07-24 EP EP97933006A patent/EP0855719B1/en not_active Expired - Lifetime
- 1997-07-24 WO PCT/JP1997/002564 patent/WO1998005036A1/ja active IP Right Grant
- 1997-07-24 US US09/043,151 patent/US6201743B1/en not_active Expired - Fee Related
- 1997-07-24 DE DE69728850T patent/DE69728850T2/de not_active Expired - Fee Related
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Publication number | Priority date | Publication date | Assignee | Title |
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JPS6352513A (ja) * | 1986-08-22 | 1988-03-05 | Hitachi Micro Comput Eng Ltd | 半導体集積回路 |
JPH04214290A (ja) * | 1990-12-12 | 1992-08-05 | Mitsubishi Electric Corp | 半導体記憶装置 |
JPH0574174A (ja) * | 1991-09-13 | 1993-03-26 | Seiko Epson Corp | 半導体記憶装置 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020084872A1 (ja) * | 2018-10-24 | 2020-04-30 | ソニーセミコンダクタソリューションズ株式会社 | 半導体回路および半導体システム |
JPWO2020084872A1 (ja) * | 2018-10-24 | 2021-10-07 | ソニーセミコンダクタソリューションズ株式会社 | 半導体回路および半導体システム |
US11411561B2 (en) | 2018-10-24 | 2022-08-09 | Sony Semiconductor Solutions Corporation | Semiconductor circuit and semiconductor system |
JP7422083B2 (ja) | 2018-10-24 | 2024-01-25 | ソニーセミコンダクタソリューションズ株式会社 | 半導体回路および半導体システム |
Also Published As
Publication number | Publication date |
---|---|
EP0855719B1 (en) | 2004-04-28 |
EP0855719A1 (en) | 1998-07-29 |
DE69728850T2 (de) | 2005-04-21 |
DE69728850D1 (de) | 2004-06-03 |
US6201743B1 (en) | 2001-03-13 |
KR100399110B1 (ko) | 2003-12-31 |
KR19990044616A (ko) | 1999-06-25 |
TW328661B (en) | 1998-03-21 |
EP0855719A4 (en) | 1998-10-28 |
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