WO1998004075A1 - Materiel et systeme de communication - Google Patents

Materiel et systeme de communication Download PDF

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Publication number
WO1998004075A1
WO1998004075A1 PCT/JP1996/002042 JP9602042W WO9804075A1 WO 1998004075 A1 WO1998004075 A1 WO 1998004075A1 JP 9602042 W JP9602042 W JP 9602042W WO 9804075 A1 WO9804075 A1 WO 9804075A1
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WO
WIPO (PCT)
Prior art keywords
signal
digital information
information
communication device
output
Prior art date
Application number
PCT/JP1996/002042
Other languages
English (en)
Japanese (ja)
Inventor
Takashi Shiba
Minoru Moteki
Akitsuna Yuhara
Hitoshi Yanagihara
Yasuhiro Ohta
Original Assignee
Hitachi, Ltd.
Hitachi Media Electronics Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Media Electronics Co., Ltd. filed Critical Hitachi, Ltd.
Priority to JP1998506770A priority Critical patent/JP3769301B6/ja
Priority to PCT/JP1996/002042 priority patent/WO1998004075A1/fr
Publication of WO1998004075A1 publication Critical patent/WO1998004075A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/707—Spread spectrum techniques using direct sequence modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
    • H04L27/2278—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using correlation techniques, e.g. for spread spectrum signals

Definitions

  • the present invention relates to a communication device and a communication system using a phase modulation method.
  • An object of the present invention is to solve the above-mentioned problem and to provide a communication system capable of improving noise immunity even when a key code length is short (including a case where spread spectrum is not performed). It is in the thing.
  • the purpose of the above is to use a digital information sequence that associates binary digital information with 1 and 1 1 as b (j), where j is an integer, and that the transmitting side has n (n is 3 or more) partial sequences.
  • the multiplied outputs are transmitted sequentially or directly or modulated, and the receiving side directly or demodulates the received signal according to the above, and then the n This is achieved by successively multiplying the signals corresponding to the fractional sequences to reproduce the digital information sequence corresponding to the original 1 and 1 and then reproducing the digital information from the information.
  • the signal (T is (n ⁇ 1)) T (n is 2 or more) before T and the current This is achieved by multiplying all of the signals, and then squaring the signal to reproduce the signal synchronization signal.
  • FIG. 1 is a system block diagram of a communication device according to a first embodiment of the present invention
  • FIG. 2 is an explanatory diagram of a conventional DPSK modulation method.
  • FIG. 3 is a block diagram of a part of the receiving side according to a second embodiment of the present invention.
  • FIG. 4 is a block diagram of a part on the transmitting side according to a second embodiment of the present invention.
  • FIG. 5 is a block diagram of a part of the receiving side according to a third embodiment of the present invention.
  • FIG. 6 is a block diagram of a part of the receiving side according to a fourth embodiment of the present invention.
  • FIG. 7 is a block diagram of a part of a receiving side according to a fifth embodiment of the present invention.
  • FIG. 8 is a block diagram of a part of the receiving side according to a sixth embodiment of the present invention.
  • FIG. 9 is a block diagram of a part of the receiving side according to a seventh embodiment of the present invention.
  • FIG. 10 is a schematic diagram of a surface acoustic wave matching filter according to a first embodiment of the present invention.
  • FIG. 11 is a schematic diagram of a surface acoustic wave matching filter according to an eighth embodiment of the present invention.
  • Fig. 12 shows the output signal waveform of the matched filter.
  • Fig. 13 shows the signal waveform after conventional delay detection.
  • FIG. 14 is a signal waveform after four-stage multiplication detection of the present invention.
  • Figure 15 shows the output signal waveform of the matched filter.
  • Fig. 16 shows the signal waveform after conventional delay detection.
  • FIG. 17 is a signal waveform after four-stage multiplication detection according to the present invention.
  • FIG. 18 is a system block diagram of the communication device according to the ninth embodiment of the present invention
  • FIG. 19 is a system block diagram of the communication device according to the tenth embodiment of the present invention.
  • FIG. 20 is a system block diagram of the communication device according to the eleventh embodiment of the present invention.
  • FIG. 21 is a system block diagram of a communication device according to a 12th embodiment of the present invention.
  • FIG. 22 is a schematic diagram of a convolver used in the communication device of the 12th embodiment of the present invention.
  • FIG. 23 is a system block diagram of a communication device according to a thirteenth embodiment of the present invention.
  • FIG. 24 is an explanatory diagram of a digital operation device used in the communication device of the thirteenth embodiment of the present invention.
  • FIG. 25 is a wireless LAN communication system using the communication device of the present invention.
  • FIG. 1 shows an example of a spread spectrum communication apparatus using the present invention, using a system block.
  • digital information corresponding to basebands 1 and 1 1 is input from the transmitting terminal 1, and digital information corresponding to 1 and 1 1 generated from the pseudo noise (PN) code generator 2.
  • the information (here, for example, 1 corresponds to 0-1 power of the digital information and 1) is multiplied by the mixer 3.
  • the same function can be realized by using a digital processing circuit using a shift register and a half adder.
  • the digital information for transmission is multiplied by the ⁇ -stage multiplying circuit 4 which is a characteristic part of the present invention, by multiplying the information before 1 by ( ⁇ 1) bits and the current information, respectively. can get.
  • the ⁇ -stage multiplying circuit 4 which is a characteristic part of the present invention, by multiplying the information before 1 by ( ⁇ 1) bits and the current information, respectively. can get.
  • n-stage multiplication circuit 4 has four stages in this embodiment, and is constituted by a three-stage shift register 5 and a multiplier 6. This circuit can perform the same processing using the half adder as described above.
  • the signal output from the n-stage multiplication circuit 4 is multiplied by a carrier 8 generated by an oscillator 7 by a mixer 8, modulated into a high-frequency band, then amplified by an amplifier 9, and output from an antenna 10. You.
  • the received modulated signal input from the antenna 10 is amplified by the amplifier 11 and converted into a matched signal by the surface acoustic wave matched filter 12 corresponding to the PN code on the output side.
  • an n-stage multiplication detection circuit 13 (four stages in this case), is used to multiply the information before 1 to (n ⁇ 1) bits and the current information, respectively.
  • the information cycle is ⁇
  • the delay line 1, 2 ⁇ delay line 15, 2 ⁇ ⁇ delay line 15, and 3 ⁇ ⁇ delay line 16 are 1 to 3 bits before
  • the mixer 17 multiplies each signal by the current signal. Since the demodulated detection signal obtained is a signal obtained by detecting a matched signal, the pulse width is narrow. Therefore, the signal is converted into a digital signal having an appropriate pulse width ratio by a square wave output circuit 18 such as a comparator and output from an output terminal 19.
  • FIG. 2 shows a conventional DPSK (Differentia1PhasesSehiftKeying) system.
  • A is the original digital information
  • (b) is the spread signal spread by the PN code (here, 5 bits)
  • (c) is the transmission / reception and modulation signal multiplied by the carrier.
  • the digital signal corresponds to 0 when there is no phase change of the signal and 1 when there is a phase change.
  • D shows the detection and demodulation method of the receiver.
  • a feature of the DPSK method is that no special oscillation circuit is required on the demodulation side, and a demodulated signal can be obtained from terminal 20 using only 1T delay line 21 and mixer 22.
  • FIG. 3 shows a part of a second embodiment of the present invention.
  • an n-stage multiplication circuit and an n-stage multiplication detection circuit which are characteristic portions of the present invention, have six stages.
  • Fig. 3 shows the inside of the n-stage multiplication detection circuit 13; 1T delay line 23, 2T delay line 24, 3T delay line 25, 4T delay line 26, 5T delay
  • the output of line 27 is multiplied by the current signal by mixer 28 to obtain an output detection signal.
  • FIG. 4 shows the inside of the n-stage multiplication circuit 4, and a transmission digital signal is obtained by a 5-stage shift register 29 and a mixer 30.
  • the equivalent SZN of the receiving device is further improved, the communication reliability is improved, and the communication distance is increased. Can be planned.
  • FIG. 5 shows an n-stage multiplication detection circuit of the communication device of the third embodiment.
  • the number of stages in this embodiment is four, similar to that of the first embodiment.
  • an n-stage multiplication detection circuit 13 has delay lines 31 with a delay time of 1 T, delay lines with 2 T and a delay line with 3 T and 3 T
  • the signal before 1 to 3 bits is obtained by the delay line 33 of FIG. 1, first, a multiplied signal of the 0T and 1T signals is formed by the mixer 34, and 2 ⁇ is obtained by the mixer 35. , 3 ⁇ to form a multiplied signal. Next, each signal is multiplied by the mixer 36 to obtain an output detection signal.
  • each signal is multiplied at a time, but it is actually difficult to form such a circuit. Therefore, in the present embodiment, each signal output is multiplied by two, and finally, the output is multiplied. According to this embodiment, even when it is difficult to multiply ⁇ signals as in the first embodiment, ⁇ multiplication outputs can be obtained.
  • FIG. 6 shows an ⁇ -stage multiplication detection circuit of the communication device of the fourth embodiment.
  • the number of stages in this embodiment is four, similar to that of the third embodiment, delay lines 37, 38, and 39 with a delay time of 1 mm are cascaded inside the ⁇ -stage multiplication detection circuit 13 Then, the signal before 1 to 3 bits is obtained, and first, the current signal is multiplied by the output of the delay line 37 of the first stage by the mixer 40, and the signal is also multiplied by the delay line 38 of the second stage. The output of the third-stage delay line 39 is multiplied by the mixer 41, and finally, the output is multiplied by the mixer 42.
  • a delay line having a long delay time for example, 3 T
  • only a 1 T delay line may be used, so that the circuit can be downsized. . (In general, the longer the delay line, the larger the delay line.)
  • FIG. 7 shows an n-stage multiplication detection circuit of the communication device of the fifth embodiment.
  • the internal processing of the n-stage multiplication detection circuit 13 includes the signal output of the delay line 43 with a delay time of 1 T and the current signal. Is multiplied by a mixer 44, and the signal is multiplied by the output of a delay line 45 having a delay time of 2 T by a mixer 46 to obtain an output detection demodulated signal.
  • three mixers were required.However, according to this embodiment, only two mixers need be used, so that the circuit can be reduced in size and cost. is there.
  • FIG. 8 shows a part of a spread spectrum communication apparatus according to the sixth embodiment.
  • ⁇ FIG. 8 shows a demodulation detection section of a receiver, and a detection circuit section 49 has a 1T delay line 4.
  • the conventional DPSK differential detection method using a conventional DPSK method and a mixer 48 is used.
  • the detected signal passes through a low-pass filter 50, and a carrier component is removed.
  • a narrow synchronous signal 52 having the same polarity code is obtained by the mixer 51.
  • this synchronization signal 52 as a comparison synchronization signal for the square wave output comparator 53, the effective SZN can be improved by picking up only the narrow matching signal part as the comparator output.
  • a sine wave was used as the synchronizing signal.
  • the pulse width is narrower than that, and the effective SZN can be further improved.
  • FIG. 9 shows a part of the spread spectrum communication apparatus according to the seventh embodiment.
  • ⁇ FIG. 9 shows a demodulation detection unit of the receiver, and the same parts as in FIG. Numbered.
  • the detection circuit section 49 uses a conventional DPSK delay detection method.
  • the detected signal passes through the low-pass filter 50, the carrier component is removed, and is input to the square wave output comparator 53.
  • a part of the remaining signal is multiplied by a mixer 55 with a signal passing through a 2T delay line 54 and a signal not passing through the delay line 54 according to the flow of a solid line 58 to suppress noise components.
  • the comparator After squaring and passing through the low-pass filter 57, it is input to the comparator as a comparison synchronization signal 52.
  • the synchronization signal is raised to the fourth power with a different delay time from the original signal, so that the noise component is suppressed and the synchronization can be maintained more.
  • FIG. 10 schematically shows the surface acoustic wave matched filter 12 used in the first embodiment.
  • an input interdigital electrode 61 and an output encoding electrode 62 are arranged on a surface acoustic wave substrate 60.
  • the PN code matches the change in the polarity of the encoding electrode
  • a sharp peak-shaped matching signal is output from the output terminal 64.
  • the use of the surface acoustic wave matched filter of the present embodiment has a feature that the detection circuit does not require a synchronization circuit, the high-speed synchronization can be obtained, and the detection signal can be obtained with a low current.
  • FIG. 11 schematically shows a surface acoustic wave matched filter according to an eighth embodiment.
  • the same parts as those in FIG. 10 are given the same numbers.
  • the surface acoustic wave substrate 60 often uses a crystal having a low temperature coefficient in order to suppress a delay time variation due to a temperature variation in the encoding electrode section.
  • the electromechanical coupling coefficient of the crystal substrate is small, the impedance of the interdigital transducer increases, and the mismatch loss increases.
  • the piezoelectric thin film 6 5 high coupling coefficient was deposited only on the input interdigital electrode portion lowers the sag shaped electrode 6 1 of impedance enter, thereby suppressing mismatch loss c
  • this embodiment it is possible to obtain a matched filter that is resistant to temperature fluctuation and has low loss.
  • FIGS. 12 to 17 show a comparison between a conventional signal waveform and the signal waveform of the present invention in order to show the effectiveness of the present invention.
  • a communication method a spread spectrum communication method is taken as an example.
  • Fig. 12 shows a signal level of 19.1.14 dBm (peak value of power per 1 MHz) and a noise level of 19.1 dBm.
  • FIG. 13 is a conventional delay detection waveform under the same conditions
  • FIG. 14 is an output signal of the four-stage detection circuit of the present invention.
  • a noise component is observed, but in the method of the present invention, almost no noise component is observed.
  • Fig. 15 shows the signal level of 94.0 dBm (peak value of power per 1 MHz) and the noise level.
  • FIG. 16 is a conventional delay detection waveform under the same conditions
  • FIG. 17 is an output signal of the four-stage detection circuit of the present invention.
  • the noise component is sufficiently small and the signal can be discriminated.
  • the signal synchronization is clearly shown, and can be used as a synchronization signal for comparators.
  • FIG. 18 is a block diagram of a communication device according to a ninth embodiment of the present invention.
  • the same parts as those in FIG. 1 of the first embodiment are denoted by the same reference numerals.
  • the modulated signal received from the antenna 10 is directly input to the matched filter 12.
  • the carrier from the oscillator 66 is once multiplied by the mixer 67 to generate the intermediate signal. It is converted to a frequency (IF) signal and input at the matched fill.
  • IF frequency
  • This embodiment is effective when the frequency of the RF signal is high (for example, 2.4 GHz band) and it is difficult to operate the SAW matched filter 27, the surface acoustic wave delay line 28, the mixer 29, and the like. .
  • FIG. 19 is a block diagram of a communication apparatus according to a tenth embodiment of the present invention.
  • the first embodiment is an example of a spread spectrum communication system, but the present embodiment relates to direct modulation of the BPSK system.
  • the digital signal input from the input terminal 68 is directly input to the n-stage multiplication circuit 4.
  • the signal output from the n-stage multiplication circuit 4 is multiplied by a carrier generated by an oscillator 69 by a mixer 70, modulated into a high frequency band, then amplified by an amplifier 71, and then amplified by an antenna 72. Is output.
  • the reception modulation signal input from the antenna 72 is amplified by the amplifier 73, and a high SZN demodulation detection signal is obtained by the n-stage multiplication detection circuit 13.
  • the demodulated detection signal obtained has a wide pulse width.
  • the signal is converted into a digital signal having an appropriate pulse width ratio by the waveform shaping circuit 74 and output from the output terminal 75.
  • the present embodiment relates to direct modulation of the BPSK scheme.
  • the present invention can be applied to schemes other than the spread spectrum communication scheme.
  • FIG. 20 is a block diagram of the eleventh embodiment of the present invention.
  • the same parts as those in FIG. 19 of the tenth embodiment are denoted by the same reference numerals.
  • This embodiment relates to the direct modulation of the BPSK system, as in the tenth embodiment.
  • the modulated signal received from the antenna 72 was directly input to the n-stage multiplication detection circuit 13.
  • the carrier from the oscillator 76 and the mixer The signal is multiplied by 7 and converted into an intermediate frequency (IF) signal, which is input to an n-stage multiplication detection circuit 13.
  • IF intermediate frequency
  • This embodiment is effective when the frequency of the RF signal is high (for example, in the 2.4 GHz band) and it is difficult to operate a delay line, a mixer, and the like.
  • FIG. 21 is a block diagram of a 12th embodiment of the present invention.
  • the same parts as in FIG. 1 of the first embodiment are denoted by the same reference numerals.
  • the modulated signal received from the antenna 10 is input to the matched filter 12, but in the present embodiment, the modulated signal is input to the convolver 78.
  • the digital signal of the PN code generator 79 is modulated in the convolver 78 by the carrier of the oscillator 80 and the mixer 81, and convolved with the input signal from the antenna.
  • the SAW matched filter since the SAW matched filter is used, it is difficult to change the PN code.
  • Fig. 22 schematically shows the structure of a convolver using surface acoustic waves.
  • An input signal is input from the input terminal 82, a reference signal is input to the input terminal 83, and a convolution output is output from the output terminal 84.
  • a surface acoustic wave substrate 85 and input IDTs 86 and 87 are arranged inside the convolver, and a convolution output is obtained in the nonlinear interaction area 88 by spatial integration of the two input signals. Is received.
  • FIG. 23 is a block diagram of a thirteenth embodiment of the present invention.
  • the same parts as in FIG. 1 of the first embodiment are denoted by the same reference numerals.
  • the modulated signal received from the antenna 10 is input to the matched filter 12 and a matched signal is obtained by analog signal processing.
  • the received signal is converted into a digital signal, and thereafter, the digital arithmetic unit 89 demodulates the information signal.
  • FIG. 24 shows the processing contents of the digital arithmetic unit 89.
  • the digitized spread signal is input to the input terminal 90, and the arithmetic processing unit performs correlation processing with the PN code as needed, and outputs a digital signal from the output terminal 91 when the correlation output exceeds a certain level. Is output.
  • This embodiment is effective in reducing the cost of the circuit when the information speed is relatively low.
  • FIG. 25 shows a communication system using the present invention.
  • a communication device of this system is used for a LAN.
  • the communication devices 96 and 97 are connected to the LAN cable 92, and the communication devices 9 and 94 are connected to each terminal 93 and 94. 5, 9 and 8 are connected.
  • the communication devices 101 and 102 are connected to the terminals 99 and 100, respectively, and the terminals can communicate freely (without passing through a wired system). If this embodiment is used, each terminal does not need to be connected to the RAN cable, so that the terminal can be moved freely (rate).
  • ADVANTAGE OF THE INVENTION it becomes possible to raise noise immunity performance, it becomes possible to improve the reliability of a communication apparatus, and to expand a communication distance, and to implement

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

On décrit un matériel et un système de communication dans lesquels on peut améliorer l'immunité au bruit, même dans le cas d'une longueur courte de code d'identification (y compris dans le cas où ne s'effectue pas une diffusion de spectre). Une série d'informations numériques contenant des informations binaires composées de 1 et -1 est attribuée à b(j), j étant un nombre entier. Du côté émetteur, la valeur de sortie de multiplication de n séries partielles (n valant 3 ou plus), est émise de façon sérielle, soit directement, soit après avoir été modulées, tandis que du côté récepteur, les signaux reçus sont démodulés s'ils sont modulés, et les signaux correspondant auxdites séries partielles sont multipliés de façon sérielle, afin de reproduire les séries d'informations numériques correspondant aux valeurs originales de 1 et -1. En outre, les informations numériques sont reproduites à partir de ces informations. Des moyens de reproduction synchrone, placés du côté récepteur d'un système de communication par diffusion de spectre, multiplie par le présent signal tous les signaux à partir du moment T jusqu'au moment T(n-1), T représentant l'intervalle binaire d'informations et n valant deux ou davantage, et le signal produit est multiplié par lui-même afin de reproduire le signal de synchronisation.
PCT/JP1996/002042 1996-07-22 1996-07-22 Materiel et systeme de communication WO1998004075A1 (fr)

Priority Applications (2)

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JP1998506770A JP3769301B6 (ja) 1996-07-22 通信装置および通信システム
PCT/JP1996/002042 WO1998004075A1 (fr) 1996-07-22 1996-07-22 Materiel et systeme de communication

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PCT/JP1996/002042 WO1998004075A1 (fr) 1996-07-22 1996-07-22 Materiel et systeme de communication

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164509A (ja) * 1986-12-26 1988-07-07 Nippon Telegr & Teleph Corp <Ntt> 遅延検波回路
JPH0468737A (ja) * 1990-07-05 1992-03-04 Sekiyu Kodan 差動位相変調通信方式用復調器
JPH0637833A (ja) * 1992-07-15 1994-02-10 Uniden Corp ディジタル信号検出回路
JPH07336406A (ja) * 1994-06-03 1995-12-22 Fujitsu Ltd 多重遅延検波復調装置
JPH08125579A (ja) * 1994-10-20 1996-05-17 Fujitsu General Ltd スペクトラム拡散通信方式

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63164509A (ja) * 1986-12-26 1988-07-07 Nippon Telegr & Teleph Corp <Ntt> 遅延検波回路
JPH0468737A (ja) * 1990-07-05 1992-03-04 Sekiyu Kodan 差動位相変調通信方式用復調器
JPH0637833A (ja) * 1992-07-15 1994-02-10 Uniden Corp ディジタル信号検出回路
JPH07336406A (ja) * 1994-06-03 1995-12-22 Fujitsu Ltd 多重遅延検波復調装置
JPH08125579A (ja) * 1994-10-20 1996-05-17 Fujitsu General Ltd スペクトラム拡散通信方式

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