Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
  • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
  • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
  • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

Definitions

• the invention relates to an integrated circuit.
• ESD protection structures are mostly field oxide transistors which are arranged between the connection pads and the supply potentials of the circuit. It is the task of the ESD protection structures to discharge the resulting charges harmlessly via their discharge paths when ESD occurs. In the case of a field oxide transistor as an ESD protective structure, for example, its channel forms the discharge path.
• the object of the invention is to provide an integrated circuit which has improved ESD protection.
• the invention is based on the knowledge that two adjacent doped regions of the same conductivity type, between which there is an insulating region, which are each connected to a connection pad of the integrated circuit and which form a parasitic field-effect transistor, that is to say which are not provided by circuit technology , are particularly at risk from ESD. If the doped regions are of different conductivity types, they can form a corresponding parasitic diode, which is also endangered by ESD.
• the invention is explained in more detail below with reference to the drawing:
• Figures 1 and 2 show details of exemplary embodiments of the invention in cross-sectional representations.
• Figure 3 shows an exemplary embodiment in a circuit diagram.
• two doped regions 2 adjacent to one another in a lateral direction are arranged on the surface of a substrate 3, between which there is an insulating region 1.
• LOCOS Local Oxidation of Silicon
• the doped regions 2 and the insulating region 1 form a parasitic semiconductor element Tpar, in this case a parasitic transistor.
• the doped regions 2 are of the same conductivity type, in the present exemplary embodiment they are n-doped. In other embodiments of the invention, however, they can both be p-doped. However, the doping concentration and the type of dopant can be in the doped regions
• the doped regions 2 are also located in an epitaxial layer, for example, instead of in the substrate 3.
• LDD regions are drain regions that have a lower doping concentration at their edges than in their interior.
• the substrate 3 is of the opposite conductivity type to that of the doped regions 2, in this case, therefore, p-doped.
• the two doped regions 2 are of different conductivity types, so that the para-semi conductor element Tpar is a parasitic diode.
• the invention is also applicable to such structures.
• the insulating region 1 projects into the substrate 3 in a trench-like manner (trench insulation).
• the insulating region 1 can be realized as a combination of the LOCOS region shown in FIG. 1 and the trench insulation.
• the left doped region 2 in FIG. 2 is realized as an n + diffusion in an n well, the right doped region as an LDD region.
• Such parasitic transistors Tpar are present, for example, where the doped regions 2 are drain or source regions of two different, adjacent transistors, which are provided in terms of circuitry, that is to say are not parasitic.
• one of the doped regions 2 can also be e.g. be a guard ring.
• FIG. 3 shows in a rough circuit diagram using an exemplary embodiment of the invention, of which the parasitic transistor according to FIG. 1 or FIG. 2 can be designed, that the doped regions 2 are each connected to a connection pad 4 of the integrated circuit.
• One of the connection pads 4 is in turn connected to a connection pin 5 of the integrated circuit.
• Such a connection is usually established by so-called bond wires.
• the connection pins 5 are external connections of the integrated circuit.
• the other connection pad 4 is not connected to any connection pin 5.
• E ⁇ can represent a measuring point, for example, which can be contacted by means of a measuring tip.
• Such connection pads 4, like the connection pads 4 connected to connection pins 5, are endangered by ESD while measurements are being carried out.
• both connection pads 4 can be connected to one connection pin 5, or none of the two.
• FIG. 3 also shows an ESD protection structure TESD in the form of a field oxide transistor, which, with its channel path (this is an unloading path), between one of the connection pads 4 or the corresponding doped region 2 and a supply potential VSS of the integrated circuit, in this case ground , is switched. Its gate is also connected to the connection pad 4.
• an ESD protection structure TESD can also be provided in both doped regions 2.
• all connecting pins 5 of an integrated circuit are provided with at least one ESD protection structure TESD, which can be connected to different supply potentials, for example dimensions and potential VDD. It is also known to provide an ESD protection structure TESD between two connection pads 4, which are connected to connection pins 5. The latter is particularly the case when these two connecting pins 5 are supply potential connections.
• the length L of the insulating region 1 in the lateral direction is greater than or equal to the length of the longest discharge path of the ESD protective structures TESD connected to the connection pads 4.
• the ESD resistance of the parasitic transistor Tpar is increased, since its ohmic resistance increases with the length L of the isolating region 1.
• the dimensioning of the parasitic transistor tpar depends on that of the ESD protection structures TESD. Since these are already designed for a high ESD strength, a high ESD strength of the parasitic transistor Tpar is also achieved in the manner described. Experiments have shown that a particularly high ESD strength of the parasitic transistor Tpar is achieved when the length L of the insulating region 1 is at least equal to 1.5 times the length of the longest discharge path of the ESD protection structures TESD.
• the channel width of an ESD protection structure TESD in the form of a field oxide transistor is generally much larger than that of other structures, such as that of the parasitic transistors Tpar. With the same current flow through such an ESD protection structure TESD and such a parasitic transistor Tpar, a much lower current density results in the former case.
• the para ⁇ itarian transistor Tpar becomes more resistive than the ESD protection structures TESD, ⁇ o that in the event of an ESD-related overvoltage of the same level, the discharge current via the para ⁇ itarian transistor Tpar is less ⁇ t al ⁇ tr via the ESD protection a lower current density results, ⁇ o that the ESD resistance of the para ⁇ itär Tran ⁇ i ⁇ tor ⁇ Tpar is increased.

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• Semiconductor Integrated Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Priority Applications (5)

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Cited By (1)

Citations (3)

• 1996
  • 1996-06-11 TW TW085107004A patent/TW308733B/zh not_active IP Right Cessation
  • 1996-07-11 WO PCT/DE1996/001258 patent/WO1997004484A1/de not_active Ceased
  • 1996-07-11 DE DE59608801T patent/DE59608801D1/de not_active Expired - Lifetime
  • 1996-07-11 KR KR1019980700272A patent/KR100308074B1/ko not_active Expired - Lifetime
  • 1996-07-11 JP JP50615297A patent/JP4006023B2/ja not_active Expired - Lifetime
  • 1996-07-11 EP EP96923832A patent/EP0839389B1/de not_active Expired - Lifetime

Patent Citations (3)

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