WO1997002604A1 - Dispositif a semiconducteur et son procede de fabrication - Google Patents

Dispositif a semiconducteur et son procede de fabrication Download PDF

Info

Publication number
WO1997002604A1
WO1997002604A1 PCT/JP1996/001792 JP9601792W WO9702604A1 WO 1997002604 A1 WO1997002604 A1 WO 1997002604A1 JP 9601792 W JP9601792 W JP 9601792W WO 9702604 A1 WO9702604 A1 WO 9702604A1
Authority
WO
WIPO (PCT)
Prior art keywords
region
layer
source region
conductivity type
channel region
Prior art date
Application number
PCT/JP1996/001792
Other languages
English (en)
Japanese (ja)
Inventor
Masahiro Yoshimatsu
Original Assignee
Nkk Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nkk Corporation filed Critical Nkk Corporation
Publication of WO1997002604A1 publication Critical patent/WO1997002604A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]

Definitions

  • the present invention relates to a semiconductor device having a pMOS-TFT structure and a method for manufacturing the same.
  • pMOS-TFT In large-capacity SRAMs, TFT-loaded memory cells have been proposed for the purpose of stabilizing the operation of one memory cell.
  • pMOS-TFT is used as a load.
  • a pMOS-TFT uses an n-type second polysilicon layer 11 as a gate, and an interlayer insulating layer 12 is provided above the second polysilicon layer 11.
  • a source region 14, a drain region 15 and a channel region 16 are provided in the formed third polysilicon layer 13.
  • the pM ⁇ S—TFT 10 having such a structure, in order to realize a more complete transistor operation, impurities of the opposite conductivity type to the source region 14 and the drain region] 5 are added to the channel region 16. That is being done.
  • impurities of the opposite conductivity type to the source region 14 and the drain region] 5 are added to the channel region 16. That is being done.
  • the potential of the channel region 16 is not fixed. For this reason, the characteristics as pMOS-TFT cannot be exhibited to a human limit.
  • the planar pattern of the third polysilicon layer 13 includes a channel region 16
  • An electrode region 17 protruding from the electrode 17 is provided, and the electrode region 17 and the potential fixing electrode 18 are electrically connected via a contact portion 19.
  • the provision of the potential fixing electrode 18 as shown in FIG. 2 increases the area per memory cell, which is contrary to the demand for miniaturization and high integration of the semiconductor memory device.
  • An object of the present invention is to provide a semiconductor device having a pMOS-TFT structure capable of more stable operation without increasing the area occupied by the semiconductor device, and a method of manufacturing the same. That is, the present invention firstly provides an insulating layer provided on or above a surface of a semiconductor substrate, a gate electrode formed on the surface of the insulating layer, and a surface of the insulating layer including the gate electrode.
  • a semiconductor device including a wiring layer to be supplied.
  • the present invention also relates to a semiconductor memory cell including a pair of pass transistors, a pair of pull-down transistors, and a pair of TFT load transistors, wherein the TFT transistors are provided on or above a surface of a semiconductor substrate; A gate electrode formed on the surface of the insulating layer, a gate insulating film formed on the surface of the insulating layer including the gate electrode, at least a part of the gate insulating film on the surface of the gate insulating film; A polysilicon layer formed above the gate electrode and constituting a source region, a drain region, and a channel region; and a part of the source region and the channel region of the polysilicon layer. A wiring layer for supplying a voltage applied to the source region formed over the surface of the portion to the channel region. To provide a semiconductor memory cell, characterized by.
  • FIG. 1 is a cross-sectional view showing a conventional pMOS-TFT.
  • FIG. 2 is a plan view showing a case where a potential fixing electrode is provided in a conventional pMOS-TFT.
  • 3A and 3B are a cross-sectional view and a plan view, respectively, showing a step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.
  • 4A and 4B are a cross-sectional view and a plan view, respectively, showing a step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.
  • FIGS. 5A and 5B are a cross-sectional view and a plan view, respectively, showing one step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.
  • 6A and 6B are a cross-sectional view and a plan view, respectively, showing a step in the first embodiment of the method for manufacturing a semiconductor device of the present invention.
  • FIGS. 7A and 7B are a cross-sectional view and a plan view, respectively, showing a step of the first embodiment of the method of manufacturing a semiconductor device of the present invention.
  • FIGS. 8A and 8B are a cross-sectional view and a plan view, respectively, showing one step of the first embodiment of the method for manufacturing a semiconductor device of the present invention.
  • FIG. 9 is a plan view showing a layout of a TF ⁇ SRAM according to the second embodiment of the present invention.
  • FIG. 10 is an explanatory diagram showing symbols used to represent each layer in the layout shown in FIG.
  • FIGS. 11A and 11B are cross-sectional views each showing a cross section of TFT-SR R corresponding to the XIA-XIA line and the XIB-XIB line in I3 ⁇ 4j9.
  • FIGS. 12A to 12C are cross-sectional views showing the respective manufacturing steps of the TFT-SRAM according to the second embodiment.
  • FIGS. 13A to 13C are cross-sectional views showing respective manufacturing steps of the TFT-SRAM according to the second embodiment.
  • FIG. 14 is a circuit diagram showing a memory cell of a TFT-SRAM according to the third embodiment of the present invention.
  • FIG. 15 is an explanatory diagram showing a TFT-SRAM memory array according to the third embodiment.
  • FIG. 16 is an explanatory diagram showing a main part of the memory array of the TFT-SRAM shown in FIG.
  • FIG. 17 is an explanatory diagram showing a memory array of a TFT-SRAM according to the third embodiment.
  • FIG. 18 is a cross-sectional view showing one process of manufacturing the TFT-SRAM memory array according to the third embodiment.
  • FIG. 19 is a cross-sectional view showing one step of manufacturing the memory array of the TFTS RAM according to the third embodiment.
  • 3A, 3B to 8A, and 8B are a cross-sectional view and a plan view, respectively, showing the steps of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • a first polysilicon layer 32 constituting a gate electrode of a TFT is formed on a surface of an insulating layer 31.
  • the insulating layer 31 may be formed directly on the surface of the silicon substrate, or may be provided above another transistor structure.
  • the insulating layer 31 is made of, for example, a silicon oxide film.
  • the gate electrode 32 is obtained, for example, by depositing polysilicon on the surface of the insulating layer 31 and then patterning it by a known photolithography technique.
  • an n-type impurity such as phosphorus (P) or arsenic (A s) is added to the gate electrode 32 by, for example, an ion implantation method to reduce the resistance.
  • the gate electrode 32 is not limited to polysilicon, and may be made of, for example, a refractory metal such as tungsten or titanium or a refractory metal silicide thereof.
  • a gate insulating film 33 is formed above the gate electrode 32.
  • a CVD oxide film such as a plasma CVD oxide film, a low-temperature oxide film (LTO), and a high-temperature oxide film (HTO) can be appropriately selected and used.
  • a polysilicon layer 34 constituting a transistor base is formed on the surface of the gate insulating film 33.
  • This polysilicon layer 34 is formed by depositing non-product K silicon on the surface of the gate insulating film 33 and then subjecting it to an annealing process in a hydrogen atmosphere, for example, to grow polysilicon having no crystal grains. Let it. Thereafter, the polysilicon layer 34 is formed by performing a process using a known photolithography technique. An n-type impurity such as phosphorus ( ⁇ ) or arsenic (A s) is added to the polysilicon layer 34 by, for example, an ion implantation method.
  • a P-type impurity is added at a low concentration to at least a part of the region of the polysilicon layer 34 located above the gate electrode 32, that is, a region other than the channel region.
  • the channel region 36 of the polysilicon layer 34 is formed.
  • a resist pattern 35 is provided on the surface of the substrate.
  • a p-type impurity such as BF 2 is implanted into the polysilicon layer 34 at a low concentration by ion implantation.
  • P- impurity diffusion regions
  • p-type impurities are added except for a part (39) of the low-concentration impurity diffusion regions 37, 38 formed, and the high-concentration impurity regions (p + ) To form a source region 40 and a drain region 41. More specifically, as shown in FIGS. 6A and 6B, on the surface of the polysilicon layer 34, the channel region 36 and a part of the low-concentration impurity diffusion regions 37, 38 (39) Then, a resist pattern 42 is formed. Next, a p-type impurity such as BF 2 is implanted into the polysilicon layer 34 at a high concentration by an ion implantation method.
  • a p-type impurity such as BF 2 is implanted into the polysilicon layer 34 at a high concentration by an ion implantation method.
  • a source region 40 and a drain region 41 are formed, and a low-concentration impurity diffusion region 39 is left in a region from the channel region 36 to the drain region 41. Thereafter, the resist pattern 42 is removed. In this way, a TFT having a so-called LDD structure is formed.
  • a wiring layer extending from the source region 40 to the channel region 36 of the TFT formed as described above is formed.
  • a thin film 43 made of a refractory metal such as titanium is formed over the entire surface of the gate insulating film 33 including the polysilicon layer 34, for example. Spaghetti ring Formed.
  • a resist pattern 44 is formed on the surface of the thin film 43 so as to cover the region of the polysilicon layer 44 which extends over the end of the source region 40 and a part of the channel region 36. Thereafter, the thin film 43 is etched to pattern the thin film 43.
  • the thin film 43 is heated by, for example, Rapid Thermal Processing (RTP), and the titanium constituting the thin film 43 is silicided into titanium silicide. Thereafter, unreacted titanium is removed by a selective etching solution (eg, NH 3 , H 2 O 2 / H 2 O). As a result, as shown in FIGS. 8A and 8B, a wiring layer 45 covering an end portion of the source region 40 and a region extending over a part of the channel region 36 is formed.
  • a high melting point metal such as tungsten and cobalt can be used in addition to titanium.
  • the wiring layer 45 may be made of a high melting point metal such as titanium or tungsten, or a high melting point wiring material such as titanium nitride, which is used for normal wiring, in addition to the high melting point metal silicide. . In this case, the RTP treatment and the selective removal after depositing the thin film 43 and performing the cleaning are unnecessary.
  • the voltage applied to the source region 40 in this case, V
  • the potential of the channel region 36 is fixed. Therefore, when the above-described pMOS-TFT 10 is used, for example, for loading a TFT-loaded memory cell of a SRAM, the operation of the pMOS-TFT 30 is stabilized, and the stability of the memory cell is reduced. improves. Also, the channel area There is no need to provide an electrode for fixing the potential of the region 36 and the electrode for the source region 40, so the area occupied by the pMOS-TFT 30 can be reduced, making it suitable for large-capacity memories. In addition, the stability of the memory cell of the SRAM, the miniaturization and high integration of the SRAM can be achieved at the same time.
  • the case where the high melting point metal or its silicide is used as the wiring layer 45 has been described as an example.
  • polysilicon or amorphous silicon for the wiring layer 45.
  • impurities can be implanted into polysilicon or amorphous silicon to reduce the resistance.
  • a PN junction is formed between the source region 40 and the wiring layer 45 at the source-side contact portion.
  • the voltage control of the source region 40 of the pMOS-TFT 30 cannot be performed smoothly. There is a risk. Therefore, the above-mentioned high melting point metal or its silicide or non-doped polysilicon or amorphous silicon is used for the wiring layer 45, and unnecessary ⁇ junctions may be formed. It is preferable because there is no.
  • FIG. 9 shows the active region 96, the field oxide region 94, the second polysilicon layer 93, the third polysilicon layer 91, and the active region 96, among the components of the TFT-SRAM to which the present invention is applied.
  • 2 polysilico A layout focusing on a via hole 92, a contact hole 97, and a wiring layer 45 connecting between the contact layer 93 and the third polysilicon layer 91 is shown.
  • FIG. 9 unlike FIGS.
  • FIG. 11A is a cross-sectional view in the X direction showing a TFT-SRAM corresponding to the line XIA-XIA in FIG.
  • FIGS. 11A and 11B a cross-sectional view of a transistor region surrounded by a field oxide film 101 in a P-well region (P-WELL) formed on an N-type substrate (N-SUBSTRATE) is shown. It is.
  • the source region S and the drain region D of the pull-down transistor (PULLDOWN TRANSIST0R) and pass transistor (PASS TRANSISTOR) of the TFT-SRAM are surrounded by the field oxide film 101 in the P-well by the ⁇ N-impurity diffusion layer. It is formed in the active area.
  • a ground line GND to which the source region S of the pull-down transistor is connected is formed in the active region by an N + impurity diffusion layer. In one place (not shown) of this ground line GND, a plurality of memory cells are grouped. The source region S of the pull-down transistor of these memory cells is grounded.
  • a gate electrode G of a pair of pull-down transistors composed of a first polysilicon film 102 through a thin gate oxide film 109 is formed.
  • G2 and gate electrodes G3, G4 of a pair of pass transistors are formed.
  • the gate electrodes G3 and G4 of the two pass transistors shown in FIG. 11B are the gate electrodes of the pass transistors of the TFT-SRAM cell adjacent to each other.
  • an interlayer insulating layer composed of a gay nitride film layer 103 and a silicon oxide film layer 107 is formed, and side walls 108 are formed on the side surfaces thereof. Are formed.
  • Contact openings H1 to H3 are locally formed in the interlayer insulating layer composed of the silicon nitride film layer 103 and the silicon oxide film layer 107.
  • a titanium silicide layer 100 is formed on one of the gate electrodes G1 exposed in the contact opening HI.
  • one of the pull-down transistors is formed by the local connection portion LI formed by the second polysilicon layer 93.
  • the gate electrode G1 of the transistor and the drain region D of the other pull-down transistor are electrically connected.
  • the pad portion PD is formed by the second polysilicon layer 93 on the drain region D of the pass transistor formed between the two adjacent pass transistors.
  • an interlayer insulating layer 104 made of a silicon oxide film layer is formed on the second polysilicon layer 93.
  • a contact opening H4 is formed in a region in the buried contact portion BC of the second polysilicon layer 93.
  • the local connection portion L1 composed of the second polysilicon layer 93 and the third polysilicon layer 91 are electrically connected via the contact opening H4.
  • the third polysilicon layer 91 constitutes a TFT body of the TFT transistor, and has a channel region and a source region.
  • the wiring layer 45 is formed from a specific portion of the third polysilicon layer 91, that is, from a part of the source region of the TFT transistor to a part of the channel region.
  • a non-silicate glass (NSG) layer 105 and a borophosphosilicate glass (BPSG) layer 106 are formed above the wiring layer 45 and the third polysilicon layer 91.
  • NSG non-silicate glass
  • BPSG borophosphosilicate glass
  • Via holes 92 are formed in the NSG layer 105, the BPSG layer 106, and the interlayer insulating layer 104 above the pad portion PD.
  • a tungsten plug WP is formed in the via hole 92.
  • bit line 95 made of an aluminum layer is formed on the BPSG layer 106.
  • Bit line 95 is electrically connected to drain region D of the pass transistor via pad portion PD and tungsten plug WP in via hole 92.
  • the wiring layer 45 is formed on the third polysilicon layer 91.
  • the wiring portion 91a of the third polysilicon layer 91 extending in the direction has a function as a power supply line for supplying a power supply voltage to each memory cell.
  • the protruding portion 91b of the third polysilicon layer 91 which extends from the wiring portion 91a and is connected to the second polysilicon layer 93 via the via hole 92, forms a substrate of the PMOS-TFT.
  • the second polysilicon layer 93 located below the protruding portion 91a of the third polysilicon layer 91 acts as a gate electrode, that is, directly above the gate electrode, that is, The region of the projecting portion 91b of the third polysilicon layer 91 that intersects with the second polysilicon layer 93 becomes a channel region of the PMOS-TFT.
  • the region of the third polysilicon layer 91 located closer to the via hole 92 than the channel region forms a drain region of the PMOS-TFT.
  • the region of the third polysilicon layer 91 on the wiring layer 45 side constitutes the source region of the PMOS-TFT.
  • a wiring layer 45 extending from the source region of the PMOS-TFT 90 to the channel region is formed, and the potential of the TFT channel region is fixed by the wiring layer 45.
  • the wiring layer 45 is formed up to the portion of the portion 9b that overlaps the second polysilicon layer 93, that is, the middle position of the channel region of the PMOS-TFT. This allows the book An SRAM cell to which the invention is applied can be realized.
  • the wiring layer 45 is formed of a high melting point metal or a high melting point metal silicide. For this reason, the resistance of the wiring portion 91a of the third polysilicon layer 91 can be reduced. As a result, an unnecessary drop in the power supply voltage due to the wiring resistance is prevented, which is also effective in improving the stability of the memory cell.
  • FIGS. 9, 10, 11A and 11B 94 indicates an active area, 95 indicates a bit line, and 96 indicates a contact hole.
  • 101 is a field oxide film
  • 102 is a first polysilicon layer
  • Reference numeral 107 denotes an interlayer insulating film
  • reference numeral 108 denotes a side oxide film.
  • a method of manufacturing the above-described PM TFTS-TFT according to the second embodiment of the present invention will be described with reference to FIGS. 12A to 12C and 13A to 13C.
  • the present invention aims at obtaining more stable PMOS characteristics without increasing the area occupied by the PMOS-TFT.
  • a conventional manufacturing method as disclosed in JP-A-7-169965 can be employed.
  • a gate 110 is formed in or on a semiconductor substrate, for example, a single crystal silicon substrate.
  • a gate 110 is placed on another transistor polysilicon gate (not shown) in which the source, drain, and channel regions are formed in a polysilicon substrate.
  • the gate 110 is a doping layer covered with a metal silicide layer such as titanium silicide. It may be formed from a polycide including a doped polysilicon layer. Further, the gate 110 may be formed entirely of doped polysilicon, entirely formed of a metal gallide, or formed of some other conductive material.
  • the gate insulating layer 114 is formed so as to cover the gate 110.
  • the gate insulating layer 114 is made of, for example, LT ⁇ C VD (Low-temperature-oxide chemical vapor deposition) method at 450 ° C to a thickness of 400 ⁇ 4 OA. Silicon. This low deposition temperature of 450 ° C is intended to avoid the adverse effects of high temperatures on integrated circuit elements (not shown) present during transistor fabrication. There is no particular limitation on the processing temperature, thickness, manufacturing technique, material, and the like.
  • the gate insulating layer 114 may be, for example, silicon nitride.
  • a contact hole (not shown) is provided in the gate insulating layer 114 by etching, and a conductive layer formed on the gate insulating layer 114 and a gate insulating layer 114 are formed. It is also possible, if necessary, to obtain electrical contact with the underlying layers.
  • a polysilicon layer 118 is formed over the above structure.
  • the polysilicon layer 118 is provided with the source, drain, and channel regions of the transistor.
  • amorphous silane (S i ⁇ 4 ) is deposited by LPCVD (low pre ssure chemical vapor deposition) at a temperature of 550 ° C. and a thickness of 350 ⁇ 40 A.
  • Polysilicon layer 1 18 with a layer of porous silicon To achieve.
  • this structure is annealed in a nitrogen atmosphere at a temperature of 600 to 65 for 5 to 30 hours to recrystallize the amorphous silicon polysilicon layer 118.
  • the crystal grains in the polysilicon layer 118 become large, so that a low off-state current and a high on-state current of a transistor are generated.
  • the threshold voltage can be lowered by reducing the thickness.
  • Such a low threshold voltage is desirable, for example, in the case of a bull-up transistor of a memory cell composed of six transistors, and it is needless to say that if the embodiment changes, other manufacturing techniques, materials and thicknesses may be correspondingly changed.
  • the thickness of the polysilicon layer 118 may be increased depending on the formation conditions of the wiring layer 45 formed on a part of the polysilicon layer 118 in the future.
  • an N-type impurity is doped on the entire surface of the polysilicon layer 118.
  • the N-type impurity for example, phosphorus or arsenic can be selected.
  • As for a P-type transistor As is 30 keV as a dopant, and is 0 with respect to the wafer normal. Or, inject at a dose of 5 ⁇ 10 12 at oms / cm 2 from an angle of 7 °.
  • the polysilicon layer 118 is patterned using masking and etching techniques known in the art. In one embodiment, the etching to pattern the polysilicon layer 118 is performed with a calculated overetch of 180%. Next, at a temperature of 4 0 0, the C VD method, dioxide silicon emission layer 1 2 2 silane (S i H 4), is deposited to a thickness of 3 0 0 ⁇ 4 0 A. Other embodiments use other materials, thicknesses and manufacturing techniques.
  • the silicon dioxide layer 122 acts as an etching stopper during the etching of the LDD mask comprising the polysilicon layer to be formed. In addition, the silicon dioxide layer 122 functions as a shielding layer for shielding contaminants during doping of the source and drain of the polysilicon layer 118.
  • the LDD mask 126 is a polysilicon layer formed to a thickness of 1200 ⁇ 10 OA by the LPC VD method.
  • the LDD mask 126 is a polysilicon layer formed to a thickness of 1200 ⁇ 10 OA by the LPC VD method.
  • other embodiments will use other materials, thicknesses and manufacturing techniques.
  • the photo resist mask 130 used for patterning the LDD mask 126 is formed by a well-known photolithographic method (photolithography technique).
  • the mask 130 has a transistor channel length 134, a source region 134 extending a source region 142 over the gate 110, and a drain region 150 extending a gate.
  • a drain over wrap 1 4 6 extending over it is defined.
  • the source overlap 13 8 and the drain overlap 1 4 6 are made sufficiently large to give the desired on-current, while the channel length 13 4 is made sufficiently large to reduce the off-current.
  • the source If the burlap 1 38 is at least 0.1 m and the channel length 1 34 is at least 0.5 m, the specifications for on-off current and break voltage are satisfied.
  • the channel length 1 34 may be a negative value up to -0.1 m. That is, the drain region 150 may not overlap the gate and may be separated from the gate by a maximum of 0.1 xm in the lateral direction.
  • the alignment tolerance of the mask 130 is 0.15 / m
  • the source overlap 1 38 is 0.25 ⁇ 0.1
  • the drain overlap is , 0.05 ⁇ 0.15 m.
  • the channel length is 0.7 m.
  • the source and drain regions are covered and the 1) 0 mask 1 26 is etched by a known etching technique. In one embodiment, the calculated overetch is 15%. Of course, if the embodiment changes, another calculated value of over-etching is used.
  • the mask 130 is removed to obtain a structure shown in FIG. 12B.
  • the LDD dopant is injected into the source region 142 and the drain region 150.
  • L 1) 1) Mask 1 2 6 masks channel region 1 5 4. 1) 1) The mask 1 2 6 protects the silicon dioxide layer 1 2 2 from contaminants K.
  • the dopant is BF 2 and is implanted by ion implantation at an angle of 0 °, ie, perpendicular to the wafer, at an energy of 55 keV. Is done. This dose is 5 ⁇ 1 () 13 atoms / cm 2 .
  • other Use dopants, doping levels, and doping techniques For an n-channel transistor, use an n-type do-band.
  • a high concentration doping mask 158 is formed on the LDD region 15OA.
  • a mask 158 is formed by depositing a desired layer of masking material and then selectively removing the dopant implant.
  • a photo resist layer is applied to form a mask 158, the photo resist portion is exposed to ultraviolet light, and either the exposed or unexposed portion is imaged. Selective removal in liquid.
  • mask 158 overlaps mask 126 and channel region 154.
  • the masking of this channel region does not depend on the mask 158, since the mask 126 remains masking the channel region. Therefore, the channel length ⁇ 34 is not affected by the alignment of the mask 158.
  • the channel length does not need to absorb mask alignment errors and can be set to a minimum value determined by the maximum off-current specification and the source-drain breakdown voltage specification. Therefore, the package density can be increased.
  • the source overlap 13 8 is also unaffected by the mask 15 8 alignment, and as long as the mask 158 extends laterally beyond the drain side gate 110, the drain overlap Laps 1 4 6 are also unaffected. This channel length and source overlap The fact that the drain overlap is not related to the alignment of the mask 158 enhances the reproducibility of the electrical characteristics of the transistor, thus improving the manufacturing yield.
  • the lateral offset 162 from the gate 110 of the heavily doped drain region 1505B is fixed with the mask 158 to obtain the minimum value that satisfies the maximum off-current specification.
  • offset 162 is 0.2 ⁇ m. In many applications where a large number of six-transistor SRAMs are used, if the offset 162 is at or above a minimum, the on-current will not decrease even if the offset 162 increases significantly. The alignment on the drain side of mask 158 does not affect the characteristics.
  • the dimensional force of offset 162 may vary between 0.2 m and 0.6 m.
  • the transistor is thus not strongly affected by the mask 158 alignment, and high reproducibility and high yield can be obtained.
  • the channel length and the source / drain overlap are determined by only one mask, that is, the mask 130, without being strongly affected by the alignment error of the mask 158. ( Figure 12A). Therefore, the mask matching tolerance value may be loose, the area occupied by the transistor can be reduced, and high reproducibility and yield can be obtained.
  • a dopant is implanted into the drain region 150B and the source region 142.
  • the silicon dioxide layer 122 protects the polysilicon layer 118 from contaminants.
  • P-type transistor In one embodiment, BF 2 as a dopant is implanted at 55 keV at an angle of 0 ° or 7 ° with respect to the wafer normal. The dose is 3 ⁇ 10 15 atoms / cm 2 .
  • n-type transistors use n-type dopants.
  • the mask 158 is removed using a known method.
  • the LDD mask 126 may also be removed using a known method. In one embodiment, mask 126 is etched away with a calculated overetching of 80%.
  • the silicon dioxide layer 122 is removed using known methods ( Figure 13A).
  • a high melting point metal is formed on the entire surface.
  • titanium 170 is deposited at 500 ⁇ 50A.
  • a photo resist mask 171 used for patterning the titanium layer 170 is formed by a known photolithographic method.
  • the wiring layer 45 must not short-circuit with the drain region 150 and must sufficiently overlap with the channel region 154, so that the wiring layer 45 overlaps with the channel region 154.
  • the wrap amount 1 7 2 may be 1 2 of the channel length 1 3 4.
  • the overlap 1 73 was set to 0.6 m, but if the embodiment changes, a value corresponding to the manufacturing technology, the material and the thickness is used.
  • titanium 170 is etched by a known anisotropic etching (FIG. 13B), and then the mask 17 1 is removed by a known technique. Selective silicidation is performed by RTP.
  • FIG. 14 shows a 6-transistor transistor SRAM cell 206, in which pull-up transistors 210 and 214 are formed by the PMOS-TFT according to the second embodiment. I have.
  • the sources of the PMOS transistors 210 and 214 are connected to a power supply Vcc such as 5.0 V or 3.0 V.
  • the drain of transistor 214 is connected to an NMOS transistor with its source connected to a reference voltage Vss (typically ground). It is connected to the drain of a pull-down transistor 218 consisting of a transistor.
  • the drain of the transistor 210 is connected to the drain of a pull-down transistor 222 consisting of an NMOS transistor whose source is connected to Vss.
  • the gate of the transistor 218 is connected to the gate of the transistor 218 and the drains of the transistors 210 and 222, and the source is connected to the bit line BL.
  • the gate of the transistor 210 is connected to the gate of the transistor 222 and the path composed of the NMOS transistor connected to the drain of the transistor 214 and the source connected to the complementary bit line BL.
  • the gates of the pass transistors 222 and 230 are connected to the common line WL.
  • FIGS. 15, 16, 18 and 19 show the structure of the memory array with memory cells shown in FIG. 14 and a method of manufacturing the same.
  • FIGS. 15 and 16 show plan views of a portion of an array having four identical memory cells 206-4-1 through 206-6-4 at different stages of fabrication. Of course, the number of memory cells in the array may be any number without being limited to this embodiment.
  • FIGS. 18 and 19 show cross-sectional views of memory cells 206-13.
  • No. 2 26—i, 230—i was obtained from N. Godinho et al., US Pat. No. 5,124,774 (permitted June 23, 1992, issued. Application No. 07Z743, 08, filed on Aug. 9, 1991)
  • Four-transistor transistors are formed in essentially the same manner as described in connection with the SRAM cell. Generally speaking, transistors
  • a P-type well 3 10 (Fig. 18 and Fig. 1 9) is formed.
  • the field oxide region 314 is grown on the substrate surface to provide isolation as needed.
  • the gate oxide layer 318 is thermally treated to grow on the transistor active area.
  • a first polysilicon layer 322 (FIGS. 15, 18, and 19) is formed on this structure.
  • the silicon dioxide layer 326 and the silicon nitride layer 330 are formed on the layer 322.
  • Sandwich etching of layers 32, 32, and 33 creates a pattern of layer 32 to form the gates of pull-down transistors 222-i, 218-i.
  • Layers 322 also form wordlines WL1-1, WL-2 (FIGS. 15 and 19), some of which are the gates of each pass transistor 226-i, 2300-i. Act as Sandwich layer 3 2 2, 3 2 6, 3
  • Step 15 The boundary of the island region including the source region, drain region, and channel region of the pull-down transistor and pass transistor is shown by the dotted line in Figure 15.
  • a conformal layer of silicon dioxide is deposited and etched to form a pull-down transistor and a spacer 334 (FIGS. 18 and 19) around the pass transistor. A portion of the gate oxide layer 318 that is removed when the spacer is etched is regrown by applying heat.
  • An n-type high concentration dopant is implanted into the substrate source and drain regions and into the Vss line Vss-i (i-1,2).
  • the spacer 334 acts as a mask, and the pull-down transistor and the pass transistor form an LDD structure.
  • a layer of silicon dioxide 333 (FIGS. 18 and 19) is deposited on the wafer.
  • Gate peer holes for the gates of transistors 2 2 2-3 and 2 18 8-3 of memory cell 206-3, 3 4 2-3 and 3 4 6-3, and similar gates in other memory cells Tovia holes are formed in the structure.
  • buried via holes 350-0-3 and 354-4-3 for the drains of the pull-down transistors of the memory cells 206-13, and similar contact portions in other memory cells are formed.
  • the contact holes for the drains of each pass transistor 2 26 6-i, 2 3 0-i 3 5 8-1 to 3 5 8-4 have a buried via hole for contact with the bit line to be formed later. Formed at the same time.
  • Layers 36 6 of titanium silicate are gate vias 3 4 2—3 and 3 4 6—3, embedded via holes. Formed on the exposed silicon surface by contact holes, such as contact holes 3505--3 and 354-3, bit line contact holes 358-i.
  • a conductive layer 110 is formed over this structure.
  • the connection line formed by the layer 110 connects the gate of the transistor 222-i to the drain of the transistor 218-i and the gate of the transistor 218-i in each memory cell 206-i.
  • the gate is connected to the drain of the transistor 222-i, respectively.
  • the layer 110 forms a conductive plate on the bit line contact hole 358-i.
  • the layer 110 forms a gate of pull-up transistors 210-i and 214-i.
  • layer 110 includes doped polysilicon covered by titanium nitride, which polysilicon is covered by titanium nitride.
  • the layer 110 is formed by sputtering titanium on the doped polysilicon on which the pattern is formed, and heating the titanium in a nitrogen atmosphere to form a titanium silicide and the silicide on the polysilicon.
  • a titanium nitride and an entire structure are formed thereon, and the titanium nitride and the unreacted titanium are peeled off.
  • the structure is heated again in a nitrogen atmosphere to form titanium nitride on the titanium nitride.
  • different embodiments use different materials and manufacturing techniques.
  • the contact holes 3 6 8-3 and 3 7 2-3 (FIGS. 17 to 19) in cells 206 to 3 were etched through layer 114 to form a connection consisting of layer 110, An electrical contact with the polysilicon layer 118 to be formed is obtained.
  • the actual position of the contact hole 372-2 is behind the plane shown in Fig.19. However, in some embodiments, the contact holes 372-2 are located in the plane of the figure as shown in FIG. A similar contact hole is etched and opened in another cell 206-i.
  • the thickness of layer 114 is 400 ⁇ 10 A, and contact etching is performed with a calculated overetch of 50%.
  • a polysilicon layer 118 (Figs. 18 and 19) is formed, and a low-concentration N-type dopant is implanted over the entire surface.
  • the polysilicon layer 118 forms the Vcc line and the source, drain, and channel regions of the pull-up transistors 210-i and 214-i.
  • Figure 17 shows the polysilicon layer 1 18, part of the layer 3 2 2 in the memory cell 206-3, and the top of the contact hole 3 58-i in the memory cell 206-4. Layer 110 is shown.
  • the silicon dioxide layers 122 shown in FIGS. 18 and 19 are formed as described in FIG. 12A.
  • a polysilicon mask 126 is formed in each memory cell 206_i over the channel regions 154-1—i and 154-2—i of the pull-up transistor. .
  • a P-type LDD dopant formed by the above technique is implanted into the third polysilicon layer 118 as described above according to FIG. 12B.
  • the source region and the drain region of the pull-up transistor, the Vcc line, Vcc-11 and Vcc-2 are doped with P-type ion impurities.
  • the photo resist mask 158 shown in FIGS. 18 and 19 is replaced with the LDD region 150 A—1—i and 1 LD of each memory cell 206-i as described above. It is formed on 5 0 A— 2— i (Fig. 17).
  • P-type dopants are implanted into the exposed area of the drain region, and are also implanted into the source region of the pull-up transistor to perform high concentration doping. The dopant is also injected into the Vcc line Vcc-1.
  • the masks 158 and 126 are removed as described above according to FIG. 12C. Further, according to FIG. 13A, the silicon dioxide layer 122 is removed, and titanium 170 is deposited on the wafer.
  • the titanium is etched to remove the photoresist mask 171, as shown in FIG. 13B. Thereafter, an RTP process is performed as shown in FIG. 13C to complete the wiring layer 45 shown in FIG. 9 and FIGS. 11A and 11B.
  • This structure is covered with one or more insulating layers (not shown).
  • the contact hole is formed via an insulating layer, and the portion 110 is exposed to the bit line contact hole 358-i J :.
  • a layer of doped polysilicon or tungsten silicide (not shown) is formed to form a conductive region over each contact hole 358-i. These areas are the bit Obtain electrical contact between the drain of drain and pass transistors 2 26—i and 2 30—i. Two regions of each memory cell 206-i extend from each contact hole 358-i to provide more space between each bit line.
  • a layer of silicon dioxide (not shown) is deposited. Windows are formed in the silicon dioxide layer up to the conductive area.
  • Vcc line A metal bit line (not shown) formed perpendicular to Vcc-1 forms a passivation layer (not shown) above these bit lines that contacts the conductive area through these windows. I do.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention se rapporte à un dispositif à semiconducteur doté d'une structure PMOS-TFT, qui fonctionne de manière stable. La superficie occupée par le dispositif à semiconducteur est néanmoins peu importante. L'invention porte également sur un procédé permettant de fabriquer le dispositif à semiconducteur. Une grille est formée sur une couche isolante et un film isolant la grille est formé sur la surface de la couche isolante comprenant la grille. Une couche de polysilicium est formée sur la surface du film isolant la grille. Dans la couche de polysilicium, une région de source est formée sur une extrémité d'une région de canal et une région de drain est formée sur l'autre extrémité, alors que dans la partie intermédiaire se trouve une région diffusée à faible concentration d'impuretés. A la surface de la région de source et de la région de canal, on forme une couche de connexion à travers laquelle une tension appliquée à la région de source va alimenter la région de canal.
PCT/JP1996/001792 1995-06-30 1996-06-28 Dispositif a semiconducteur et son procede de fabrication WO1997002604A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP7/165190 1995-06-30
JP16519095 1995-06-30

Publications (1)

Publication Number Publication Date
WO1997002604A1 true WO1997002604A1 (fr) 1997-01-23

Family

ID=15807554

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/001792 WO1997002604A1 (fr) 1995-06-30 1996-06-28 Dispositif a semiconducteur et son procede de fabrication

Country Status (1)

Country Link
WO (1) WO1997002604A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01231024A (ja) * 1988-03-11 1989-09-14 Seikosha Co Ltd 薄膜トランジスタアレイ
JPH05110035A (ja) * 1991-10-16 1993-04-30 Sony Corp スタテイツクｒａｍ
JPH06232405A (ja) * 1993-02-03 1994-08-19 Nec Corp 薄膜トランジスタ
JPH0878686A (ja) * 1994-09-05 1996-03-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01231024A (ja) * 1988-03-11 1989-09-14 Seikosha Co Ltd 薄膜トランジスタアレイ
JPH05110035A (ja) * 1991-10-16 1993-04-30 Sony Corp スタテイツクｒａｍ
JPH06232405A (ja) * 1993-02-03 1994-08-19 Nec Corp 薄膜トランジスタ
JPH0878686A (ja) * 1994-09-05 1996-03-22 Nippon Telegr & Teleph Corp <Ntt> 半導体装置及びその製造方法

Similar Documents

Publication Publication Date Title
KR100746220B1 (ko) 적층된 노드 콘택 구조체들과 적층된 박막 트랜지스터들을채택하는 반도체 집적회로들 및 그 제조방법들
US5348897A (en) Transistor fabrication methods using overlapping masks
US20040005755A1 (en) Semiconductor memory device and a method of manufacturing the same
JP2005203780A (ja) ノードコンタクト構造体、それを有する半導体素子、及びその配線構造体、並びにその製造方法
US6888191B2 (en) Semiconductor device and fabrication process therefor
US6649935B2 (en) Self-aligned, planarized thin-film transistors, devices employing the same
JP2589438B2 (ja) 半導体メモリ装置及びその製造方法
JP2851968B2 (ja) 改良された絶縁ゲート型トランジスタを有する半導体装置及びその製造方法
US5497022A (en) Semiconductor device and a method of manufacturing thereof
JP2658844B2 (ja) 半導体記憶装置
KR100252560B1 (ko) 반도체메모리장치및그제조방법
JPH10242299A (ja) 半導体記憶装置及びその製造方法
KR100493047B1 (ko) 선택적 에피택셜 성장을 이용한 반도체 소자의 국부 배선형성 방법
JP3039432B2 (ja) 半導体装置の製造方法
US6737711B1 (en) Semiconductor device with bit lines formed via diffusion over word lines
WO1997002604A1 (fr) Dispositif a semiconducteur et son procede de fabrication
JP2751893B2 (ja) 半導体記憶装置およびその製造方法
JP2621824B2 (ja) 半導体装置の製造方法
KR960015786B1 (ko) 반도체장치 및 그의 제조방법
JP2621820B2 (ja) スタティック型メモリセル
JPH0964203A (ja) 半導体装置の製造方法
KR100207809B1 (ko) 반도체 장치 및 그의 제조방법
JP2001189389A (ja) 半導体記憶装置及びその製造方法
JP3055491B2 (ja) 半導体装置およびその製造方法
JP2004128182A (ja) 半導体集積回路装置およびその製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)