WO1993017380A1 - Liquid crystal display device - Google Patents
Liquid crystal display device Download PDFInfo
- Publication number
- WO1993017380A1 WO1993017380A1 PCT/JP1992/000200 JP9200200W WO9317380A1 WO 1993017380 A1 WO1993017380 A1 WO 1993017380A1 JP 9200200 W JP9200200 W JP 9200200W WO 9317380 A1 WO9317380 A1 WO 9317380A1
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- WIPO (PCT)
- Prior art keywords
- display
- liquid crystal
- power consumption
- image
- signal
- Prior art date
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
- G06F3/147—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using display panels
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/10—Special adaptations of display systems for operation with variable images
- G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
Definitions
- the present invention relates to a liquid crystal display device in a personal computer, and more particularly, to a liquid crystal display device having a power consumption reducing function and capable of performing a stable display.
- FIG. 1 shows a block diagram of a display device equipped with this automatic display stop system, together with a central processing unit (hereinafter referred to as CPU).
- the display unit is connected to CPU 101 via bus line 102.
- Display controller or display image generating means connected
- First plane image display storage means 104 composed of 103 and video memory (also called VRAM) and liquid crystal display element (LCD)
- T 1 test circuit 1 1 1 is C PU 10
- the measurement circuit outputs a count-up signal 113 when a predetermined time elapses without inputting the next interrupt signal after starting the count, and the display stop circuit 1 22 2 measures T 1 Count up signal from circuit 1 1 1
- measurement circuit 1 1 1 and display stop circuit 1 2 are a circuit that stops the display by setting the signal 114 to high level in response to 113.
- FIG. 2 forms the power consumption mode switching means 108.
- the transmission of the LCD data 1 15 and the LCD drive signal 1 16 to the LCD is stopped.
- the display drive circuit 123 resets the count by setting the signal 112 to the high level at the same time that the INTR 122 changes to the high level after the display stops or during the count, and resets the signal to the signal 114
- reference numeral 109 denotes a power supply
- 110 denotes an external input means such as a keyboard.
- the present invention solves this problem and allows the user to use a personal computer or a word processor, etc. It is an object of the present invention to provide a personal computer or a word processor which can be used and consumes less battery. Disclosure of the invention
- the present invention provides a liquid crystal display device having the following technical configuration to achieve the above object. That is, in a display device including a power supply, a central processing unit, a liquid crystal display unit, a display image generation unit, a first image display storage unit, a display image data control unit, a power consumption mode change unit, an external input unit, and the like.
- the display image data control means is provided with a second image display storage means, and in the case of the normal power consumption mode, the display image data generated by the display image generation means is stored in the first image display storage means.
- the low power consumption mode is set by activating the power consumption mode changing means through the LCD, the display image data stored in the second image display storage means is displayed.
- the liquid crystal display device temporarily stores the display image data generated by the display image generation unit in the second image display storage unit, and then stores the display image data in the second image display storage unit. Is stopped, and then the display image data stored in the second image display storage means is displayed on the liquid crystal display means.
- FIG. 1 is a diagram showing a configuration example of a conventional liquid crystal display device. It is a block diagram.
- FIG. 2 is a diagram illustrating the principle of the liquid crystal display device according to the present invention, and is a block diagram illustrating a configuration of a specific example of the liquid crystal display device according to the present invention.
- FIG. 3 is a block diagram showing a configuration of a second specific example of the liquid crystal display device according to the present invention.
- FIG. 4 is a block diagram showing a configuration of a third specific example of the liquid crystal display device according to the present invention.
- FIG. 5 (A) shows an address bus decoder circuit used in the liquid crystal display device according to the present invention
- FIG. 5 (B) shows a specific example of a display image generation means standby start switching circuit. This is a block diagram.
- FIG. 6 (A) is a frequency dividing circuit used in the liquid crystal display device of the present invention
- FIG. 6 (B) is a block diagram showing a specific example of a counter circuit.
- FIG. 7 (A) is a block diagram showing a specific example of a signal generation circuit for a holding memory, that is, a signal generation circuit for a second image display storage means, used in the liquid crystal display device according to the present invention.
- Figure (B) is a block diagram showing a specific example of the synchronization signal switching circuit.
- FIG. 8 (A) is a block diagram showing a specific example of a data access circuit used in the liquid crystal display device according to the present invention
- FIG. 8 (B) is a signal waveform diagram relating to the data access circuit. It is.
- FIG. 16 is a view for explaining effects obtained in the liquid crystal display device according to the present invention.
- FIG. 17 is a block diagram showing a configuration of a fourth specific example of the liquid crystal display device according to the present invention.
- FIG. 18 and FIG. 19 are timing charts showing the operation of the liquid crystal display device according to the present invention.
- BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, specific examples of a liquid crystal display device according to the present invention will be described in detail with reference to the drawings.
- FIG. 2 is a block diagram illustrating a basic configuration example of a liquid crystal display device according to the present invention.
- Power supply 109 central processing means 101, liquid crystal display means 107, display image generation means 103, first image display storage means 104, display image data control means 106, power consumption Mode change means 1 0
- the display image data control means 106 is provided with a second image display storage means 208, and the normal power consumption In the case of the mode, the display image data generated by the display image
- the second image is displayed.
- a control means 2 15 for displaying the display image data stored in the display storage means 208 on the display of the liquid crystal display means 107 is provided.
- the display image data generated by the display surface image generating means 103 is once stored in the second surface image display storage means 208, and then the display image data is stored.
- the display function of the generating means 103 is stopped, and the display surface image data stored in the second image display storage means 208 is displayed on the liquid crystal display means 107.
- the display data holding memory 208 which requires only a small amount of power, is used to store the LCD data 216, and a large amount of power is required.
- the display function of the display image generation circuit 103 which functions as a display controller to be stopped.
- the LCD data 211 in the second image display storage means 208 which stops and functions as a display data holding memory Is displayed repeatedly. In other words, when word processing software or the like is waiting for keyboard input, the user can see the display even when the low power consumption mode is set.
- the power source 201 used in the present invention is not particularly limited, but is a small and portable personal convenience.
- a DC power source such as a battery or a battery.
- the configuration of the power consumption mode switching switch used in the present invention is not particularly limited.
- the power consumption mode switching switch can be switched between the normal power consumption mode and the low power consumption mode by manual or automatic control. It is sufficient if it is configured to be able to arbitrarily select the password and the password.
- the selection of the above mode may be performed, for example, when the first image display / storage means is accessed via the CPU by an input from an external keyboard, or when a program such as a spreadsheet is accessed.
- a case where the first image display storage unit is accessed is detected, and based on the frequency of the access, a determination is made as to whether to enter the low power consumption mode or the normal power consumption mode.
- the presence or absence of an interrupt signal to the CPU may be detected, and the determination may be made based on the frequency.
- the normal power consumption mode and the low power consumption mode may be executed by changing the voltage or the frequency during use.
- the power consumption mode changing means 108 provided in the display image data control means 106 includes at least an external input means or a specific program processing via the central processing means.
- Access detection means 205 for detecting a state in which a predetermined signal has accessed the first image display storage means 104 or the display image generation means 103 based on the access frequency, and the access frequency per unit time.
- Means (not shown) for calculating the key A means (not shown) for comparing the access frequency with a reference value is provided, and when the access frequency falls below the reference value, the mode is switched from the normal power consumption mode to the low power consumption mode. It may be anything.
- a predetermined signal is output from the first image display storage means 104 or the display image generation means 103 based on at least the external input means or a specific program processing via the central processing means.
- Interrupt signal detecting means for detecting the state of interruption to the CPU, means for calculating the interrupt frequency per unit time (not shown), means for comparing the interrupt frequency with a reference value (FIG. (Not shown), and a control means configured to switch from the normal power consumption mode to the low power consumption mode when the interrupt frequency falls below the reference value.
- a control means 2 comprising a pseudo drive signal generation means 206 for generating a pseudo drive signal 210 of the liquid crystal display means 107 for the drive signal 217 and a memory control circuit 207 for controlling the same. 15 are provided.
- the display image data stored in the second image display storage means 208 is displayed on the liquid crystal display means 107 in synchronization with the pseudo drive signal 218.
- the VRAM access detection circuit 205 constituting the power consumption level switching means 108 in the present invention is a memory control circuit when the CPU 101 is not accessing the first image display storage means 104.
- the memory control circuit 207 receives the high level signal of the VRAM access detection circuit 205, the memory control circuit 207 transfers the LCD data 216 from the first image display storage means 1104 via the display image generation means 3103. Display data retention Stored in memory 208.
- the memory control circuit 207 sends a high-level power-off mode switching signal 221 to the pseudo signal control generation circuit 206 and the display image generation means 103 to display image generation means 1 for display.
- the pseudo signal control generation circuit 206 generates a pseudo drive signal 218 for LCD in place of the stopped display plane image generation means 103, and is a fixed image from the display data holding memory 208.
- the display data 220 is read out and sent to the liquid crystal display device 107 as pseudo LCD data 219.
- the writing and reading of the data to and from the display data holding memory 208 are performed by the memory signal 214 generated by the memory control circuit 207 according to the signal 218.
- the VRAM access detection circuit 205 sets the signal 211 to the memory control circuit 207 to low level. That is, a signal to set to the normal power-off mode is issued.
- the memory control circuit 207 switches the low-level low power consumption to the pseudo signal control generation circuit 206 and the display image generation means 103.
- the image generation means 103 is driven at a low frequency, for example, by sending the display signal 2 12 for display.
- the pseudo signal control generation circuit 206 stops the pseudo synchronizing signal 218 for LCD and switches to the LCD data signal 219 from the display image generation means 103, and the display screen image generation means 106
- the display data from 3 is output as LCD display data.
- the display device of the personal computer according to the specific example described above does not have the problem of turning off the display of the display unit even in the low power consumption mode, and the user can operate without interrupting his thinking.
- FIG. 3 Another specific example of the liquid crystal display device according to the present invention will be described with reference to FIGS. 3 and 4.
- FIG. 3 is a diagrammatic representation of the liquid crystal display device according to the present invention.
- FIGS. 3 and 4 are both shown in FIG. 2 and have improved functions based on the first specific example. Is the same as
- the power consumption mode changing means 108 in FIG. 3 comprises, for example, an address bus decoder circuit or the like, and the central processing unit (CPU) 101 comprises the first image display storage. Access to the means 104, or access to detect that the central processing unit (CPU) 101 has performed any interrupt operation on the display surface image generating means 103;
- the output signal 239 from the standby start switching circuit 222 changes according to the change of the level and the “L” level.
- the control circuit 2 15 When the output 2 39 from the standby start switching circuit 2 22 is set to, for example, “H” level, the control circuit 2 15 is activated to be in the low power consumption mode, and when the output is set to “L”.
- the display image generating means 103 is configured to be activated and switched to the normal power consumption mode.
- FIG. 5 (A) An example of the address bus decoder circuit 205 used in the present invention is shown in FIG. 5 (A), and an example of the display controller 'standby start switching circuit 222' is shown in FIG. 5 (B). Keep it.
- the address bus decoder circuit 205 used in the present invention comprises address buses A16 to A19, multiplexers MP1 to MP4 and a decoding circuit D. 1 and input address buses Al6 to A19, and in response to a timing signal 237 for writing the memory, the decode circuit D1 Transfer the data.
- the decoding circuit D1 decodes AM16 to AM19 which are the outputs of the multiplexers MP1 to MP4, and if they are in the VRAM 104 area which is the first plane image display storage means. If it is, the output 2 35 of the decode circuit D 1 is changed from “L” level to “H” level.
- AMI 6 to AM 19 are AMI 6 ⁇ ⁇ ⁇ "H” level, AMI 7 ⁇ ⁇ ⁇ "H” level, AM I 8 ⁇ ⁇ ⁇ "L” level, AM I 9 ⁇ ⁇ ⁇ ⁇ In the case of the "H" level, that is, this state is represented by B in hexadecimal notation.
- the signal of the CPU 101 and the like in this state Only during the period when 2 3 7 is at the “L” level, the output 23 5 of the decode circuit 01 is at the “11” level.
- the display controller / standby start switching circuit 222 is composed of an AND gate circuit, a binary counter BC1, a NAND gate circuit, an inverter circuit, and the like as shown in FIG. 5 (B).
- the output signal 235 from the address bus decoder circuit 205 is input to the binary counter BC1 at a "H" level as a reset signal, the feedback signal FB goes to the level.
- the binary counter BC 1 starts counting by using the signal FLM 1 which is the output 2 31 from the count circuit 224 as a clock, and starts counting at a predetermined count.
- the output signals OUT 1 and OUT 2 are simultaneously at the “H” level, and as a result, the feedback signal FB is at the “L” level, and the signal FLM 1 is not input.
- the output signal 239 from the display controller's standby start switching circuit 222 is the inverse of the feedback signal FB.
- the pseudo signal control generation circuit 206 of the control circuit 215 includes a frequency dividing circuit 223, a counter circuit 224, a synchronous signal switching circuit 225, and a data switching circuit 224.
- the frequency dividing circuit 223 for example, converts the source oscillation clock input from an appropriate oscillation source 0 SC into an internal clock 2 3 4 having a frequency that can be easily used in the internal circuit. The frequency is divided.
- the configuration of the frequency dividing circuit 223 is not particularly limited.
- a circuit combining an appropriate flip-flop and an inverter as shown in FIG. 6 (A) is used.
- the counter circuit 224 periodically generates the pseudo synchronizing signal 231 by counting the internal clock 234 to a predetermined number.
- data transfer is performed by one internal clock
- a horizontal synchronization signal (latch pulse) is generated by 160 internal clocks
- a vertical synchronization signal is generated by 240 horizontal clocks. Can be generated.
- FIG. 6A is a block diagram of one embodiment of the frequency divider circuit 223 used in the present invention
- FIG. 6A is a block diagram of one embodiment of the counter circuit 224 used in the present invention. The diagrams are shown in Fig. 6 (B).
- the counter circuit 224 in FIG. 6B is composed of presettable counters PSC 1 and PSC 2 and timing circuits T 1 and T 2, and has an internal clock 23 4 (normally about 2 . 5 MHz) to the presettable counter PSC1.
- New paper After counting the number set by preset terminal 1, outputs LP1 signal.
- the preset terminal 1 is set to binary "H” level or "L” level according to the number to be counted.
- the LP signal is input clock after 127 counts. Output minutes.
- the timing circuit Tl, ⁇ 2 in Fig. 6 (B) outputs “H” level at the rising edge of the input signal, and outputs “L” level at the rising edge of the B input signal. Circuit.
- the presettable counter PSC1 is reset at the rising edge of the clock CK when the reset signal is at the "H" level.
- a signal FLM1 is generated by a presettable counter PSC2 using LP.1 as a clock.
- CP1 is a pseudo signal for data transfer
- LP1 is a pseudo signal for line scanning and corresponds to a horizontal synchronization signal.
- FLM1 is a pseudo signal for changing the plane and corresponds to a vertical synchronizing signal.
- the synchronous signal switching circuit 225 is provided with a normal driving signal 2 1 for the liquid crystal display means 107 output from the display image generating means 103 in response to the output 230 from the standby start switching circuit 222. 7 and the liquid crystal display means output from the counter circuit 2 2 4
- the pseudo drive signal 2 31 is switched and supplied to the liquid crystal display means 107 as a drive signal 2 18.
- the normal drive signal 217 output from the display image generating means 103 is supplied to the liquid crystal display means 107, and in the low power consumption mode. Then, the pseudo drive signal 231 output from the counter circuit 224 is supplied to the liquid crystal display means 107.
- the code data stored in the first image display storage unit is stored in the liquid crystal display unit 10 even in the normal power consumption mode.
- the fixed image data stored in the display data storage memory 208 which is the second image display storage means, can always be displayed.
- the synchronization signal switching circuit 2 25 becomes unnecessary.
- the data switching circuit 2 26 is connected to the first image display storage means 104 output from the display image generating means 103 in accordance with the output 23 6 from the standby start switching circuit 22 22.
- An operation for switching between a signal 2 16 indicating the stored display image data and a signal 2 20 indicating the fixed display image data stored in the second image display storage means 208 is performed.
- the data stored in the first image display storage means 104 is supplied to the liquid crystal display means 107 as display image data 219
- the fixed display image data stored in the second image display storage means 208 is used as the display image data 219 as the liquid crystal display means 107. It is supplied to.
- the code data stored in the first plane image display storage means is displayed on the liquid crystal display means 107 even in the normal power consumption mode. It is also possible to always display the fixed plane image data stored in the display data holding memory 208, which is the second image display storage means, without performing this operation. The switching circuit 2 26 becomes unnecessary.
- a signal generation plane for a retained memory 207 is provided as equivalent to the memory control circuit 207 in the specific example of FIG. Converts the display image data stored in the first plane image display storage means 104 in response to the signal 2 17 output from the display plane image generation means 103.
- the second image display storage means that is, a synchronization signal 2 32 for writing to the display data holding memory 208 using the image data signal 2 16 output from the second plane image display storage means 2 is used.
- a synchronization signal 2 3 3 for reading out the surface image data from the second image display storage means 2 8 is output in response to the control signal 2 3. Then, an output is made to the second plane image display storage means 208.
- the display surface image data stored in the second image display storage means 208 is supplied to the liquid crystal display means 107 via the data switching circuit 226. .
- FIG. 7A shows a block diagram of a specific example of the signal generating circuit 207 for the holding memory, which is the second image display storage means used in the liquid crystal display device according to the present invention.
- FIG. 7 (B) shows a block diagram of a specific example of the synchronous signal switching circuit 222 used in the liquid crystal display device in the present invention.
- Reference numeral 7 denotes a flip-flop, an AND gate circuit, an inverter circuit, and the like, as shown in Fig. 7 (A).
- the output signal 239 from the switching circuit 222 is at the "L" level
- the signal FLM rises to the "H" level at the rising edge of the signal FLM, and the output signal 239 is at the "H” level.
- Signal FLM rises to "L” level under the condition To output the WE.
- the inverted signal is referred to as a read enable signal RE.
- the read enable signal RE is fixed at the "H" level.
- the signal R STW based on the signal FLM and the signal SWCK based on CP are output.
- a signal R STR based on the signal FLM1 and a signal SRCK based on the CP1 are output.
- the signal RS TW is a memory address for writing data. This is a reset signal, and the signal SWCK is a data transfer signal for write data.
- the signal R STR is a memory address reset signal for reading data
- the signal SRCK is a data transfer signal for reading data.
- the periodic signal switching circuit 225 usable in the present invention is composed of multiplexers MP1 to MP3,
- the synchronizing signal 2 17 from the controller 103 and the pseudo synchronizing signal 2 31 output from the counter circuit 2 24 are output from the holding memory signal generating circuit 2 07 via the multiplexers MP 1 to MP 3. Switch according to the output control signal 2 2 3 6.
- the multibrixer MP 1 When the control signal 2 36 is at the “H” level, the multibrixer MP 1 outputs the signal FLM 1 as the signal F LMM, and when the control signal 2 36 is at the “L” level, the signal F LMM is output. Outputs signal FLM.
- control signal 236 is always fixed at the “H” level.
- the signal FLM is a screen change signal (corresponding to a vertical synchronization signal)
- the signal LP is a row scanning signal (corresponding to a horizontal synchronization signal)
- the signal CP is a data transfer signal.
- the signal is -
- the liquid crystal display means 107 that can be used in this specific example is not particularly limited, and a liquid crystal display device that is usually commercially available is used.
- VGA 640 X Liquid crystal display means such as 480 pixels 320 Kbits
- IBM CGA 640 x 200 pixels 130 Kbits
- the display image generating means 103 used in the present invention is, for example, Cirrus You can use CL-1 GD 610 020 (Standby mode) or CHIPS 822 C4555 (Relax mode).
- the configuration of the central processing unit (CPU) used in the present invention is not particularly limited, and a known commercially available CPU can be used. It is possible to use 803 886 made by the company.
- the configuration of the display storage means 208 is not particularly limited, and a well-known commercially available memory may be used.
- Company's FIFO memory ⁇ ⁇ 3 ⁇ 5 1 4 2 2 1 ⁇ (1 ⁇ ) ⁇ ⁇ 5, 100 kbits) or Texa Twin Instrument's FIFO memory TMS 4 C 1 0 5 0 (l Mb its, 1 0 0 0 kbits) can be used.
- the configuration of the first image display storage means 104 used in the present invention is not particularly limited, and a known commercially available memory may be used.
- a known commercially available memory may be used.
- ordinary dynamic memory may be used.
- RA can be used.
- FIG. 4 shows a third specific example of the liquid crystal display device according to the present invention.
- 3 ⁇ 4 ⁇ nana paper It has basically the same configuration as the liquid crystal display device shown in FIG. 3, but the display image generation 103 is controlled by software to change the power consumption mode. This is an example of how the work is performed.
- a data access circuit 244 is newly provided, and the data access circuit 244 is newly provided with the address bus 202 and the central processing means 101. And a data bus 246 provided between the display image generating means 103 and the display image generating means 103.
- the address is changed.
- the data access circuit 244 periodically detects the address based on the software. For example, if the specified address does not reach the specified number of times within a unit time, the data access circuit 244 according to the result. A predetermined output is output to the data bus 246, and the power consumption mode of the display image generating means 103 is changed.
- FIG. 8 (A) A block diagram of a specific configuration example of the data access circuit 244 used in the above specific example of the liquid crystal display device according to the present invention is shown in FIG. 8 (A).
- the data access circuit 24 is composed of a decode circuit D2 and a tristate buffer circuit TSB. Accordingly, if the address bus 102 is decoded to have an arbitrary address, the gate signal output from the decoding circuit D2 is set to the “H” level, and the signal is received.
- the tri-state buffer circuit TSB opens the gate and transmits the control signal 236 to the data buffer.
- the power consumption mode switching operation described above is executed via the newly provided data bus 246.
- the decoding is performed in response to a signal 238 generated when reading the I0 storage space.
- FIG. 8 (B) shows the output 235 of the address bus decoding circuit 205 in the liquid crystal display device according to the present invention, and the display controller / standby start switching circuit 22. Waveforms of the output signal 239 from 2 and the output signal 236 from the holding memory signal generation circuit 207 and the screen change signals FLM, FLM1 and the write enable signal WE, The waveform of the enable signal RE is shown.
- the output signal 235 of the address bus decode circuit 205 becomes "H" level.
- the output signal 239 from the display controller / standby start-up switching circuit 222 becomes “L” at the same time as the output 235 of the address bus decoding circuit 205 becomes “H” level.
- the level returns to the "H” level after the specified number of pseudo signals FLM1 have been counted.
- the write enable signal WE is output at the rising edge of the screen change signal FLM when the output signal 239 from the display controller / standby startup switching circuit 222 is at the "L” level. H level and signal 2 39 is at "H" level
- the read enable signal RE is an inverted state of the write enable signal WE or a state where the "H" level is maintained.
- the output signal 236 from the holding memory signal generation circuit 207 is obtained by taking AND of the signal 239 and a signal obtained by inverting the write enable signal WE.
- the display controller 'standby start switching circuit 2 2 2 It means that it is driving.
- image data based on the data stored in the first plane image display storage circuit 104 output from the display image generation circuit 103 is output to the display image generation circuit.
- the fixed plane image data stored in the second image display storage circuit 208 is newly generated in the pseudo signal control generation circuit 206 in the pseudo synchronization signal.
- the fixed image data stored in the second image display storage circuit 208 is generated by the newly generated pseudo synchronization.
- the first image output from the display image generating circuit 103 is displayed on the display element 107 continuously in accordance with a signal or a synchronization signal output from the display image generating circuit 103.
- Detecting means 108 for detecting access by the central processing unit (CPU) 101 of the first image display storage circuit 104 or display image generating circuit 103, 08.
- CPU central processing unit
- a central processing unit (CPU) 101 is provided with a detection means 108 for detecting an interrupt signal to the 101, and the normal power consumption display mode and the low power consumption mode are provided in accordance with the detection frequency by the detection means 108. Electric power How to switch the display mode.
- Detecting means 108 detecting the access of the first image display memory circuit 104 or the display image generating circuit 103 by the central processing unit (CPU) 101, and low power consumption. A method of stopping and driving the CPU 101 or switching the driving frequency according to the detection frequency of the detection means 108 together with the display mode.
- CP according to the detection frequency by the above detection means 108 ⁇ Stop and drive 101, or switch the drive frequency.
- the fixed image data stored in the second plane image display storage circuit 208 is generated in accordance with the pseudo synchronization signal generated in the pseudo signal control generation circuit 206.
- the image data output from the display surface image generation circuit 103 is stored in a second image display storage circuit 208 in accordance with the synchronization signal.
- the current of the entire liquid crystal display device is divided into three of a system section S current ⁇ , a display section current ⁇ , and a holding current C, and the relationship with time t is considered. become. If no power is saved, the current of A + B + C is always flowing.
- the system unit (which is about four times the display unit), which accounts for the largest percentage, can save power by shutting it down as required by software and users. In fact, there are several products that use OS detection and bus detection. Ideally A schematic diagram of Fig. 16b shows the case where the stem was finely stopped according to the needs of the software and the user to save power.
- the effect of the display section power saving on the entire system will be significant.
- the power saving of the system section alone can limit the operation time of the entire system to several times, but if the power saving of the display section is performed, it will be doubled.
- this system provides a method of reducing the current display on the display unit without erasing it.
- the holding memory circuit 208 in the normal mode, the holding memory circuit 208 is used while the LCD data 219 output from the display image generating circuit 103 in FIG. 2 is displayed according to the LCD synchronization signal 218.
- LCD data 219 is stored in the memory, and in the power saving mode, as shown in FIG. 2, the display image generation circuit 1 requires a large amount of power because it performs calculations based on the data in the VRAM 104. 0 3 is stopped, and the LCD holding data 220 in the holding memory circuit 208 that requires only a small amount of power is repeatedly displayed.
- Fig. 9 shows a block diagram of the embodiment in normal mode based on the above usage method (1).
- the CPU 101 corresponds to a central processing unit such as 80C88 of Intel Corporation.
- VRAM Reference numeral 104 denotes a video memory using a dynamic memory or the like used in a microcomputer as is well known, and corresponds to a first image display storage circuit.
- the holding memory circuit 208 is a circuit including a storage circuit element using a dynamic circuit or the like capable of storing an LCD data, and is a second surface image display memory circuit for fixed image display. Equivalent to 8.
- the display controller 103 is a microcomputer circuit called a normal VGA controller or the like, and serves as the display image generation circuit 103.
- the image circuit 106 performs central control of the present system and corresponds to a display image data control circuit.
- the LCD circuit 107 is a display circuit including a liquid crystal display and corresponds to a display element.
- the CPU 101, the display controller 103, and the VRAM 104 are connected by an address bus 102.
- the display controller I 03 scans the contents of the VRAM 104, performs a predetermined operation, converts the resulting image data to LCD, outputs LCD data 216, and simultaneously drives the LCD. Output the LCD synchronization signal 2 17 for
- the display image data control circuit 106 transfers the LCD data 219 and the LCD synchronization signal 218 to the LCD circuit 107, during which the LCD data 209 and the LCD synchronization signal 218 are transferred.
- the holding memory circuit 208 stores the LCD data 219 from the display image data control circuit 106 in the memory according to the LCD synchronization signal 218.
- LCD circuit 107 synchronizes LCD data 219 from display image data control circuit 106 with LCD. Display on LCD 107 according to signal 218. Note that the transfer of the LCD data 219 and the LCD synchronization signal 218 from the display image data control circuit 106 to the holding memory circuit 208 may always be performed, or the transfer immediately before entering the power saving mode. The content is fine.
- FIG. 10 is a block diagram of the embodiment in the power saving mode based on the method of use (2) of the present invention.
- the display controller 103 is stopped.
- the display image data control circuit 106 generates the pseudo synchronizing signal 2 18 and transfers it to the LCD circuit 107, and at the same time, the data is stored in the holding memory circuit 208 in synchronization with the pseudo synchronizing signal 2 18 LCD hold data 220 is repeatedly transferred to LCD circuit 107.
- the LCD circuit 107 displays the LCD holding data 220 from the pseudo signal generation circuit 206 of the display image data control circuit 106 on the LCD in accordance with the pseudo LCD synchronization signal 218.
- Fig. 11 shows a block diagram of the embodiment when switching from the power saving mode to the normal mode based on the method of use (3) of the present invention.
- the display controller 103 is driven to drive the VR.
- the contents of AM104 are scanned, a predetermined operation is performed, and the resulting image data is converted to LCD data and LCD data 216 is output.
- the control circuit 106 generates the pseudo-sync signal 2 18 and transfers it to the LCD circuit 107, and at the same time, holds the memory circuit in synchronization with the pseudo-sync signal 2 18 LCD stored in 208
- the held data 220 is repeatedly transferred to the LCD circuit 107.
- the LCD circuit 107 displays the LCD holding data 220 from the display image data control circuit 106 on the LCD 107 in response to the pseudo LCD synchronization signal 218. This is the period from when the display controller 103 is driven to the time when it operates normally, the period during which the display controller 103 is driven and the display is performed in the power saving mode, and the synchronization signal to the LCD circuit 107. This is because there must be a period to match the timings of the two.
- Fig. 12 shows a block diagram of the method (4) for switching from normal mode to power saving mode.
- the display controller 103 is driven to scan the contents of the VRAM 104, a predetermined operation is performed, the resulting image data is converted to LCD data, and the LCD data 211 is output. At the same time, it outputs an LCD synchronization signal 2 17 for driving the LCD.
- the display image data control circuit 106 generates the pseudo synchronizing signal 218 and transfers it to the holding memory circuit 208.
- the LCD circuit 107 displays the LCD data 216 from the display image data control circuit 106 on the LCD according to the LCD synchronization signal 217.
- FIG. 13 is a block diagram of an embodiment for determining whether to switch between the power saving mode and the normal mode, which is the method of use (5) according to the present invention. Success
- Is a decision circuit that detects interrupts 1 0 8 is an address bus 1 0.2 And monitor the interrupt signal INTR 503 to the CPU 101 and determine that there is no change in the display, output the signal to switch the display to the power saving mode as the determination signal 502, and If it is determined that there is, a signal for setting the display to the normal mode is output as the determination signal 502.
- the criterion is the frequency of access to the VRAM 104, the frequency of INTR, and the like.
- the switching is performed in a hardware manner in accordance with the determination signal 502, but it is of course possible to provide a register inside the determination circuit to periodically perform the detection and then perform the software switching.
- FIG. 14 is a block diagram of another embodiment for determining whether to switch between the power saving mode and the normal mode, which is the method of use (6) according to the present invention.
- the monitoring circuit 602 monitors the address bus and the interrupt signal INTR 503 to the CPU, and if it determines that there is no change in the display, sets the signal for setting the display to the power saving mode as the determination signal 504. Output, and if it is determined that there is a change in the display, a signal for setting the display to the normal mode is output as the determination signal 504.
- the monitoring circuit 602 monitors the address bus and the interrupt signal INTR to the CPU, and if it determines that there is no change in the input, determines the signal for putting the CPU into the power saving mode as the determination signal 506.
- the criterion is the frequency of access to the input / output function in the OS in the software, in addition to what has been described in the above specific example.
- FIG. 15 is a diagram for explaining a method of use (7) based on the liquid crystal display device according to the present invention. That is, in this specific example, the central processing unit 101, the first image display and storage circuit 104, the second image display and storage circuit 208 for fixed display of the surface image, the display surface image generation circuit 103, the display In a liquid crystal display device having a control circuit 106 and a display element 107 and having a normal power consumption display mode and a low power consumption display mode, a fixed surface stored in the second image storage circuit 208 Image data is displayed on the display element 107 in accordance with a pseudo synchronization signal newly generated from the display control device, and the first image display storage circuit 1 output from the display surface image generation circuit 103 All the image data based on the data stored in the storage device 04 is stored in the second image display storage device 208.
- the signal system to the LCD circuit 107 is a set of the LCD data 108, the LCD synchronization signal 109, the LCD holding data 202, and the pseudo synchronization signal 201. Since the input is switched, the image circuit 105 becomes complicated. Therefore, when the display controller 103 returns to the normal operation due to a change in the contents of the VRAM 104, etc., the LCD data 210 is stored in the holding memory circuit 208, and at the same time the holding memory The contents of 208 continue to be transferred to LCD circuit 107. That is, the signal system to the LCD circuit 107 is always only one set of the set of the LCD holding data 220 and the pseudo sync signal 218.
- the conventional low-power display system can be further simplified.
- the drive signal from the display controller 103 is switched from the drive signal 217 to the pseudo drive signal 218 In this case, or conversely, when switching from the pseudo drive signal 218 to the drive signal 217 from the display controller, there is a problem that the display flickers.
- a flicker prevention circuit 700 for stopping the display of the liquid crystal display element when switching between the normal power consumption mode and the low power consumption mode is provided. It is characterized by stable display without flicker.
- Fig. 17 shows a block diagram of the system according to this example.
- the flicker prevention circuit 700 uses the drive signal 817 from the display controller 103 when the power-off mode switching signal 8122 changes from the mouth level to the high level.
- An LCD stop period A7077 (Fig. 18) is generated during switching to the display by the pseudo drive signal 818, and the signal 812 changes from the high level to the low level.
- the LCD stop period B 7 17 (Fig. 19).
- FIG. 18 shows a timing chart when switching from display by the drive signal 817 from the display controller 103 to display by the pseudo drive signal 818.
- the LCD vertical synchronizing signal 70 1 is a vertical synchronizing signal for driving the LCD from the display controller 103.
- the pseudo vertical synchronizing signal for LCD 700 is LC when the display controller 103 is stopped. This is a vertical synchronization signal for D drive.
- the LCD drive signal with stop period / LCD pseudo drive signal 705 means a signal generated from the display controller 103 for driving the LCD.
- the LCD drive stop permission signal A703 is used only when the level is high to permit switching from display by the drive signal & 17 from the display controller 103 to display by the pseudo drive signal 818.
- This signal can rise at any timing to the high level, but falls to the low level in synchronization with the pseudo-vertical synchronization signal for LCD 702.
- the LCD drive stop signal A704 is the rising edge of the LCD vertical sync signal 701, and the LCD pseudo vertical sync signal 702 under the condition that the LCD drive stop enable signal A703 is high level. This signal is at the high level during the rising edge of. Then, while the CD drive stop signal A704 is at a high level, the LCD drive stops.
- 706 is the LCD display period by the LCD drive signal
- 708 is the LCD display period by the pseudo LCD drive signal
- 707 is the LCD drive period by the drive stop signal A 704 in c here showing the stop period, if increasing the frequency of the pseudo vertical synchronizing signal 7 0 2, LCD drive halt period a 7 0 7 is shortened. .
- FIG. 19 shows a timing chart of the embodiment in the case of switching from the display by the pseudo drive signal 818 to the display by the drive signal 817 from the display controller.
- the LCD drive stop permission signal B 711 is high only when the LCD drive signal from the display controller is used. This signal allows the display to be switched to a high-level display. It can be started at any time at the high level, but falls at the low level in synchronization with the LCD vertical synchronization signal 701.
- the LCD drive stop signal B 7 1 2 is the rising edge of the LCD pseudo vertical synchronization signal 7 0 2 and the L CD ⁇ vertical synchronization signal 7 0 under the condition that the LCD drive stop enable signal B 7 1 1 is at the high level. This signal is high during the rising edge of 1.
- the drive stop signal B 712 for CD is at a high level, the drive stop period B 717 for LCD is set.
- the LCD drive stop enable signal The rising edge of the LCD pseudo vertical synchronization signal 702 must be included during the high-level period of B711, that is, the LCD pseudo vertical synchronization signal 7202 A precondition is that the frequency is higher than the frequency of the vertical synchronization signal for LCD 701. Further, by delaying the rise of the LCD drive stop permission signal B711, the high level period of the LCD drive stop signal B711 can be reduced. However, at this time, at least the drive stop permission signal B 7 for CD must be included in order to always include the rising edge of the pseudo vertical synchronizing signal 70 2 for LCD while the drive stop permission signal B 7 11 for LCD is at high level. 11 During the period from the rising edge of 1 to the rising edge of the pseudo vertical synchronizing signal for LCD 702, it is necessary to increase the frequency of the pseudo vertical synchronizing signal for LCD 702.
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
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Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69228929T DE69228929T2 (de) | 1992-02-25 | 1992-02-25 | Flüssigkristallanzeige |
EP92905102A EP0584358B1 (en) | 1992-02-25 | 1992-02-25 | Liquid crystal display device |
US08/039,247 US5864336A (en) | 1992-02-25 | 1992-02-25 | Liquid crystal display device |
PCT/JP1992/000200 WO1993017380A1 (en) | 1992-02-25 | 1992-02-25 | Liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP1992/000200 WO1993017380A1 (en) | 1992-02-25 | 1992-02-25 | Liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
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WO1993017380A1 true WO1993017380A1 (en) | 1993-09-02 |
Family
ID=14042190
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1992/000200 WO1993017380A1 (en) | 1992-02-25 | 1992-02-25 | Liquid crystal display device |
Country Status (4)
Country | Link |
---|---|
US (1) | US5864336A (ja) |
EP (1) | EP0584358B1 (ja) |
DE (1) | DE69228929T2 (ja) |
WO (1) | WO1993017380A1 (ja) |
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JP2002140052A (ja) * | 2000-08-23 | 2002-05-17 | Semiconductor Energy Lab Co Ltd | 携帯情報装置及びその駆動方法 |
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Also Published As
Publication number | Publication date |
---|---|
DE69228929D1 (de) | 1999-05-20 |
EP0584358A1 (en) | 1994-03-02 |
US5864336A (en) | 1999-01-26 |
EP0584358B1 (en) | 1999-04-14 |
DE69228929T2 (de) | 1999-12-02 |
EP0584358A4 (en) | 1995-03-01 |
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