JP5138296B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5138296B2 JP5138296B2 JP2007181020A JP2007181020A JP5138296B2 JP 5138296 B2 JP5138296 B2 JP 5138296B2 JP 2007181020 A JP2007181020 A JP 2007181020A JP 2007181020 A JP2007181020 A JP 2007181020A JP 5138296 B2 JP5138296 B2 JP 5138296B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- power supply
- display
- display memory
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 31
- 238000001514 detection method Methods 0.000 claims description 6
- 230000003247 decreasing effect Effects 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000013507 mapping Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Power Sources (AREA)
- Memory System (AREA)
Description
12 表示用メモリ
13a、13b メモリ用電源部
14 バイアス回路
15 ソースドライバ
16 電圧選択回路
C1 容量素子
CLK、DATA 端子
MAW メモリ書き込み信号
MAR メモリ読み出し信号
RCK メモリ読み出しクロック
RD、WD 表示データ
RVDD、VCC 電源
WCK メモリ書き込みクロック
Claims (6)
- 表示用メモリと、該表示用メモリの制御用の論理回路とを含む半導体装置であって、
前記論理回路への電源とは別に前記表示用メモリへ電源を供給する電源回路を備え、
前記電源回路は、前記論理回路による前記表示用メモリへのアクセス状態に応じて、電源の駆動能力を可変とし、(1)前記表示用メモリへの書き込みおよび読み出しを同時に行う場合、(2)前記表示用メモリへの書き込みのみを行う場合、(3)前記表示用メモリへの読み出しのみを行う場合、(4)前記表示用メモリへの書き込みおよび読み出しのいずれも行わない場合、(1)(2)(3)(4)または(1)(3)(2)(4)の順に前記電源の駆動能力を下げるように構成することを特徴とする半導体装置。 - 前記電源回路は、前記電源の駆動能力を下げる場合にバイアス電流を下げることを特徴とする請求項1記載の半導体装置。
- 前記論理回路における前記表示用メモリへのアクセス信号を検出し、検出結果に基づいて前記電源回路のバイアスを制御するバイアス回路を備えることを特徴とする請求項2記載の半導体装置。
- 前記電源回路は、前記電源の駆動能力を下げる場合に前記表示用メモリへの電源電圧を下げることを特徴とする請求項1記載の半導体装置。
- 前記論理回路における前記表示用メモリへのアクセス信号を検出し、検出結果に基づいて前記電源回路における前記電源電圧を制御する電圧選択回路を備えることを特徴とする請求項4記載の半導体装置。
- 請求項1乃至5のいずれか一に記載の半導体装置を含む表示装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007181020A JP5138296B2 (ja) | 2007-07-10 | 2007-07-10 | 半導体装置 |
US12/216,671 US8117472B2 (en) | 2007-07-10 | 2008-07-09 | Semiconductor device |
CN200810130476.1A CN101345042B (zh) | 2007-07-10 | 2008-07-10 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007181020A JP5138296B2 (ja) | 2007-07-10 | 2007-07-10 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009020183A JP2009020183A (ja) | 2009-01-29 |
JP5138296B2 true JP5138296B2 (ja) | 2013-02-06 |
Family
ID=40247036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007181020A Expired - Fee Related JP5138296B2 (ja) | 2007-07-10 | 2007-07-10 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8117472B2 (ja) |
JP (1) | JP5138296B2 (ja) |
CN (1) | CN101345042B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6057462B2 (ja) * | 2013-01-24 | 2017-01-11 | シナプティクス・ジャパン合同会社 | 半導体装置 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60164237U (ja) * | 1984-03-30 | 1985-10-31 | セイコーエプソン株式会社 | 小型携帯電子機器 |
US5864336A (en) * | 1992-02-25 | 1999-01-26 | Citizen Watch Co., Ltd. | Liquid crystal display device |
JPH06139773A (ja) * | 1992-10-29 | 1994-05-20 | Hitachi Ltd | 半導体集積回路 |
KR950005216B1 (ko) * | 1993-03-31 | 1995-05-22 | 삼성전자주식회사 | 컴퓨터 주변장치의 전원절약장치 |
JP3437701B2 (ja) * | 1996-01-31 | 2003-08-18 | 株式会社東芝 | 電子機器 |
US6301671B1 (en) * | 1998-03-23 | 2001-10-09 | International Business Machines Corporation | Apparatus and method for power reduction control in a video encoder device |
JP2000132283A (ja) * | 1998-10-21 | 2000-05-12 | Nec Corp | 半導体記憶装置の消費電力低減方法 |
US6657634B1 (en) * | 1999-02-25 | 2003-12-02 | Ati International Srl | Dynamic graphics and/or video memory power reducing circuit and method |
JP2002072990A (ja) * | 2000-06-12 | 2002-03-12 | Sharp Corp | 画像表示システム及び表示装置 |
US7155625B2 (en) * | 2001-05-09 | 2006-12-26 | Intel Corporation | Method and apparatus to modify power requirements for a system |
JP3596507B2 (ja) | 2001-09-28 | 2004-12-02 | ソニー株式会社 | 表示メモリ、ドライバ回路、及びディスプレイ |
US7176864B2 (en) * | 2001-09-28 | 2007-02-13 | Sony Corporation | Display memory, driver circuit, display, and cellular information apparatus |
JP3882642B2 (ja) | 2002-03-01 | 2007-02-21 | 株式会社日立製作所 | 表示装置及び表示用駆動回路 |
US7114084B2 (en) * | 2002-03-06 | 2006-09-26 | Micron Technology, Inc. | Data controlled programmable power supply |
KR100945577B1 (ko) | 2003-03-11 | 2010-03-08 | 삼성전자주식회사 | 액정 표시 장치의 구동 장치 및 그 방법 |
JP4033066B2 (ja) * | 2003-05-07 | 2008-01-16 | ソニー株式会社 | 周波数制御装置、情報処理装置、周波数制御方法及びプログラム |
AU2003252366A1 (en) * | 2003-08-04 | 2005-02-15 | Sharp Kabushiki Kaisha | Power source device and communication system |
JP4731195B2 (ja) * | 2005-04-07 | 2011-07-20 | ルネサスエレクトロニクス株式会社 | 液晶表示装置、液晶ドライバ、及び液晶表示パネルの駆動方法 |
KR100790035B1 (ko) * | 2005-08-31 | 2008-01-02 | 엘지전자 주식회사 | 전원제어장치 및 방법 |
JP4077847B2 (ja) * | 2005-10-07 | 2008-04-23 | トヨタ自動車株式会社 | 複数枚の回路基板を固定する固定部材とそれを利用したモジュール |
JP4840908B2 (ja) * | 2005-12-07 | 2011-12-21 | ルネサスエレクトロニクス株式会社 | 表示装置駆動回路 |
-
2007
- 2007-07-10 JP JP2007181020A patent/JP5138296B2/ja not_active Expired - Fee Related
-
2008
- 2008-07-09 US US12/216,671 patent/US8117472B2/en not_active Expired - Fee Related
- 2008-07-10 CN CN200810130476.1A patent/CN101345042B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101345042B (zh) | 2014-10-29 |
US20090019297A1 (en) | 2009-01-15 |
JP2009020183A (ja) | 2009-01-29 |
CN101345042A (zh) | 2009-01-14 |
US8117472B2 (en) | 2012-02-14 |
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