WO1993013474A1 - Circuit de collecte de donnees comportant une unite de calcul centrale et un convertisseur analogique-numerique - Google Patents

Circuit de collecte de donnees comportant une unite de calcul centrale et un convertisseur analogique-numerique Download PDF

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Publication number
WO1993013474A1
WO1993013474A1 PCT/DE1992/001051 DE9201051W WO9313474A1 WO 1993013474 A1 WO1993013474 A1 WO 1993013474A1 DE 9201051 W DE9201051 W DE 9201051W WO 9313474 A1 WO9313474 A1 WO 9313474A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
input
analog
switching means
control device
Prior art date
Application number
PCT/DE1992/001051
Other languages
German (de)
English (en)
Inventor
Bernhard Mattes
Hartmut Schumacher
Norbert Crispin
Werner Nitschke
Wolfgang Drobny
Otto Karl
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE9115849U external-priority patent/DE9115849U1/de
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO1993013474A1 publication Critical patent/WO1993013474A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B60—VEHICLES IN GENERAL
    • B60R—VEHICLES, VEHICLE FITTINGS, OR VEHICLE PARTS, NOT OTHERWISE PROVIDED FOR
    • B60R16/00—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for
    • B60R16/02—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements
    • B60R16/03—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for supply of electrical power to vehicle subsystems or for
    • B60R16/0315—Electric or fluid circuits specially adapted for vehicles and not otherwise provided for; Arrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric constitutive elements for supply of electrical power to vehicle subsystems or for using multiplexing techniques
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/22—Means for limiting or controlling the pin/gate ratio
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
    • G—PHYSICS
    • G08—SIGNALLING
    • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
    • G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
    • G08C15/06—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division

Definitions

  • a large number of analog signals are often to be recorded and processed in electronic control devices, in particular for motor vehicle applications.
  • So-called single-chip circuits (MCU) are often used for signal processing, which usually only have a maximum of eight analog-digital input channels, which are queried internally in a multiplexed manner.
  • the computing effort for real-time polling of the analog inputs is very high for the central processing unit (CPU) of the circuit.
  • CPU central processing unit
  • the user is faced with the decision to use a further single-chip circuit or a further analog multiplexer without the larger number then available to be able to take full advantage of input connections.
  • Such a solution also has the disadvantage that the additional components require additional space and that the additional components require additional energy. Particularly when the components are packed very densely, this can also cause problems in dissipating the power loss.
  • the electronic circuit comprises, in addition to a central processing unit and an A / D converter ( ⁇ nalog / digital converter), internal switching means 22 for controlling external switching means which influence the analog input lines.
  • a / D converter ⁇ nalog / digital converter
  • an external multiplex device is provided, which is connected on the input side to a multiplicity of analog lines and on the output side to an analog input line of the electronic circuit, the multiplex device being controllable by the internal switching means.
  • At least one analog / digital input connection Ai, i-1-8 of the circuit is connected via a resistor network to a plurality of controllable digital output connections of the switching means 22, the digital output connections being such it is controllable that a plurality of input connections can be connected in succession to the at least one input connection for analog signals.
  • the resistance network has at least two branches connected to the Ai, each branch in turn consisting of a series connection of at least two resistors.
  • One controllable digital output of the circuit is connected to one tap of each of these branches of the resistance network.
  • a corresponding number of branches of the resistance network connected to an analog / digital input Ai, (i-1-8), the taps of which are each connected to a digitally controllable output connection of the processor make them larger Number of input connections for analog signals provided.
  • FIG. 1 shows a first exemplary embodiment of an electronic circuit with internal switching means
  • FIG. 2 shows a first exemplary embodiment of an electronic device equipped with this circuit
  • FIG. 3 and FIG. 4 shows exemplary embodiments of electronic devices with resistance networks connected on the input side.
  • FIG. 2 shows a schematically illustrated electronic circuit 2 which, in addition to a conventional central processing unit 20 and an analog / digital converter (A / D converter) 21, additionally comprises switching means 22 which can be controlled by the central processing unit 20. Externally arranged circuit parts 23, 24 can be controlled via the switching means 22.
  • the switching means 22 connected to the circuit part 23 via a plurality of output lines 01, 02, 03.
  • the switching means 22 are still connected to the central processing unit 20 and the A / D converter.
  • the switching means 22 serves to influence input lines A1 to A8 carrying analog signals, as will be explained in more detail with reference to the following exemplary embodiments.
  • FIG. 2 shows a first exemplary embodiment of an electronic control unit 1 using the electronic circuit 2 explained with reference to FIG. 1, essentially in the form of a block diagram.
  • the electronic control unit 1 initially comprises the electronic circuit 2, which in turn comprises a central processing unit 20, an A / D converter 21, and switching means
  • Output lines 01 to 03 of the switching means 22 of the electronic circuit 2 are connected to a multiplex device 23 arranged externally, ie outside the electronic circuit 2.
  • the multiplex device is on the output side
  • the multiplexing device 23 connected via a line A1 to: an input connection of the A / D converter 21 arranged within the electronic circuit 2.
  • the multiplexing device 23 is connected via eight connecting lines A01 to A08 to output connections of a peripheral circuit 24 which supplies the multiplexing device 23 with analog signals via the connecting lines A01 to A08.
  • Further output connections of the peripheral circuit 24 are connected via connecting lines A2 to A8 to corresponding input connections of the A / D converter 21 arranged in the electronic circuit 2.
  • Line A1 with the corresponding input connection of the internal A / D converter 21 are connected.
  • the multiplexing device 23 is controlled by corresponding signals from the switching means 22 via the connecting lines 01 to 03.
  • the internally arranged A / D converter 21 has a total of only eight input channels A1 to A8, further analog signals supplied on lines A01 to A08 can be evaluated in this way.
  • This circuit arrangement relieves the central processing unit 20 of the electronic circuit 2 in real time. If the settling times of the supplied analog signals are to be waited for after switching on the multiplexing device 23 until the actual signal conversion of the analog to a digital signal begins, this can be effected by appropriate activation of the switching means 22.
  • Settling times can arise, for example, from the charging of capacitances provided for interference suppression or from switching processes of the multiplexing device 23.
  • the settling time to be waited for can expediently be predetermined by the circuit structure of the control means 22 or can be flexibly changed in software via the central computing unit 20, for example by influencing a corresponding control register.
  • the greatest advantage of such a circuit arrangement arises, for example, in the A / D conversion of a group of input signals on, for example, four successive or adjacent A / D channels, as will be shown below using an example.
  • the central computing unit 20 merely gives the switching means 22 the command to convert, for example, a group of four analog signals into corresponding digital signals.
  • the central processing unit 20 can initially turn to other tasks and is therefore not burdened with the conversion of the analog signals into digital signals.
  • the switching means 22 After receipt of the conversion command issued by the central processing unit 20, the switching means 22 first switch the multiplexing device 23 to channel A01 and then wait for a first settling time T01 before the A / D converter 21 begins the conversion of the analog signal present on the output side of the multiplexing device 23 on the connecting line A01 into a corresponding digital signal. The switching means 22 then wait until the end of the signal conversion. The result of the signal conversion is saved as result 01.
  • the switching means 22 control the multiplexing device 23 in such a way that it switches to channel A02 and the analog signal present at this input channel leads to the connection line A01 on the output side.
  • a necessary settling time T02 is first waited until the signal conversion is carried out by the A / D converter 21.
  • the switching means 22 wait for the signal conversion and save the result 02 of this signal conversion.
  • the switching means 22 then control the multiplexing device 23 in such a way that the analog signal present on the input line A03 is connected to the output-side connecting line A1. Possibly. a third settling time T03 is waited until the A / D converter 21 begins the signal conversion.
  • the switching means 22 wait for the end of the signal conversion and save the result 03 of the signal conversion.
  • FIG. 3 shows a schematically illustrated electronic control device 1, which comprises a single-chip circuit (MCU) 2.
  • the circuit 2 has eight input connections A1 to A8 for analog signals and at least two digitally controllable output connections 01, 02.
  • a / D converter analog / digital converter
  • a resistance network consisting of the resistors R1, R2, R3, R4 is connected to the input terminal A1 of the circuit 2.
  • the resistance network consists of two branches connected in parallel, each of which comprises a series connection of two resistors R1, R4 or R2, R3.
  • One tap of the series connection of the resistors R1, R4 or R2, R3 is connected to a digitally controllable output connection 01 or 02 of the switching means 22 of the circuit.
  • the unconnected connections of the resistors R1, R2 are available as input connections A11 or AI2 for input voltages Uli, U12.
  • a total of nine input connections A11, AI2 and A2 to A8 are available for analog input signals.
  • the operation of this embodiment can be described as follows. First of all, an analog input signal U11 lying at the input connection All is to be detected.
  • the digitally controllable output connection 02 of the switching means 22 of the circuit 2 is to be controlled such that it is at zero potential, that is to say it is conductively connected to the ground connection.
  • the digitally controllable output connection 01 of the switching means 22 of the circuit 2 remains in the tri-state, ie in a high-resistance state.
  • the analog input signal U11 is fed to the input terminal A1 of the circuit 2 via the resistance network.
  • the further analog input signal U11 possibly present at the input connection A12 has no influence on the input signal U11, since the output connection 02 of the circuit 2, as already mentioned above, is connected to the ground connection.
  • the Analog input signal U12 applied to input terminal A12 is detected and evaluated, the digitally controllable output terminal 01 of the switching means 22 is switched to ground, while the output terminal 02 remains in the tristate state, that is to say in a high-resistance state.
  • the analog input signal U12 is fed to the input terminal A1 of the circuit 2 via the resistance network.
  • the analog input signal U11 possibly present at the input connection A1 does not impair the input signal U12, since the digitally controllable output connection 01 of the circuit 2 is connected to ground.
  • FIG. 4 shows a further exemplary embodiment of the invention, in which, using a simple resistance network with resistors R1 to RN, R21 to R2N, an input connection A1 for analog input signals of the circuit 2 can be used N times. This means that a total of N analog input signals U11 to U1N can be applied to this input connection A1.
  • the resistor network R1 to R2N consists of a total of N branches connected to A1, which in turn consist of a series connection of two resistors R1 and R21, R2 and R22 to RN and R2N. Each connection point of the two resistors of each series circuit is connected to a digitally controllable output connection 0, 02 to ON of the switching means 22 of the circuit 2.
  • the analog input signal U11 applied to the input connection A11 is to be detected and evaluated.
  • all digitally controllable output connections 02 to ON of the switching means 22 are to be controlled in such a way that they are at zero potential, that is to say they are connected to the ground connection.
  • the digitally controllable output connection 01 should remain in the tristate state, that is to say in a high-ohmic state.
  • the analog signal Uli present at the input connection A11 is fed to the input connection A1 of the circuit 2 via the resistance network.
  • the analog input signals U12 to U1N possibly present at the further input connections A12 to A1N do not impair the input signal U11 to be detected and evaluated, since the digitally controllable output connections 02 to ON of the circuit 2 are connected to ground. Corresponding considerations apply to the acquisition and evaluation of the analog input signals U12 to U1N.
  • the resistors R1, R2, R3, R4 forming the resistance network in FIG. 1 are dimensioned such that R1 and R2 as well as R3 and R4 receive the same resistance value.
  • the resistors R1 and R2 have a value of approximately 10 Kohm and the resistors R3 and R4 have a value of approximately 45 Kohm.
  • the resistors R1, R2 ... RN of the resistor network can expediently also have the same resistance value, for example about 10 Kohm, while the resistors R21 to R2N also have the same value, for example 100 Kohm.
  • the simpler exemplary embodiment according to FIG. 3 is particularly suitable for the detection of analog input signals U11, U12 with lower demands on the resolution of the two channels leading to the input connections A11, A12.
  • the resolution of the A / D converter 21 of the circuit 2 is reduced accordingly by the best transfer factor 0.5 when the two channels (input connections A11, A12) are treated equally.
  • This can be greatly improved for a larger number of analog input signals to be recorded if the connection points of the resistors of the resistor network are provided by protective elements, such as, for example Zener diodes, which are arranged externally or in the circuit 2, are protected.
  • the division factor of the resistance network according to FIG. 3 could then be selected such that the range of values to be recorded for the analog input signals U11, U12 corresponds to the entire voltage reference range of the A / D converter.
  • a further improvement in the accuracy of the evaluation of the detected analog input signals can be achieved by applying a calibration voltage to the corresponding input connections, for example A11, AI2 according to FIG. 3, during the course of production of the electronic control unit 1, a corresponding adjustment factor then being achieved an interface is written from the outside into an EEPROM arranged in the circuit 2.
  • the resolution of the two channels opening at A11, A12 can be greatly improved if the reference voltage of the A / D converter 21 of the circuit 2 is reduced, for example by the controllable one, for measuring U11, U12 Digital output Or.
  • this sets the resistance network of Ra, Rb in FIG. 1 on one side of Rb to zero potential (ground), as a result of which the reference voltage Uref of

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Human Computer Interaction (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

Un appareil de commande électronique, notamment destiné aux applications dans le domaine des véhicules automobiles, comprenant un circuit monopuce (2), comporte un réseau de résistances (R1, R2, R3, R4) relié par des terminaux de sortie (01, 02) numériques. Ce qui permet d'exploiter de multiples façons au moins un terminal d'entrée (A1, A8) du circuit (2).
PCT/DE1992/001051 1991-12-20 1992-12-16 Circuit de collecte de donnees comportant une unite de calcul centrale et un convertisseur analogique-numerique WO1993013474A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE9115849U DE9115849U1 (fr) 1991-12-20 1991-12-20
DEG9115849.4U 1991-12-20
DE4231496 1992-09-21
DEP4231496.8 1992-09-21

Publications (1)

Publication Number Publication Date
WO1993013474A1 true WO1993013474A1 (fr) 1993-07-08

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Application Number Title Priority Date Filing Date
PCT/DE1992/001051 WO1993013474A1 (fr) 1991-12-20 1992-12-16 Circuit de collecte de donnees comportant une unite de calcul centrale et un convertisseur analogique-numerique

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DE (1) DE4242436C2 (fr)
WO (1) WO1993013474A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3498106B2 (ja) * 1995-05-12 2004-02-16 株式会社ルネサステクノロジ アナログ・ディジタル変換器
JPH1175269A (ja) * 1997-07-01 1999-03-16 Honda Motor Co Ltd 通信制御装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2052193A (en) * 1979-05-31 1981-01-21 Nissan Motor Data gathering system for automotive vehicles
EP0198425A2 (fr) * 1985-04-12 1986-10-22 Alcatel N.V. Système de transmission d'informations à large bande et à intégration de services

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184822A (ja) * 1982-03-31 1983-10-28 Fujitsu Ltd 入力回路
JP2623921B2 (ja) * 1990-06-05 1997-06-25 三菱電機株式会社 内燃機関の失火検出装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2052193A (en) * 1979-05-31 1981-01-21 Nissan Motor Data gathering system for automotive vehicles
EP0198425A2 (fr) * 1985-04-12 1986-10-22 Alcatel N.V. Système de transmission d'informations à large bande et à intégration de services

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
NOVELLINO J.: "VME BOARDS OFFER REAL-TIME DATA AQUISITION.", ELECTRONIC DESIGN., PENTON MEDIA, CLEVELAND, OH., US, vol. 37., no. 17., 10 August 1989 (1989-08-10), US, pages 81 - 83., XP000053722, ISSN: 0013-4872 *

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DE4242436A1 (en) 1993-06-24
DE4242436C2 (de) 2002-01-31

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