Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/681—Floating-gate IGFETs having only two programming levels
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
  • G06N3/00—Computing arrangements based on biological models
  • G06N3/02—Neural networks
  • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
  • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
  • G06N3/065—Analogue means
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
  • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
  • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
  • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
  • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
  • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
  • H03K2217/0036—Means reducing energy consumption

Definitions

• the present invention relates to a semiconductor device, and more particularly to providing a high-performance semiconductor integrated circuit device for realizing a neural network computer (neuron computer).
• a neural network computer neural network computer
• these logic circuits employ a method of performing operations using digital signals, that is, binary signals of “1” and “0”.
• digital signals that is, binary signals of “1” and “0”.
• the Neumann method is used.
• each instruction is executed according to a predetermined program.
• very high-speed calculations are possible for simple numerical calculations.
• Calculations such as force pattern recognition and image processing require a huge amount of time.
• they are very weak at information processing, which is also good at humans, such as association and learning.Thus, various software technology O researches are currently being conducted. It is not currently done.
• the human brain has an extremely complex structure, a force with a very high level of function. Its basic configuration is very simple. In other words, it is composed of neurons with arithmetic functions called neurons, and nerve fibers that transmit the operation results to other neurons, so to speak, function as wiring.
• Fig. 9 The structure of this brain 0D basic unit is simplified and drawn with a model (Fig. 9; 90, 90a, 901b, 901c are neurons, and 902a, 90 2 b, 90 2 c are nerve fibers, 90 3 a, 90 3 b, 90 3 c are called synaptic connections, for example, w is the signal transmitted through nerve fiber 90 2 a.
• the neuron 9001a takes a linear sum of the input signal intensities, and when the sum exceeds a certain threshold, the neuron is activated and the nerve fiber The signal is output to 90 2 b. The neuron does not output the signal when the total value is less than or equal to the threshold value.
• V, V 2, ⁇ '3 ,' ⁇ ', V n is the n input signals defined as, for example, the magnitude of the voltage corresponds to the signal transmitted from other neurons.
• v 9 , w 3 , ⁇ , w_ are coefficients that represent the strength of the connection between neurons, and are biologically called synaptic connections.
• Figure 10 (b) is a representation of the relationship between z and v QUT, when sufficiently large hearing than z is [nu tau is 1, sufficient '], when again outputs a 0.
• nMOS neuron MOSFET
• the present invention is an epoch-making technology that can perform the main function of the function of a neuron with only one transistor, and furthermore, can perform a power calculation directly on an electric signal, so that there is almost no power consumption.
• Fig. 11 (a) shows an example of a simplified MOS cross-sectional structure, where 1101 is a P-type silicon substrate, for example, and 112.103 is an N + diffusion layer.
• the gate insulating provided on a channel region layer (such as S i 0 2), 1 1 06 are electrically insulated potential floating gate one Bok in a floating state, 1 1 07, for example S i 0 2 insulating films and the like, (Ri G r G. G, N G) 1 1 08 corresponds to an input of an input gate neurons.
• FIG. 11 (b) is a further simplified drawing for explaining the operation. Assuming that the capacitance coupling coefficient between each input gate and the floating gate is c G and the capacitance coupling coefficient between the floating gate and the silicon substrate is, the potential Z of the floating gate is
• V 4 are respectively input gate GG 9.
• G 3 voltage being input to G 4
• the potential of the silicon substrate is 0 V, is ie ground I said
• the MOS is a conventional N-channel MOS transistor Looking at the floating gate Ichito the gate one Bok electrode, the threshold voltage (voltage on the substrate table surface and the rolling layer is formed) V ' ⁇ T as seen from the floating gate Assuming that ' W '", the above VMOS is turned on with ZZ >>" TTT ', and turned off with Z ⁇ Yjj ⁇ .
• the function of the neuron can be expressed simply by using one of these MOS 110 109 and constructing the same inverse circuit as in [1 (c)].
• 1 1 1 0, 1 1 1 1 1 are the resistors that constitute Invera
• the basic operation of firing the neuron when the input to the neuron is added at the voltage level and exceeds the linear sum value is realized by only one MOS. . Since voltage mode wiring is performed, the current flowing in the input section is only the charge / discharge voltage of the capacitor, and its magnitude is very small. On the other hand, in the inverter, a DC current flows when the neuron is fired. This is because the resistor 111 is used as a load, and the CMOS configuration according to the invention (Japanese Patent Application No. 11141463) is used. MOS If a MOS gate is used, The current can be eliminated.
• FIG. 12 is a drawing showing an example of a CMOS configuration.
• Fig. 12 (a) schematically shows the cross-sectional structure of a CMOS neuron gate, where 1201 is a P-type silicon substrate, 1202 is an n-type well, and 1203a and 1203b are: ⁇ ' + Source and drain, 1204a and 1204b are P + type source and drain, 1205 is a floating gate, and 1206a to 1206d are electrodes of input gate.
• FIG. 12B shows an example in which a single neuron circuit is configured.
• Reference numeral 1210 denotes a symbol for the CMOS neuron gate shown in FIG. It corresponds to the number.
• 1 2 1 1 is an inverter for CM ⁇ S
• 1 2 1 2 and 1 2 1 3 are NMOS transistors and PMOS transistors, respectively.
• 1214 has a small number of elements and one neuron can be constructed, as in the case of c or more which is the output of a neuron, and power consumption is very low. Therefore, MOS is an indispensable element for realizing a neuron computer. It is becoming.
• Fig. 13 shows an example of the basic configuration of a two-Euron circuit that uses a conventional M ⁇ S transistor and also includes a synaptic connection.
• 1301 is a neuron circuit as shown in FIG. 11 (c), for example, and 1302 is wiring for transmitting output signals of other neurons.
• Reference numeral 1303 denotes a synapse coupling circuit, which is a circuit for assigning a weight to an input signal.
• This is a source follower circuit in which a load resistor (R + R ..) is connected to the source 1306 of the NMOS transistor 1304. Therefore, when the output voltage V e of the ignited neuron is applied to the gate electrode 1305 of the NMOS transistor, the source 1 306 has
• a voltage of Y appears (where V TH is the threshold voltage of the NMOS Transistorsk 1304).
• Figure 14 (a) shows an example of a method for realizing a variable resistor. For example, if a constant voltage is applied to the gate of one MOS transistor 1441, this transistor functions as one resistor. By changing the value of, the resistance value can be changed.
• FIG. 2B shows an example of a circuit for controlling the value of, and is composed of a 4-bit binary counter 1402 and a DZA converter 144.
• the synaptic connection strength is expressed by a 4-bit binary number, which is converted to an analog voltage by the D / A converter 1403 and output as a value.
• the value of the counter may be reduced by the control signal and the value of may be reduced.
• to weaken the synaptic connection strength count up and increase the value of V.
• the problems in the case of using a synapse connection circuit not shown in FIGS. 13 and 14 will be described below.
• the first problem is that in Figure 13 the voltage is divided by resistors to generate weights. In this method, the current is always flowing through this resistor, so that the weighted output voltage is maintained, so that (R + R ⁇ vs 2 Z 2 power is always consumed)
• the power consumption of the entire circuit is never reduced even if the power consumption in the neuron 1301 is reduced by applying the MOSS.
• C A two-layer neural network consisting of n neurons in one layer.
• the strength of each synaptic connection can be changed as appropriate, and the changed value must be stored.
• the power of using a 4-bit binary counter for this purpose alone requires at least 30 M ⁇ S transistors.
• many elements are required to construct a DZA converter.
• these circuits consume more power per synaptic connection, which is disadvantageous in terms of power consumption.
• the present invention has been made to solve such a problem, and the power consumption is extremely small, and a synapse coupling can be realized with a small number of elements. It is intended to provide a semiconductor device capable of realizing a computer chip. Disclosure of the invention
• the semiconductor device of the present invention has a first semiconductor region of one conductivity type on a substrate, and a first source and a first drain region of an opposite conductivity type provided in this region.
• a first gate electrode in a potential floating state provided in a region separating the first source and the first drain region via a first insulating film; the first gate electrode
• a first MOS transistor having a plurality of second gate electrodes capacitively coupled via a second insulating film and a source electrode connected to one of the second gate electrodes. And that at least one of the gate electrode and the drain electrode of the MOS transistor is connected to a first wiring for transmitting a signal of two potential levels of high (or low or high L).
• a synapse connection can be configured with a small number of elements, and power consumption is always low. Therefore, high integration and low power of a neural network can be achieved. Realizing the Nuronon Computer Chip It was done. BRIEF DESCRIPTION OF THE FIGURES
• FIG. 1A is a circuit diagram showing a first embodiment.
• Fig. 1 (b) is a circuit diagram showing only the synapse coupling circuit 104 of Fig. 1 (a).
• Fig. 1 (d) is a graph showing the relationship of i-V ⁇ P.
• FIG. 2A is a schematic plan view showing a second embodiment.
• Fig. 2 (b) is a cross-sectional view taken along line X-X 'in Fig.
• FIG. 2 (c) is a diagram showing the semiconductor device of the present invention including synapses and neurons using symbols.
• Figure 2 (d) is a circuit diagram showing the main part of the synaptic connection (NMOS part with a floating gate).
• Fig. 2 (e) is a circuit in which the main parts of the synaptic connection in Fig. 2 (d) are arranged in a matrix.
• He Fig. 2 (f is a cross-sectional view of a nonvolatile memory element using a ferroelectric thin film. Is a graph showing the characteristics of a depletion-type PMOS FET, and
• Figure 3 (b) is a graph showing an example of the time response characteristics of the circuit shown in Figure 1fb).
• FIG. 3 (c) is a graph showing an example of the time response characteristics of the circuit shown in Fig. 1 (b).
• FIG. 3 (d) shows a modification of the present invention! ;
• FIG. 3E is a circuit diagram showing a modification of the present invention.
• FIG. 3F is a circuit diagram showing a modification of the present invention.
• FIG. 3G is a circuit diagram showing a modification of the present invention.
• FIG. 3 (e) shows a structural diagram having a floating gate.
• FIG. 4A is a circuit diagram showing the third embodiment.
• Fig. 4 (b) is a conceptual diagram showing the synaptic connection of Fig. 4 (a).
• FIG. 5A is a plan view showing a layout example of a main part of a neural network including one synaptic connection and one neuron 502.
• Fig. 5 (b) shows the material of Fig. 5 (a).
• Fig. 5 (c) is a cross-sectional view taken along the line X-X 'in Fig. 5 (a).
• Fig. 5 (d) is a sectional view taken along the line Y-Y 'in Fig. 5 (a.).
• FIG. 6A is a circuit configuration diagram showing a fifth embodiment.
• FIG. 6 (b) is a simplified view of FIG. 6 (a).
• FIG. (7a) shows the sixth embodiment, and shows a four-layer neural network expressed using the notation method of FIG. 6 (b).
• FIG. 8 (b) is a diagram showing an I (n) part of FIG. 7 (a).
• FIG. 8 (a) is an E road diagram showing a seventh embodiment.
• Fig. 8 (b) is a diagram showing the relationship between Y in and V in aj.
• Fig. 9 is a model diagram showing the configuration of the basic unit of the neuron of ⁇ . Model drawing explaining the function of the neuron.
• Figure lo (b) is a graph showing the relationship between z and vout .
• FIG. 11 (a) is a cross-sectional structure diagram showing an example of a Les Moss.
• FIG. 11 (b) is a conceptual diagram for explaining the operation of the MOS of FIG. 11 (a).
• Fig. 11 (c) is an inverter circuit diagram using M ⁇ S in Fig. 11 (a).
• FIG. 11 (d) is a graph showing V 0UT 1 and V 0UT 2 in FIG. 11 (c) as a function of Z.
• FIG. 1 2 shows a prior example, and is a schematic cross-sectional view of a CM ⁇ S neuron gate.
• Fig. 1 2 shows a prior example, and is a schematic cross-sectional view of a CM ⁇ S neuron gate.
• FIG. 14 (b) is a circuit diagram showing an example in which one neuron circuit is configured according to the preceding example.
• Fig. 13 is a circuit diagram showing a prior example, showing a basic configuration example of a neuron circuit including a synaptic connection using transistors.
• Fig. 14 (a) shows a prior example, and is a circuit diagram showing an example of a method of realizing a variable resistor.
• FIG. 14 (b) is a circuit diagram showing an example of a circuit for controlling the value of V r with respect to FIG. 4 (a).
• FIG. 1A is a circuit diagram without the first embodiment, in which 101 is a neuron circuit, and for example, the circuits shown in FIGS. 11 and 12 may be used. If lower power consumption is required, it is preferable to use the circuit shown in FIG. 102 a to 102 d are input terminals of the neuron circuit. For example, the circuit of FIG. 12 corresponds to 1206 a to 1206 d.
• Reference numeral 103 denotes a wiring for outputting the output signal of the neuron. For example, the wiring is connected to the output terminal 1 2 1 4 of the neuron circuit as shown in FIG. DD or
• Reference numeral 104 denotes a circuit that functions as a synapse that connects the output 103 of one neuron and the input 102a of one two euron 101.
• Reference numeral 105 denotes an NMOS transistor, and reference numerals 106a and 106b denote a source and a drain of XMOS, respectively.
• 107, 108a and 108b are PMOS transistors and their O-sources and drains, respectively: N " ⁇ 10 S, P ⁇ P S source electrode 106 a.
• 108 a is both connected to one of the neuron's input terminals 1 0 2 a—
• the drain 106b of the NMOS and the drain 108b of the PMOS are connected to V DD and the ground, respectively.
• the capacitor C of 1 1 represents the capacitance associated with the input terminal 102a, including the stray capacitance, and is not particularly provided as a circuit element.
• Fig. 1 (e) shows the change in ' Qut when the vin is changed from 0 V to v DD in the circuit of Fig. 1 (b).
• V in 0V
• V rat 0V
• V gs p 0V
• Y. c n 0
• the NMOS transistor 105 is turned off.
• V in is sequentially increased, and when V in > V TH n , the NMOS transistor 105 becomes O ', i- flows, and the capacitance C There is charged 1 T. ui rises.
• the value of the weight w can be determined by the value of the threshold value V T réelle n of the NMOS transistor 105.
• a neural network with a fixed synapse connection strength can be realized.
• impurities of the channel portion in a manufacturing process B, P or A s etc.
• the ion beam may be focused and irradiated onto the channel portion of the transistor, and a preset dose may be sequentially implanted.
• the neural network with fixed synaptic connection strength realized in this way has no learning function, but it has been found that it can compute very quickly for specific problems such as the forward salesman problem.
• the drain 106 b of the NMOS transistor 105 is connected to V DD , but this may be connected to the signal line 103.
• the signal line 103 needs to supply a current for charging the capacitor C, the output of the neuron circuit at the preceding stage needs to have a sufficiently large current supply capability.
• the synaptic connection strength is variable, and a neural network having a learning function of t can be constructed.
• FIG. 2 (a) schematically shows a plan view
• FIG. 2 (b) is a cross-sectional view taken along line X-X '
• Reference numerals 201 and 202 denote NMOS and PM transistors
• reference numeral 203 denotes a floating gate on the NMOS channel region via a gate oxide film 204 having a thickness of, for example, 20 OA.
• it is formed of an N + type polycrystalline silicon thin film.
• the floating gate 2 0 3 is opposed to the N + region 2 0 6 via the S i 0 2 film 2 0 5 to about 5 0 to 7 0 A, for example.
• Chi tau region of this 2 0 6 is a charge injection electrode.
• Reference numeral 211 denotes an electrode formed of, for example, WS i 2 (tungsten silicide), which is capacitively coupled to the floating gate 203 through, for example, a 200 A Si 2 film 212 .
• 2 1 3 a, 2 1 4 a are each! S T MO S and PMO S Tran Soo evening situ source are both connected to one input terminal of the next neuron.
• 2 13 b and 2 14 b are the drains of the NMOS transistor and the PMOS transistor, respectively, and are connected to the power supply line (v DD ) and the ground line (V S J respectively).
• connection wiring to V DD , V s originally and the next two euron input is omitted, and in Fig. 2 (b), 2 1 ⁇ ⁇
• the field oxide film, 216 is, for example, a ⁇ -shaped silicon substrate.
• 112 (c) shows the semiconductor device of the present invention composed of synapses and neurons by using symbols, and each part corresponds to the same numbered part in FIGS. (A) and (b).
• 2 1 7 shows one neuron circuit
• 218a to 218d are input terminals of the neuron circuit, which correspond to 101 and 102a to 102d in FIG. 1 showing the first embodiment, respectively.
• this embodiment realizes a synaptic connection by connecting NM 0 S and PM 0 S in series similarly to the first embodiment. ing.
• the difference is that the NMOS has a floating gate 203.
• the Is'AiOS transistor 201 becomes an enhancement type transistor that turns on when a voltage of V TH n or more is applied to the gate electrode 207.
• the gate electrode 207 Works exactly the same as described.
• S'MOS gate electrode (abbreviated as G)
• 211 is a synapse intensity change ⁇ ⁇ abbreviated as control electrode
• 206 is a charge injection electrode (abbreviated as C)
• 203 is a floating gate (abbreviated as FG) It is.
• Z is expressed as (C G V G + C w V + CV + Q F) / (C ox one Cr + C 3 ⁇ 4 ⁇ C G) ... (8).
• Q F is the total amount of charge in the floating gate, V. V e waso respectively G, W, the potential of the C, C ⁇ , C r, C i, Cr FIG 2 (c) This is the capacitive coupling coefficient between each electrode and FG defined in.
• the potential of the P-type silicon substrate was set to 0V. .
• NMOS turns ON when.
• the threshold voltage V TH n of NMOS viewed from the gate electrode 207 is
• V TH n (C T0T / C G ) V TH *-(Q F / C G )... (10)
• V TH n is determined solely by the value of Q F.
• V pp be a program voltage greater than V DD .
• V DD 5V
• Vpp 10 ⁇ '.
• Q F 0.
• the thickness of the oxide film 205 is, for example, 5 OA
• an electric field of 1 ⁇ / cm is applied to the oxide film, and a Fowler-Nord-Dimm tunnel current flows, and C flows into FG. Electrons are injected and Q F ⁇ 0.
• the tunnel electric ⁇ is ⁇ little stops in a state in which a certain amount of electrons are injected in course to precisely control the amount of charge injected
• the pulse width or the pulse height, or the pulse width and the pulse height are constant, and the pulse width may be changed.
• Electron injection can also be performed by changing ⁇ in a pulsed manner. For example, most first time, leave the V ,,,, V v a r Te to Baie v pp, v c only may be doing a pulsed manner dropped to 0 V. Similarly, electrons are injected and the amount can be controlled.
• QF is negative
• V TH n is larger than the expressions (10) and (11). That is, from Eq. (7), this is a change operation that reduces the synaptic connection strength w.
• connection strength w As shown in Fig. 2 (d), the main parts of synaptic connections (NMOS parts with floating gates) were arranged in a matrix of four (2 12, 2, 13, 2, 14 and 21).
• Gj, G 9 corresponds to the signal line 2 1 0, 2 are arranged in parallel.
• W and ⁇ ' 0 correspond to the signal lines 2 1 and 2 are also arranged in parallel.
• V pp and G For example, if you want to change (weaken) only the synaptic connections of 2 1 and 2, only V ⁇ gives a potential of V pp and G. And may be set to 0 V. Of course, it is set to 0 (V). See Fig. 2 (d).
• V c Y pp
• G r G 2 and WW 2 are all raised to V pp . Then, even if G 9. W. If only Y is set to 0 Y, only the synapses 2 15 located at the intersection can increase the connection strength.
• each NMOS transistor has the PM0S shown in FIGS. 2 (a) to 2c). Needless to say, and associated wiring is attached.
• one synaptic connection can be composed of one XMOS transistor and one PMOS transistor as shown in Fig. 2 (a), the area occupied on the chip Is very small, and can accumulate synaptic connections at high density.
• the synaptic connection can determine its coupling strength by the electric charge stored in the floating gate, it is possible to freely change the coupling strength and memorize the force and its value. It achieves almost the same functions with two simple functions. It also has the function of selectively adjusting only certain synapses to an arbitrary strength for synaptic connections arranged in a matrix.
• a dc current upon keeping the output potential of the synaptic constant value, it is not necessary to flow a dc current at all, such as the power consumption can be made very small, ultra high density 3 ⁇ 4: It has the correct and ideal characteristics for the neural network configuration.
• the conventional synaptic connection (Figs. 13 and 14) not only consumes a large amount of power, but also requires a large number of elements to memorize the connection strength.
• the present invention makes it possible for the first time to realize a highly integrated neural network.
• N + -type polysilicon is used as the material for the electrodes 203 and 207, and WSi is used as the material for the electrode 211.
• A1 was used as the material of 210 was described, but this is only an example, and other materials that can achieve the same function are used. Of course, it is possible. Needless to say, the materials and film thicknesses of the insulating films 204.205, 208, and 212 are not limited to the materials and film thicknesses described here.
• the case where the charge injection electrode 206 is provided as an independent electrode has been described. This is, for example, the extension of the source electrode 21 a or the drain electrode 21 b of the XOS transistor 201. May be provided in the existing portion. This eliminates the need for wiring for applying a potential to the electrode 206, which is advantageous for high integration.
• the ⁇ ' + layer it may be formed by a polysilicon electrode, for example.
• the selective coupling strength is changed by a combination of voltages applied to the two electrodes 2 11 () and 2 07 (G).
• 2 11 (W) is an electrode provided exclusively for strength improvement, while 2 07 (G) also serves as an NMOS gate electrode. This is because, for example, in Fig. 2 (d), another electrode dedicated to intensity change similar to W is added, and the amount of charge injected into FG is controlled by the combination of voltages applied to these two electrodes. Good.
• a floating gate type MOS transistor is used in order to make the threshold value of the NM OS transistor variable.
• an MX OS type device may be used.
• 2 16 is a P-type Si substrate
• 2 17 is, for example, a 5 OA Si 0 2 film
• 218 is a ferroelectric thin film, for example, a PZT CP b (Z r ⁇ T i 1- ⁇ ) 0 9 ) is used.
• 219 is an electrode of ⁇ i, for example.
• 220a and 220b are 1 ⁇ type sources and drains.
• any means may be used to make the threshold value of the NMOS transistor variable.
• the charge amount of the floating gate one in Bok is as was previously mentioned base is able to control the threshold v T "n Power ':, apparent from (1 1) as, lambda, even cowpea to may given a predetermined potential to V r ⁇ ⁇ " ⁇ can be made variable.
• the synaptic connection may be performed by controlling the potential of vw or V in this way.
• the PMOS transistor (107, 202) is replaced by the NMOS (105, 201).
• Y ss ground
• This use is a Depureshiyon type PMOS FET having the characteristics shown in FIG. 3, for example (a) (, Re O if,.
• V g «P -.
• Fig. 3 (b) shows the time response characteristics of the circuit of Fig. 1 (b). Since the rise time is determined by the characteristics of the XMOS transistor I05, the force remains unchanged; The response is faster when a depletion-type PMOS transistor is used. To further shorten the falling down time may Shiteyare increase the value of V TTI P.
• the transistors (107, 202) may be used Enhansu Men Bok type PMOS FET is Y TH P rather 0.
• the time response characteristics of the circuit in Fig. 1 (b) are as shown in Fig. 3 (c).
• the rise characteristics are the same as those in Fig. (B).
• the force fall characteristics are completely different. That is, '. ut is the output voltage constant value equal Natsuta time to I v T 1. Because at this point, the ⁇ S transistor turns off.
• this voltage level decreases with time and becomes 0 V after sufficient time has passed. This is because the charge stored in the capacitor C escapes due to the leakage of the PN junction or the sub-threshold current of the P-channel transistor.
• Such synaptic connections can memorize the state of excitement for a while.
• the power of the new “-” becomes ⁇ level
• I n TP p ! A voltage equal to is held.
• the resistor R should be connected in parallel with the P-MOS transistor (107, 202.) c In this case, the output voltage will be asymptotic to ⁇ with the RC time constant. Also, lasting output To adjust the voltage level, change the value of v TH p .
• V Tfl P of the PMOS transistors (107, 202) by changing the value of V Tfl P of the PMOS transistors (107, 202), synapse connections with various characteristics can be realized.
• v T / may be set to an appropriate value during the manufacturing process by, for example, channel ion injection for threshold adjustment.
• a structure having a floating gate may be used to increase or decrease the amount of charge in the floating gate to make V TH A variable.
• a structure having a floating gate Ichito like shown in FIG. 3 (d, by the value of the potential or c c a v e v T "values may be changed by p.
• V TH P (C TQT / C G ) V TH * ⁇ (QFZC'G) ⁇ (W V C... ( 14 )
• V ⁇ 1 can be changed as needed by changing the value of ⁇ .For example, it is possible to keep the excitation state only for a specific Nabilus connection for a certain period of time.
• Fig. 3 shows these examples only for the partial circuit corresponding to Fig. 1 (b).
• a PMOS transistor instead of a PMOS transistor, a resistor 303, a depletion-type PMOS 304 with a gate connected to the source, and an enhancement type NAiOS 305 with a gate connected to the drain.
• the Enhanced-type PMO S with the gate connected to the drain, and the depletion-type iMO S, t Any device can be used as long as it works as a load resistor, such as a MOS transistor to which a gate voltage is applied.
• Fig. 4 (a) is indicated by symbols, but the meaning of each symbol is the same as in Figs. 2 (a) and (d).
• Reference numerals 401 and 402 denote NMOS and PMOS transistors, respectively, both having a common floating gate (FG) 403.
• 404 is a gate electrode which is capacitively coupled via an insulating film of Si 0 2, etc.
• FG floating gate
• Reference numeral 405 denotes a control electrode (W) for synapse intensity change similar to 211 in Fig. 2 (c), and reference numeral 406 denotes an electrode (C) for two persons (C) similar to J6.
• 407 is a signal line for transmitting the output signals of all the neurons, and 408 is a wiring connecting the output voltage of the synapse to one input terminal of the next stage neuron 409. is there.
• the threshold ⁇ ' ⁇ v TH J from the gate electrode G common to NMOS PXiOS is given by the following equation.
• ⁇ TH (C ⁇ QJ / CQ) ipu one (Q / CQ)... (1 /)
• C G , ⁇ ⁇ ⁇ , etc. are all determined by the manufacturing process, and are parameters that do not change when the device is completed. That is, the value of ⁇ ⁇ ⁇ - ⁇ ⁇ ⁇ is always constant, and does not change even if the strength of the synaptic connection is changed. This fact has the following significant implications.
• the PMOS transistor in order to speed up the falling characteristic of the synapse output, the PMOS transistor must be a destruction type (V TH P > 0) and increasing the value of ⁇ ⁇ / as much as possible was effective.
• the condition of equation (12) that is, TF
• the third embodiment is the same as the second embodiment except that the NMOS and the PMOS share a floating gate. Therefore, it goes without saying that the same can be applied to the change of the synaptic connection strength.
• FIG. 5 (a) depicts the layout of the main part of a neural network consisting of one synaptic connection and one neuron 502.
• FIG. 5 (a) depicts the layout of the main part of a neural network consisting of one synaptic connection and one neuron 502.
• This circuit is realized by a CMOS process using two-layer polysilicon and two-layer aluminum wiring technology.
• the pattern of each part is L, t is made of such a material, and an example is shown in Fig. (B).
• the A1 wiring running in the X direction is the wiring on the first layer, and the wiring running in the Y direction is the wiring on the second layer. Also ⁇ ' DD .
• a 1 line for clarity of layout ⁇ is, they do it by supplying a potential of the first layer A 1 line running in the X direction if e Yi j
• FIGS. 5 (c) and 5 (d) are cross-sectional views taken along line X-X 'and Y-Y' of FIG. 5 (a).
• 504 are NMOS and PMOS transistors, respectively, and 505 is a floating gate (FG) common to both.
• 505, 506, and 507 are a common gate electrode (G) for N IOS and PMOS, a control electrode ( ⁇ ') for changing synaptic connection, and a charge injection electrode (C), respectively.
• the circuit has a similar function and is represented as a specific pattern.
• the charge injection electrode 508 is provided via a thermal oxide film 509 of about 7 OA (see FIG. 5, c)) grown on the polysilicon electrode 505, for example. It is formed of a second layer of polysilicon. However, this may of course use the N + diffusion layer 206 as in the second embodiment.
• W (507) is connected to the second-layer A1 wiring 511 via a contact hole 510.
• G (506) is connected to signal line 512.
• the signal line 512 is connected to the output terminal of the neuron similarly to 103 in FIG. 1 (a) and 210 in FIG. 2 (a).
• ⁇ 13 is capacitively coupled to the floating gate (FG) 515 via the insulating film 514.
• Numeral 515 is a floating gate of the NMOS transistor 513 and the PMOS transistor ⁇ 17, and constitutes a CMOS neuron gate ⁇ 19. This is the device that is just invited to 1210 in Figs. 12 (a) and (b).
• the output is input to the CMOS inverter 521 by the A1 wiring 520, and the output power is output to the A1 wiring 522 of the first layer.
• this output is connected to the A1 wiring 524 of the second layer through the through hole 523, and further connected to the A1 wiring 525 parallel to 5I2.
• the wiring 524 also extends downward (524b), which is an output line to the neuron in the next layer (details will be described in the example of ⁇ ).
• the ⁇ 25 signal line forms a signal line that feeds the output of the neuron 502 to the input side of the same neuron, and through a synapse circuit similar to 501, for example, Connected.
• 526 is a ⁇ -type Si substrate
• 527 is an n-type hole
• 528 is a field oxide film.
• the most important function of the neural network is realized with a very small chip area including the feedback function.
• the synapse and one neuron have been described, it can easily be extended to a neural network consisting of many two eurons.
• FIG. 6A is a configuration diagram of a circuit showing a fifth embodiment of the present invention.
• Down ⁇ , down - ⁇ ⁇ , j n represents the n-number of neurons group of the first layer, each having a circuit similar to 502 in FIG. 5 a).
• ⁇ . N ⁇ 2 ⁇ , ⁇ ⁇ , and III 1, ⁇ III 2 , “" ⁇ j j n m ” represent n neurons in the second layer and m neurons in the third layer, respectively.
• Each neuron has the same structure as 502. 0 and ⁇ are output lines from the neurons in the first layer, and correspond to the signal lines 5 and 12 in Fig. 5 (a).
• ⁇ 1 II 2 '' * ' ⁇ I ⁇ ⁇ is the input line to the neuron population of the second layer corresponds to 5 1 5 of the floating gate of FIG. 5).
• C ⁇ 1 , OJJ 2 , OJJ 3 ..., ⁇ ⁇ ⁇ are the output lines of the neuron group of the second layer, and some of them are connected to the third layer through the wiring of 60 1 a, 60 1 b, etc. Is connected to the input line of the group of neurons.
• a part is connected to the wiring 603a, 603b, etc. parallel to the output line of the first layer neuron group by the wiring 602a, 602b, etc., forming a feedback loop.
• 60 1 602a and 603a correspond to 524b 524 525 wiring, respectively.
• 604a, 604b, etc. are synapse connection circuits, and correspond to, for example, 501 in FIG. 5 (a).
• FIG 6 (b;) there is shown a simplified drawing (a) c 6 0 5 of down j (n) represents the neuron population of the first layer n from n neurons It means becoming.
• n outputs (n forces of the first layer and ⁇ outputs of the second layer are fed back) and ⁇ inputs to the second layer
• the arrow at 608 indicates that n outputs are being fed back.
• FIG. 7 (a) is a four-layer neural network expressed using the notation of FIG. 6 (b), which is the sixth embodiment of the present invention.
• I (. N) is the input layer and consists of n amplifiers as shown in FIG. Input II 2 of the binary signals..., A circuit for outputting a I n as the level of each 0 V and V DJ).
• the four-layer neural network force with feedback is realized by a correct two-dimensional array.
• the human brain can easily construct a neural network containing any number of layers of neurons by repeating the same array of forces, which are said to be composed of six layers of neurons, in a planar manner. That is, the semiconductor device of the present invention has a feature very advantageous for realizing a neuron computer.
• FIG. 8 is a drawing showing a second embodiment of the present invention.
• FIG. 4A This is the same as FIG. 4A except that the drain of the XOS 401 is connected to 0 V, the drain of the PMOS 402 is connected to one nr , and G is connected to the signal line 801. 4 are assigned the same numbers as in FIG.
• FIG. 8 (b) shows the relationship of ut .
• 'TH n is the threshold viewed from gate electrode 404 of the NMOS transistor 40 1.
• V in V DD
• the wiring of 103, 210, 407, etc. is connected to the output terminal of the 21-port, and if the L It is not connected to the output of the input buffer as shown in Fig. 7 (a). It may be sharp.
• the output data of the neuron may be latched once to a flip-flop or the like, and the value may be supplied to these wirings through a pass transistor or the like. Needless to say, the power may be supplied via an appropriate amplifier.
• the semiconductor device of the present invention can realize a neural network having basic functions close to the human brain with a small number of elements and low power consumption. Furthermore, it is the most suitable semiconductor device for realizing a neuron combination because a complex neural network can be constructed with a regular array of planar elements.

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• 1991
  • 1991-01-12 JP JP03013780A patent/JP3122756B2/ja not_active Expired - Fee Related
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• 1992
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