WO1988005188A1 - Agencement de processeur avec processeur z 80 pour fonctions de terminal ainsi qu'agencement pour representation de caracteres de petite et grande dimension sur un ecran cathodique pilote par une commande de tube cathodique - Google Patents

Agencement de processeur avec processeur z 80 pour fonctions de terminal ainsi qu'agencement pour representation de caracteres de petite et grande dimension sur un ecran cathodique pilote par une commande de tube cathodique Download PDF

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Publication number
WO1988005188A1
WO1988005188A1 PCT/HU1987/000062 HU8700062W WO8805188A1 WO 1988005188 A1 WO1988005188 A1 WO 1988005188A1 HU 8700062 W HU8700062 W HU 8700062W WO 8805188 A1 WO8805188 A1 WO 8805188A1
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WO
WIPO (PCT)
Prior art keywords
output
input
processor
memory
cathode ray
Prior art date
Application number
PCT/HU1987/000062
Other languages
German (de)
English (en)
Inventor
Lajos PORTÖRO^"
Gábor SZABÓ
Imre Fazekas
József TÓTH
Károly GULYÁS
László KELEMEN
Bálint ALMÁSI
János ECSEKI
János CSÁRDÁS
Miklós MOLNÁR
József SZABÓ
Original Assignee
Vilati Automatika Vállalat
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Vilati Automatika Vállalat filed Critical Vilati Automatika Vállalat
Publication of WO1988005188A1 publication Critical patent/WO1988005188A1/fr

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/222—Control of the character-code memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/24—Generation of individual character patterns
    • G09G5/26—Generation of individual character patterns for modifying the character dimensions, e.g. double width, double height
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
    • G09G5/30—Control of display attribute
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Definitions

  • the invention relates to a processor arrangement with a Z 80 processor for terminal functions, which includes a processor, a dynamic memory associated with it with random access, a read-only program memory, a DMA controller for direct memory access, an inner and outer address bus for the connection - Structure of the connection between the units mentioned, an inner and outer data bus, coupling units for the establishment of a connection between the outer address and data bus, as well as the memory and the program memory, a bus drive unit connecting the inner data bus to the outer data bus, and has a cathode ray tube control, the data input of which is connected to the outer data bus via a buffer register, the cathode ray tube control having a data request output, a data acknowledgment input and an output connected to a display, while the processor contains a memory request output and a refresh output.
  • the invention further relates to a circuit arrangement that can be connected to this processor structure for mapping characters with large and small dimensions on a cathode ray tube controller controlled by means of a cathode ray tube controller, the character bus of the cathode ray tube controller with character selection elements of a character assigned to the characters with small dimensions.
  • a character generator is connected, while the output of the character generator is connected to parallel inputs of a step register, a serial data output of the step register is connected to an input of a video signal decoding and drive unit, the output of which is connected to the cathode ray tube monitor, a control signal bus of the cathode ray tube control assigned to the attribute symbol is also connected to the input of a pipe line register, the output of which is connected to further inputs of the unit mentioned, while its central clock generator is connected to a frequency divider, one output of which is connected to the clock input of the cathode ray tube control.
  • the solution according to the invention can be used as a uniprocessor cathode ray tube terminal which can be implemented with Z 80 processor elements and, due to its structure, is suitable not only for operating the cathode ray tube but also for carrying out other processor and terminal functions.
  • the function of a terminal with a general purpose requires a " significant processor capacity
  • the first thing to be mentioned here is the refreshing of the image in time with the frame rate, ie the generation of the characters to appear on the screen.
  • the running time of this time-optimized subrute is approximately 211. us, which is almost a third of the total time of 640 Aus ⁇ .
  • the processor cannot provide any other functions, so that almost a third of its useful time cannot be used.
  • This image refreshing solution can only be used to a limited extent in the systems which contain the extremely widespread Z 80 processors, since the detection of the POP commands relating to the screen area is more complicated than in the systems of type I 8085.
  • the cathode ray tube control I 8275 mentioned enables the use of the so-called attribute characters.
  • the attributes carry the information which relates to the display (illustration) of the character or character field following them.
  • the number of characters to be transferred to the cathode ray tube control changes. This fact leads to an irregularity in the data transmission which has to be carried out between the processor and the cathode ray tube control and which is repeated in cycles of 20 ms. Correct image reconstruction requires processor time, which reduces its usable free capacity.
  • the information to be mapped is small, preferably large letters, for example writable in matrix consisting of 16 x 16 raster points, with extended attribute performance are used.
  • Such requirements are characteristic of the terminals used in the rail reservation systems.
  • the increase in the free capacity of a processor is generally sought because, in addition to operating the screen, a number of other functions are to be provided by a terminal.
  • the object to be achieved with the invention is to obtain a single processor arrangement in which the refreshing of the image content and, if appropriate, the fulfillment of special character representation claims require a much lower processor capacity, and the freed capacity can be used for the purposes mentioned.
  • the processor regularly addresses the dynamic memory located in the processor system with random access during its normal function in the refresh cycle of the commands and thus ensures that the content of the memory is retained.
  • This process is called memory refresh.
  • the invention is based on the fundamental knowledge that the refresh cycle time of the memory is comparable to the refresh time of the image content and that the screen can be refreshed during the refresh cycle of the memory with a corresponding hardware arrangement.
  • the serial executes during this refresh
  • the character information is read from the memory at the same time by the dynamic memory refresh.
  • the memory refresh is continued in the conventional manner during the time period of the image rewind, if no character forwarding takes place.
  • the memory refreshing takes place with certainty within the time period required for this.
  • a processor arrangement with a processor of the type Z 80 for terminal functions was created, which has a dynamic memory associated with the processor with random access, a read-only program memory, a direct memory access-securing DMA controller, an inner and an outer Address bus for establishing the connections between the mentioned units, an inner and outer data bus, coupling units for establishing connections between the outer address bus and data bus, as well as the memory and the program memory, a bus drive unit connecting the inner data bus to the outer data bus and has a cathode ray tube controller, the data input of which is connected to the outer data bus via a buffer register, and which furthermore has a data request output and data acknowledgment input and an output connected to a display, the processor has a memory Inquiry output and a Auffrischungsausga ⁇ g and according to the invention, the arrangement includes an address multiplexer, the output of which is connected to the outer data bus and an input group is connected to the inner address bus, while another input group of the address multiplexer in the basic state at
  • Memory request output of the processor is connected to clock inputs of the memory via a unit which delays the clock control, the refresh output of the processor is connected to a clock input of a D flip-flop and via a delay unit to its erase input, a static input of the flip-flop is connected to the data request output of the cathode ray tube controller, an output of the flip-flop is connected to the selection input of the address multiplexer and a read-in input of the buffer register, while an inverted output of the flip-flop is connected to the static input of a with the clock signal of the arrangement controlled second flip-flops is connected, the output of which is connected on the one hand to the counting input of the display address counter, on the other hand to the data acknowledgment input of the cathode ray tube control and with the clear input of the display address counter the line of the image system Nchron signal of the controlled display is connected.
  • Another basic idea of the invention is based on the knowledge that when displaying "large letters" on the screen, only a quarter of the number of characters which can be applied when "small letters” are displayed has space. Since the number of cells in the field of memory containing the characters corresponds to the number of characters belonging to the mapping of the "small letters", for example 2000, there is the possibility of mapping "large letters” only to display the characters to be stored in every second cell and the cells in between can be used freely for attribute characters. In such an organization, the treatment of the characters to be mapped is independent of the number of attractions. constant, so it is not necessary to provide the appropriate positioning of the visible characters with processor support.
  • the character generator used for mapping "small letters” can also ensure that "large letters” are mapped.
  • the arrangement according to the invention saves a significant processor time in comparison to the known means with a similar structure and also enables “the generation of special screen formats.
  • FIG. 1 is a block diagram of the arrangement according to the invention, FIG. 1 shows a diagram of the unit 18 delaying the clock control, FIG.
  • FIG. A block diagram of the arrangement belonging to the illustration with "large letters”.
  • FIG. 1 shows a general block diagram of the system-technical arrangement according to the invention, which is essentially based on Z 80 processor elements.
  • the inputs and outputs required to understand the function are identified in the individual blocks.
  • the characters used are identical to those used in the catalogs of the manufacturers and consist predominantly of the short description of the English name of the corresponding function. For the sake of simplicity, these names have been summarized in the table below:
  • the Z 80 processor arrangement includes a processor 1, a dynamic memory 2 with random access, a program memory 3 containing a fixed program, a cathode ray tube controller 4, a DMA control unit 5 performing the control of the direct memory access, a serial transmission control unit 6, a counter timer circuit 7, a keyboard interface 8, a printer interface 9, a port decoding unit 10, a memory address interface 11, a memory output drive unit 12, a program memory address interface 13, a program memory output drive unit 14 Clock generator 15, a frequency divider 16 and a bus drive unit 17, these units are also contained in the known terminal control unit.
  • the connection is established between the units of the arrangement by means of an inner data bus 101, an inner address bus 100, an outer address bus 102 and an outer data bus 103.
  • the known units mentioned are for better differentiation from the new units in the drawing using a
  • the first of these units is a unit 18 which delays the clock control, the internal structure of which was illustrated in FIG. 2. Its one input is connected to the memory request output MRQ of the processor 1, while its corresponding output is connected to the one input of the memory address interface 11, furthermore an output of the unit 18 with the clock inputs CAS and RAS of the memory 2 is in Ver ⁇ binding.
  • Such a new unit is further formed by an address multiplexer 21, one of which has an input group with the inner address bus 100 and the other input group with the output of a display address counter 22 is connected. The output of the address multiplexer 21 is connected to the outer address bus 102.
  • the charging input of the display address counter 22 is connected to a display input address register 23 controlled by the outer data bus 103.
  • a selection input SEL of the address multiplexer 21 is controlled via a line 203 from the output Q of the D flip-flop 20, this line 203 also being connected to the load input Ld of the buffer register 24.
  • the control of the display address counter 22 in the basic state is secured via a line 200 from the one flank of the image synchronizing signal of the controlled display, while the negated output of the D-
  • flip-flops 19 via a line 204, the line 204 also controlling the data acknowledgment input DACK of the cathode ray tube controller 4.
  • the control of the flip-flops 19 and 20 is carried out by a logic circuit consisting of inverter 26, 27 NAND gate 28 and capacitor 29 on the basis of the signal of the refreshing output RFRSH of the processor 1.
  • An input D of the flip-flop 20 is connected via a line 201 to the data request output DRQ of the cathode ray tube controller 4.
  • the static input D of the flip-flop 19 is controlled by the negated output of the flip-flop 20, while its clock input Cp is connected to the one output of the frequency divider 16.
  • Line 202 is connected via an inverter to an admission input E ⁇ of bus drive unit 17.
  • the outer data bus 103 is via the Pu erregister 24 with the data input DATA IN of the cathode ray tube controller 4 and further through the interface 25 with the Background storage devices of the arrangement can be connected.
  • the keyboard interface 8 enables the connection to the keyboard, while the printer interface 9 secures the connection to the printer.
  • FIG. 2 shows the construction of the unit 18 which delays the clock control, which consists of an amplifier 40 connected to the memory request output MRQ and inverters 41, 42, 43 and 44 connected in series, and a capacitor 45.
  • the individual elements ensure a slight delay and separation, and also ensure that the memory address interface 11 is controlled in a timely manner.
  • FIG. 3 illustrates the arrangement of the units formed between the cathode ray tube monitor 34 and the cathode ray tube controller 4, the basic task of which is to display the corresponding rows of drawings on the screen. Similar to FIG. 1, the known units are surrounded by a double line.
  • This illustrated part of the arrangement according to the invention contains a character generator 30, the inputs A3 A9 of which receive the codes determining the characters from the outputs CC0 ... CC6 of the cathode ray tube controller 4 via a character bus 110, while the inputs A0 , AI, A2 of the character generator 30 enable the selection of the rows matching the characters.
  • Outputs LC0 .... LC3 of the cathode ray tube control 4 deliver control signals of the character series.
  • the output of the character generator 30 is connected to parallel inputs of a step register 31, whose serial output is connected to a serial input of a video signal decoding and drive unit 33.
  • the operating mode of the display is predetermined by the state of a pipe line register 32, which is connected via a control signal bus 111 to the cathode ray tube control 4 and directly to the unit 33.
  • the unit 33 directly controls the CRT monitor 34.
  • the known elements of the arrangement further include a clock generator 39 and a frequency divider 38 controlled by it, which also carries out pulse shaping.
  • two multiplexers 36 and 37 are used, inputs AI .... A4 and B1, B2, B3 of the
  • Multiplexers 36 are correspondingly connected to the inputs LC0 .... LC3 of the drawing, while outputs Y1 .... Y3 of the multiplexer 36 at the inputs A0 .... A2 of the drawing generator 30 and the output Y4 on a video Sperreinga ⁇ g VT the unit 33 are connected.
  • An output Y1 of the multiplexer 37 is connected via a line 302 to the clock input Cp controlling the shifting (shifting) of the step register 31, while an output Y2 of the multiplexer 37 is connected via a line 303 to a control output of the pipe line register 32 ⁇ is bound.
  • An output AI of the multiplexer 37 is connected directly to the output of the clock generator 39, the frequency of which is, for example, 12.5 MHz.
  • Another output A2 of the multiplexer 37 is connected to the output: 8 of the frequency divider 38 which has an eightfold divider ratio. This output leads via a line 304 to a clock input CL of the cathode ray tube control 4.
  • the frequency divider 38 also has outputs: 2 and: 16 for generating a half and a sixteenth division, which is associated with the respective inputs B1 and B2 of multiplexer 37 are connected.
  • the outer data bus 103 is connected to a memory register 35, the output of which is connected to the selection input SEL of the two multiplexers 36, 37.
  • the processor arrangement designed according to the invention functions as follows:
  • the refreshing of the information content of the screen is explained with reference to FIG. 1.
  • the refresh is carried out by the cathode ray tube controller at the data request output DRQ
  • the DMA control unit 5 is switched (this connection is not established in the arrangement according to the invention).
  • the DMA control unit 5 is initiated (triggered) on byte transmission.
  • the memory 2 which has a dynamic structure, also requires its own refreshment in order to be able to maintain the stored information.
  • the usual need for refreshing the dynamic memories with random access is 128 refresh cycles per 2 ms, ie an average of 15.625 microseconds each per cycle.
  • the system based on the Z 80 processor solves this refresh in such a way that when each operational code is read in, it generates a refresh signal which appears at its refresh output REFRSH, and at the same time controls the memory request output MRQ and the lower seven Bits of its address bus generate a refresh address, which advances by one in each refresh and repeats 128 refresh cycles. In this way, a so-called “incomplete” reading from the memory 2 takes place each time the memory is refreshed, which is sufficient to preserve the stored information.
  • a 2.5 MHz processor of the type Z 80 generates the refresh cycles with a frequency of 7.6 microseconds even in the case of an unfavorable program run that is conceivable with regard to the refresh.
  • the memory 2 is therefore refreshed at least twice in the worst case.
  • the image containing the usual 2000 characters 25 rows, 80 characters per row
  • the image containing the usual 2000 characters has a duration of 20 ms. If the return time is subtracted from the total image time, it follows that the cathode ray tube controller 4 on average 8 microseconds each request one character.
  • the essence of the function of the arrangement according to the invention is that the fulfillment of the information requirement of the screen is associated with the refreshing of the dynamic memory 2, and even - as can be seen below - the reading of the drawing information at the same time also Refreshing the memory 2 triggers.
  • the possibility for this is provided by the fact that the cycles controlling the memory refresh take place on average in time intervals of 7.64. Us, the screen takes up an average after a time interval of 8. Us is a new character and for refreshing the dynamic memory it is sufficient to start the memory access (read) less often by a factor of two.
  • the successive characters are also located at successive addresses, so the order in which the characters are read out also corresponds to the refresh.
  • the memory refresh must be carried out in the conventional manner described.
  • the data required to refresh the information content of the screen are read out of the memory 2 during the refresh cycle of the Z 80 processor and forwarded to the cathode ray tube controller 4, and thus the memory 2 is also refreshed.
  • the information required for refreshing the image content is stored in the successive addresses of the memory 2. Since the memory 2 can be used for a number of other purposes in addition to the storage of the characters forming the image content its information storage capacity is significantly higher than that required for image refreshment. The reading out of the characters is repeated cyclically for each image. It is thus understandable that the start address relating to the storage location of the image refresh information has to be determined at the beginning of each image.
  • This task is performed by the address address register 23, into which the port decoding unit 10 uses the control of the processor 1 to write the above-mentioned start address via the external data bus 103, ie more precisely the first eight bits of its most significant value. Sixteen bits are required to address memory 2. At the beginning of each picture, the arrangement receives a synchronous signal from the controlled display via line 200, which is in the six-bit range
  • Display address counter 22 writes this start address from the display start address register 23 (the value of the lower eight bits is assumed to be zero in this case).
  • the address multiplexer 21 connects the outer address bus 102, depending on the value of the signal at its selector input SEL, to the inner address bus 100 or to the output of the display address counter 22. In the basic state, the inner address bus 100 is connected to the outer one Address bus 102 connected.
  • the processor 1 cyclically carries out memory refresh operations as described above, while in the process it controls its refresh output RFRSH and its memory query output MRQ into the active state.
  • the signal appearing on line 202 separates the outer data bus 103 from the inner data bus 101 by blocking the permissible input E ⁇ of the bus drive unit 17 and controls it via the inverter 26 the flip-flop 20.
  • the state of the latter changes only when the cathode ray tube controller 4 requires the input of a character and this fact is reported by the active state of the data request output DRQ, which controls the static input of the flip-flop 20. Since the fulfillment of the data request is now being checked, it is now to be assumed that the state of the data request output was active and the flip-flop 20 tipped over into the other state. Thereupon the output Q which becomes active activates the line 203
  • Selection input SEL of the address multiplexer 21 and the output of the display address counter 22 are connected to the outer address bus 102.
  • the address of the memory 2 is now determined by the memory start address stored in the display address counter 22 and set according to the above, at which the value of the current character to be refreshed is contained.
  • the active state of the memory request output MRQ of the processor 1 controls the Taktsteu ⁇ rung verzögern ⁇ de unit 18 (Fig. 2) and other outputs appear in sequence the control signals of a corresponding polarity, Takteingä 'length RAS and CAS, including the permission signal of the memory address interface 11 , which enables the value connected to the outer address bus 102 to address the memory 2.
  • the code of the character appears on the outer data bus 103 and arrives at the input of the buffer register 24.
  • the addressing of the memory 2 thus also provides for its refreshing.
  • the rear flank of the signal of the refresh output RFRSH tilts the flip-flop 20 into the basic state after a delay and signal formation consisting of inverter 27, capacitor 29 and NAND gate 28, whereupon writes the character value fetched over the line 203 onto the outer data bus 103 into the buffer register 24, then the address multiplexer 21 resets to the basic state.
  • the flip-flop 19 tilts to the subsequent clock signal and, under the control of line 204, shifts (shifts) the display address counter 22 by one, which corresponds to the address of the following character, and at the same time controls the data acknowledgment input DACK of the cathode ray tube control 4.
  • the cathode ray tube control reads in the character values stored in the powder register 24 and the extraction of the characters is thus ended.
  • an image synchronizing signal arrives via line 200, which controls the display address counter 22 to the basic state, and a new refresh cycle, which relates to the entire screen area, begins from the start memory address.
  • the cathode ray tube controller 4 does not require the retrieval of a new character during the refresh cycle of the processor 1, it does not control its data request output DRQ (for example during the image rewind), and in this case the known conventional memory refresh comes into play.
  • DRQ data request output
  • the two different types of refreshment are changed, asynchronousities inevitably occur, but these do not cause any problems thanks to the at least two times of over-refreshing.
  • the screen is thus refreshed automatically during those cycles of the processor 1 during which the dynamic memory is to be refreshed in this way, the time required for the separate image refreshing, which each took 8 ms each of 20 ms, was completely saved.
  • FIG. 3 The known part of the arrangement illustrated here corresponds to the control unit of type 8275 from INTEL and its function is described on pages 43-90, section 7 of the manual mentioned. This function is referred to only to the extent necessary for understanding the arrangement according to the invention.
  • the character generator 30 is formed by a read-only memory with a capacity of 1 kbyte, with the aid of which a customary character set with 128 elements with an 8 x 8 matrix can be realized.
  • the cathode ray tube controller 4 stores a number of characters corresponding to a row and sends, for every eighth clock signal from the clock generator 39, a code which is characteristic of a subsequent character, via the character bus 110 and the character generator 30, which for each character has its parallel output with the given character series the combination of the character concerned issues, which inscribes into the step register 31 for every eight measures.
  • the step register 31 is shifted by the clock signals which have an undivided frequency, so the video signal decoding and drive unit 33 receives eight information bits per character and row at its serial data output.
  • the outputs LC0 .... LC3 of the cathode ray tube control 4 determine which of the 10 raster areas on the screen belongs to a given row of characters.
  • the gang LC3 of high quality controls the video blocking input VT of the unit 33, ie the last two rows are always dark, which corresponds to the space between the rows of characters.
  • the signals of the outputs LC0 .... LC2 are sufficient to distinguish the 8 rows within the characters.
  • the cathode ray tube controller 4 forwards corresponding control signals to the pipe line register 32 via a control signal bus 111, and this prescribes a state dependent on its values (for example lifting out, flashing, etc.) for the unit 33.
  • the mode of operation for mapping characters with dimensions of 8 ⁇ 8 is referred to below as the “lower case mode” and the arrangement illustrated in FIG. 3 functions in a similar manner.
  • mapping of characters with dimensions of 16 x 16 represents an optional possibility of the arrangement according to FIG. 3, which can be selected depending on the content of the memory register 35 via the data bus 103.
  • the function in this case is as follows:
  • the memory register 35 controls the selector inputs SEL of the multiplexers 36 and 37 into the .active state. outputs to the outputs. It can now be observed that output 30: 16 switches to line 303 instead of previous output: 8, while output 302 switches to line 302 instead of output; 1. This solution is essentially equivalent to that if the frequency of the clock generator 39 were halved with regard to the step register 31 and the pipe line register 32.
  • the codes of the entire characters corresponding to one row appear unchangeable per grid row.
  • the fastest changing output LC0 is not connected in the "capital letter mode”
  • the outputs LC1 .... LC3 are properly with the corresponding inputs B1 .. ..B3 connected.
  • the character generator 30 advances two rows of characters one row at a time, and the eight raster rows that belong to the mapping of one row of characters are read out for the duration of 16 raster rows. The result is an enlargement of the vertical dimensions of the image to be displayed twice.
  • the reading of the step register 31 also takes two times the duration, i.e. in the horizontal direction, the unit 33 receives new information in every second raster point by writing the step register 31.
  • these, for example, odd clocks and memory addresses can be used to pass on attribute characters.
  • the arrangement illustrated in FIG. 1 forwards the attribute characters to the cathode ray tube controller 4 in the same way as the characters to be imaged, which, however, recognizes them and, when attribute characters arrive on the character bus 110, gives them a neutral state for the character generator 30 and the code corresponding to the attribute character via the control signal bus 111 to the pipe Forward line register 32, which sets the unit 33 in a state corresponding to the attribute character. Since data is only forwarded from the step register 31 in every second cycle, the forwarding of the attribute characters remains invisible with respect to the screen and does not influence the actual position of the characters depicted.
  • the arrangement illustrated in FIG. 3 is therefore capable of mapping characters with a dimension of 16 x 16 and even assigning an attribute character to each character using a character generator with a capacity of 1 kbyte.
  • the use of the attribute characters does not interfere with the mapping of the characters even with any frequency.

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  • Controls And Circuits For Display Device (AREA)

Abstract

Dans un agencement de processeur comportant un processeur Z 80 (1) destiné à des fonctions de terminal, des informations relatives aux caractères sont envoyées à un tube cathodique du type I 8275 dans un cycle nécessaire à la régénération de l'image, à partir d'une mémoire à propagation (2) et en passant par un bus de données extérieur (103). Le processus de régénération de l'image s'effectue dans les cycles de régénération de la mémoire à l'aide d'un multiplexeur d'adresses (21), lequel relie le bus d'adresses extérieur (102) de la mémoire (2), au cours des cycles simultanés de régénération de la mémoire et de l'image, à la sortie d'un compteur d'adresses d'affichage (22) contenant l'adresse de début de la mémoire. Deux bascules (20, 19) assurent l'écriture des données de caractères extraites, l'avancement du compteur (22) précité et la commande du multiplexeur d'adresses (21). Le basculement desdites bascules est admis dans les cycles du processeur de régénération de l'image pendant la demande des données; lors de la régénération, l'adressage de la mémoire (20) par une unité (18) temporisant la commande de cycle commandée par le processeur (1) est admis. L'invention concerne également la représentation des caractères en ''capitales'' à partir des signaux fournis par la commande de tube cathodique (4). A cet effet est branché un multiplexeur (36, 37) respectivement entre la commande de tube cathodique (4) et un générateur de caractères (30), également entre un générateur d'impulsions (39) et un diviseur de fréquence (38) qui lui est relié, ainsi qu'un registre incrémentiel (31) commandé par le générateur de caractères (30). L'insertion et la synchronisation dudit multiplexeur permettent, sans modifications du logiciel, l'affichage en ''capitales'' et l'emploi de n'importe quels caractères d'attribut.
PCT/HU1987/000062 1986-12-30 1987-12-30 Agencement de processeur avec processeur z 80 pour fonctions de terminal ainsi qu'agencement pour representation de caracteres de petite et grande dimension sur un ecran cathodique pilote par une commande de tube cathodique WO1988005188A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
HU5528/86 1986-12-30
HU552886A HU196096B (en) 1986-12-30 1986-12-30 Processor arrangement for implementing terminal functions by a processor of z80 type as wellas arrangement for displaying small-dimension and large-dimension characters on the cathode ray monitor controlled by control-circuit of cathode ray

Publications (1)

Publication Number Publication Date
WO1988005188A1 true WO1988005188A1 (fr) 1988-07-14

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/HU1987/000062 WO1988005188A1 (fr) 1986-12-30 1987-12-30 Agencement de processeur avec processeur z 80 pour fonctions de terminal ainsi qu'agencement pour representation de caracteres de petite et grande dimension sur un ecran cathodique pilote par une commande de tube cathodique

Country Status (2)

Country Link
HU (1) HU196096B (fr)
WO (1) WO1988005188A1 (fr)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4357604A (en) * 1978-04-14 1982-11-02 Fujitsu Fanuc Limited Variable size character display
EP0123896A2 (fr) * 1983-04-04 1984-11-07 Tektronix, Inc. Circuit pour contrôler en mode caractères et en mode vidéo
DD231971A3 (de) * 1983-12-14 1986-01-15 Robotron Bueromasch Bildschirm-refreshsteuerung
EP0043889B1 (fr) * 1980-06-16 1986-01-29 International Business Machines Corporation Dispositif pour engendrer des caractères proportionnés à des hauteurs multiples
DD233003A1 (de) * 1984-12-27 1986-02-12 Robotron Bueromasch Bildschirmsteuerung mit crt- und dma-controller

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4357604A (en) * 1978-04-14 1982-11-02 Fujitsu Fanuc Limited Variable size character display
EP0043889B1 (fr) * 1980-06-16 1986-01-29 International Business Machines Corporation Dispositif pour engendrer des caractères proportionnés à des hauteurs multiples
EP0123896A2 (fr) * 1983-04-04 1984-11-07 Tektronix, Inc. Circuit pour contrôler en mode caractères et en mode vidéo
DD231971A3 (de) * 1983-12-14 1986-01-15 Robotron Bueromasch Bildschirm-refreshsteuerung
DD233003A1 (de) * 1984-12-27 1986-02-12 Robotron Bueromasch Bildschirmsteuerung mit crt- und dma-controller

Also Published As

Publication number Publication date
HU196096B (en) 1988-09-28

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