HU196096B - Processor arrangement for implementing terminal functions by a processor of z80 type as wellas arrangement for displaying small-dimension and large-dimension characters on the cathode ray monitor controlled by control-circuit of cathode ray - Google Patents

Abstract

In a processor arrangement comprising a Z 80 processor (1), intended for terminal functions, information relating to the characters is sent to a type I 8275 cathode ray tube in a cycle necessary for image regeneration, from a dynamic memory (2) and passing via an external data bus (103). The image regeneration process is effected in the memory regeneration cycles by means of an address multiplexer (21), which connects the external address bus (102) of the memory (2), during simultaneous memory and image regeneration cycles, to the output of a display address counter (22) containing the address of the start of the memory. Two flip-flops (20, 19) ensure the writing of the data of the characters extracted, the shifting of the above-mentioned counter (22) and the control of the address multiplexer (21). The tripping of said flip-flops is permitted during the image regeneration processor cycles during data request; during regeneration, addressing of the memory (2) by a unit (18) which delays the cycle control operated by the processor (1) is permitted. The invention also concerns the representation of ''capital-letter'' characters from signals supplied by the cathode ray tube monitor (4). For this purpose, a multiplexer (36, 37) is connected respectively between the cathode ray tube control (4) and a character generator (30), also between a pulse generator (39) and a frequency divider (38) connected thereto, as well as an incremential register (31) controlled by the character generator (30). The insertion and synchronization of said multiplexer enable the use of ''capital-letter'' displays, and any desired attribute characters.

Description

BACKGROUND OF THE INVENTION The present invention relates to a processor arrangement with a Z 80 processor for performing terminal functions comprising a processor, associated dynamic random access memory, read-only program memory, a direct memory access DMA controller, an internal and an external address bus for linking said units. memory linkers to program memory, a bus drive circuit connecting the internal data bus to the external data bus, a cathode ray tube controller whose data input is connected to an external data bus via a buffer register, a cathode ray tube controller having a data request output and a data reset input , and the processor has memory request output and update output.

The invention further relates to a circuit arrangement coupled to this processor structure for displaying small and large characters on a cathode ray tube controlled cathode ray tube monitor, wherein the cathode ray tube control bus is connected to a character generator the data output of which is connected to the input of a video signal decoding and drive circuit, the output of this circuit is connected to the cathode ray tube monitor, the control signal bus associated with the cathode ray tube controller attribute characters to a pipe line register input connected to a further input of said circuit, is connected to the clock input of the cathode ray tube controller.

The present invention is intended to provide processor and terminal functions other than a single processor cathode ray tube with Z 80 processor elements.

As a result of the proliferation of computing, there is a growing demand for cathode-ray tube terminals, especially those operating over high-speed data lines. The 9600 Baud or higher data transmission lines are increasingly demanded by microprocessor-based systems that control terminals, while the market requires inexpensive and simple terminal designs.

When examining which tasks require significant processor capacity in the operation of a general-purpose terminal, the first step is to generate the image refresh, i.e., the characters to be displayed on the screen at the frame rate. By way of example, the second volume of the 1985 edition of the INTEL Microsystem Component Hapdbook describes a simple and intelligent terminal layout using a Type I 8275 processor. In this solution, the screen is refreshed by a subroutine per string (corresponding to 10 raster lines), using forty POP instructions and some hardware support. The runtime of this time-optimized subroutine is approximately 211 ps, accounting for almost one third of the total 640 ps of the 10 raster series. The CPU cannot perform any other function during the image refresh, so it cannot use nearly one third of its useful time.

This image refresh solution is of limited use in systems that use the very widespread Z 80 processor, since the recognition of POP instructions for screen screen etiquette is more complex than in the I 8085 system.

For example, in a telephone factory power supply type 34 single-processor terminal, the data needed to update the image content is transmitted by a direct memory access controller from the memory of the central control processor. With this structure, the Z 80 solution delivers 160 ps of information corresponding to a line of 80 characters. In the meantime, the processor is waiting, it cannot execute other instructions, meaning that it can actually only process 640-160 = 840 ps under 340 ps.

Processor capacity is also required to meet many special display needs. The referred I type 3275 cathode ray tube controller allows the? so-called attribute characters. Attributes carry information related to the display of the following character or character field. Depending on the number of attribute characters placed in the image field, the number of characters to pass to the cathode ray tube controller will change. This fact makes the transmission of data between the processor and the cathode ray tube controller repeated over 20 ms cycles uneven. A correct image reconstruction processor takes time and therefore reduces its usable free capacity.

In some application areas where the information to be displayed is small, large-scale applications are preferred, e.g. 16x16 raster-point matrix letters with extensive attribute services. Typically, such requirements are encountered in terminals used in railway reservation systems. The 1 kbyte character generator used in the layout outlined in the referenced INTEL manual is not sufficient to produce the uppercase character matrix, but requires four times its capacity.

The processor is free. They usually seek to increase their capacity because a terminal can be expected to perform many other functions besides serving the screen. These include the provision of high-speed data lines, the ability to operate as a personal computer, including the provision of interfaces to connect to local peripherals. Until now, these demands could only be met with multiprocessor layouts, which obviously meant significantly higher hardware costs.

It is an object of the present invention to provide a single-processor arrangement in which updating the image content and, where appropriate, meeting specific character rendering requirements, consumes substantially less processor capacity and the released capacity can be used for the purposes referred to.

To understand the present invention, it is understood that dynamic random access memory in the processor system is routinely addressed by the processor during its instruction update cycle while performing its normal function, and thereby ensures that the contents of the memory are retained. This process is called memory upgrading. The invention is based on the basic recognition that the memory refresh cycle time is comparable to the refresh time of the image content and that the screen can be refreshed during the memory refresh cycle by proper hardware arrangement. During this refresh, reading the character information from memory sequentially perform. During the representation run, when there is no character transfer, the memory upgrade continues in the traditional way. When switching between the two types of memory upgrades, due to the appropriate cycle times, the memory upgrade will be safely performed within the time required for this.

A processor arrangement according to the invention has been provided with a Z 80 processor for performing terminal functions comprising dynamic random access memory assigned to the processor, read-only program memory, DMA controller providing direct memory access, internal and external address bus linking said units, an external data bus, interfaces connecting the external address and data bus to the memory with program memory, a bus drive circuit connecting the internal data bus to the external data bus, a cathode ray tube controller having data input and display output, the processor having memory request output and update output, and according to the invention, the arrangement comprises an address multiplexer, the output of which is connected to an external data bus, one of its input groups is connected to the internal address bus, the other b its initial group is connected to the output of the display address that contains the initial display memory address, is connected to the process inputs of the processor memory request output, the processor update output is connected to the D-type flip flop and its deletion input via the delay circuit, the flip flop is static connected, one output to the address multiplexer selection input and the buffer register scan input, the inverted output to the static input of the second flip flop controlled by the clock of the layout, its output being connected to the display address counter counting input and the cathode ray tube control display The line for the synchronization signal of the controlled display is connected to the delete counter input of the address counter.

Another basic idea of the present invention is to recognize that "in case of capitalization of characters, only a quarter of the characters on the screen can fit on the screen". Since the number of compartments in the character field in the memory, the number of characters in the "lowercase display" e.g. Corresponds to 2000, "In case of capitalization, it is only possible to store the characters to be displayed in every other compartment, and the intermediate compartments are freely used for attribute characters. With such an organization, the display characters are handled independently of the number of attribute characters, so there is no need for processor support to ensure that the displayed characters are properly positioned.

In "uppercase" display, two multiplexers and a clock generator with properly split signals make it possible for the "lowercase character generator" to also display "uppercase characters".

The arrangement of the present invention saves significant processor time compared to known devices of similar structure and also allows for the production of special screen formats.

Due to the advantageous properties outlined herein,? despite the simple structure, the arrangement according to the invention can be used to form an eight-bit general purpose configuration having a cathode ray tube terminal and the speed and intelligence of a microcomputer. All this advantage can also be considered that the use of the system as a general micro machine does not require the use of a separate cathode ray tube terminal.

Embodiments are illustrated by the drawing in which

Figure 1 is a block diagram of an arrangement according to the invention, a

FIG. 2 is a schematic of the circuit delay delay circuit 18, a

Fig. 3 is a block diagram of the "uppercase display e" layout.

Figure 1 is a general block diagram of the system arrangement of the present invention, which is mainly based on Z 80 processor elements. In the drawing, the inputs and outputs needed to understand the operation of each block are marked. The designations used in the manufacturer's catalogs are the same as those used in the manufacturer's catalogs and consist mainly of the abbreviation of the corresponding function in English. For simplicity, these notations are summarized in the following table:

lel lead and Hungarian name English name ADDR title addres CAS column column address strob DAT data data DAT.OUT data output data out DATA IN data input data in Dack data acknowledgment date aeknowledge DRQ data request data request request cf. To enter load MRQ memory request memory request RAS my bitters say row address strob Ruy completed ready RFRSH update refresh SEL choice select

For the 80 processor layout, 1 processor, random access dynamic memory 2, fixed program 3 memory, cathode ray tube controller 4, direct memory access control 5 DMA controller, 6 serial transfer controller, 7 counter timer circuit, 8 keyboard interface, 9 printer interface, 10 port decoding circuits, 11 memory address interfaces, 12 memory output drives, 13 program memory address interfaces, 14 program memory output drives, 15 clock generators, 16 frequency dividers and 17 bus drive circuits, which are also known in the prior art terrain control circuitry. The connection between the units of the arrangement is made by means of the inner bus 100, the inner data bus 101, the outer address bus 102 and the outer data bus 103. The known units referred to are delimited by a double line in the drawing to distinguish them from the new units.

In the drawing, the units with which the known arrangement is completed according to the invention are indicated by a single line. The first such unit is a cycle control delay circuit 18, the internal structure of which is illustrated in FIG. One of its inputs is connected to the MRQ memory request output of processor 1, its corresponding output is connected to one of the inputs c, m of memory 11, and one of its outputs is connected to the CAS and RAS clock inputs of memory 2. its input group is connected to the internal address bus 100, and its other input group is connected to the output of the display address counter 22. The multiplexer output of address 21 is connected to the external address bus 102. The write input of the display counter 22 is connected to the display start register 23 controlled from the external data bus 103. The selector input of address 21 multiplexer is controlled via line 203 from the Q output of type D flip flop 20 and is also connected to line input Ld write input Ld.

The reset of the display address counter 22 via line 200 is provided by one of the edges of the controlled display sync signal, and is traversed via line counter 204 through line 204 by the negative output of type D 19 flip flop and line 204 controlled by cathode ray tube controller 4 DACK input. The flip flops 19 and 20 are controlled by a logic circuit consisting of 26 inverters, 27 inverters, 28 NOGs, and capacitors 29 based on a signal of the 1x processor RFRSH update output; .

The static input D of the flip flop 19 is controlled by the negated output of the flip flop 20 and its Cp stroke input is connected to one of the outputs of the frequency selector 16. The line 202 is connected via an inverter to the enabling input En of the bus driver circuit 17.

The outer data bus 103 is connected via the buffer register 24 to the DATA IN data input of the cathode ray tube controller 4 and can be connected to the array 25 via an interface 25. The keyboard 8 connects to the keyboard, the printer interface 9 to the printer.

FIG. 2 illustrates the structure of a clock control delay circuit 18 comprising an amplifier 40 connected to the MRQ memory request output and a series of inverters 41, 42, 43 and 44 connected in series, and a capacitor 45. Each element provides low latency and isolation and provides for the correct timing control of RAS and CAS cycle inputs and memory address interface 11.

Fig. 3 shows an arrangement of units formed between the cathode ray tube monitor 34 and the cathode ray tube controller 4, the basic function of which is to display the appropriate strings on the screen. As in Fig. 1, the known units are here delimited by a double line.

This part of the arrangement includes a character generator 30, which inputs A3 ... A9 receive character-defining codes via a 110-character bus from the cathode ray tube controller output CC0 ... CG6, and inputs A0, A1 and A2 allow character lines to be assigned. . The outputs LC0 ... LC3 of the cathode ray tube controller 4 provide the control signals of the strings. The output of the character generator 30 is connected to a parallel input of a shift register 31, and its serial output is connected to the serial input of a video signal decoding and drive circuit 33. The display mode is determined by the state of the pipe line register 32, which is connected via control bus 11 to the cathode ray tube controller 4 and directly to the circuit 33. Circuit 33 directly controls cathode ray tube 34 monitor.

Known elements of the arrangement also include a clock generator 39 and a frequency divider 38 controlled therefrom which also performs pulse shaping.

According to the invention, two multiplexers 36 and 37 are used, wherein the multiplexer 36 has inputs A1 to A4 and 81, B2, B3 connected to the outputs LC0 to LC3 as shown in the drawing, and outputs Y1 to Y3 are the character generator A0. They are connected to input A2 and output Y4 is connected to the VT video block input of circuit 33. The output Y1 of the multiplexer 37 is connected to the thread input Cp via the wagon 302 and the output Y2 via the line 303 to the control input 32 of the pipe line register 32. The input of Al is directly connected to the output of the clock generator 39, for example, with a frequency of 12.5 MHz, and the input of A2 is connected to the eight-division B output of the frequency divider 38. This output leads via line 304 to the clock input CL of the cathode ray tube controller 4. Frequency divider 38 also has two and sixteenth divider outputs 2 and: 1E which are connected to inputs B1 and B2 of multiplexer 37.

The external data bus 103 is connected to a storage register 35, the output of which is connected to the inputs of the two multiplexer SEL selections 36, 37.

The processor arrangement according to the invention works as follows.

Referring to Figure 1, an update of the information content of the screen is described. In the case of the referred known terminal 80 processor element terminal, the update is triggered by an active state displayed at the output of the cathode ray tube controller DRQ request request, which is connected to the completed RDY input of the DMA controller 5. The 5 DMA controllers are initialized for byte transmission. In response to the data request, the DMA controller 5 takes control of the system from processor 1 in a known manner and performs a regular memory / port operation, which transmits one / bits of full image content from memory 2 to cathode ray tube controller 4 and returns control to the system. For 1 processor. This process is repeated cyclically. If the system clock is 2.5 MHz and 2000 characters can be displayed on the screen, it will take approximately 8 ms to refresh the entire screen. This also means that the precessor 1 has only 20 to 8 = 12 ms of free time per display period of the 20 msec image.

Regardless of the image content update outlined here, the dynamically-structured memory 2 also needs a specific upgrade to keep the information stored. Dynamic Random Access Memory typically requires 128 refresh cycles every 2 msec, an average of 15.625 microseconds per cycle. The Type 80 processor system solves this update by generating an update signal each time it reads-41, which is displayed on the RE FRSH update output, while simultaneously controlling the MRQ memory request output and an update bit in the lower seven bits of its cymb generates an address that advances one time per update and repeats every 128 update cycles. In this way, each memory is updated with a so-called. "Truncated reading from memory 2 is sufficient to preserve stored information. A Z 80 Type 2.5MHz processor produces 7.6 microsecond refresh cycles even when running the worst upgrade program possible. Therefore, even in the worst case scenario, the memory 2 is over-updated at least twice.

In order to understand the present invention, it is also necessary to examine the time needed to update the image content. A standard image of 2000 characters (25 lines, 80 characters per line) has a duration of 20 ms. Excluding the retraction times from the total image time, it is obtained that the cathode ray tube controller 4 requests an average of 8 microseconds at intervals.

The essence of the operation of the arrangement according to the invention is to combine the information needs of the screen with the updating of the dynamic memory and, as will be seen, reading the character information also solves the updating of the memory 2. This option is created by the fact that the cycles that control memory refresh occur at intervals of 7.64 ps on average, the screen needs a new character after an average of 8 / s, and enough time is needed to refresh the dynamic memory. twice as often to initiate memory access (reading). In addition, consecutive characters are located on consecutive memory addresses, so read out the characters in the correct order for the update. However, when the screen does not need to receive new characters (eg during rollback), the memory should be updated in the conventional manner. Accordingly, according to the present invention, the data needed to update the information content of the screen is read from memory 2 during the update cycle of the Z 80 processor and transmitted to the cathode ray tube controller 4, thereby updating the memory 2.

The information needed to update the image content is stored in successive addresses of the memory 2. Since the memory 2 can be used for a variety of purposes other than storing the characters representing the image content, its information storage capacity is significantly higher than that required for image updating. Reading the character information is repeated cyclically for each image. It is understood that at the beginning of each image, the start address of the memory 2 for storing the image update information must be determined. This task is performed by the start address register 23, into which the port decoding circuit 10 writes said external data bus start address, more precisely its first eight bits with the highest local value. The address of memory 2 requires sixteen bits. At the beginning of each image, the layout receives a synchronous signal from the controlled display over the line 200, which writes this starting address from the display address register 23 into the sixteen-bit display address counter 22 (the lower eight bits are then taken as zero).

The address multiplexer 21 connects the external cfmbus 102 to the internal cfmbus 100 or, depending on the value of the signal at the SEL selection input, or the output counter 22 of the display address 22. By default, the inner address bus 100 is coupled to the outer cfmb bus 102.

The processor 1 cyclically performs a memory update operation as described above, wherein the processor 1 cyclically performs a memory update operation as described above, wherein the processor 1 controls the RFRSH update output and the MRQ memory request output. As a result, the signal on line 202 disconnects the external data bus 103 from the internal data bus 101 by disabling the Enable input En of the bus drive circuit 17 and controls the flip flop 20 via inverter 26. The state of the latter changes only when the cathode ray tube controller 4 needs a character input and this fact is indicated by the active status of the DRQ data request output which controls the static input of the flip flop. After examining the execution of the data request, assume that the output state of the DRQ data request was active and the 20 flip flop rolled over. As a result, the active Q output through line 203 activates the selector input SEL of the address multiplexer 21 and the output of the display address counter 22 is coupled to the external address bus 102. The address of the memory 2 is now determined by the memory starting address stored in the display address counter 22, which contains the value of the current character to be updated.

The active state of the MRQ memory request output of the processor 1 controls the cycle control delay circuit 18 (FIG. 2) and outputs its output sequentially control signals of RAS and CAS corresponding polarity, including the enable address of the memory address interface 11, allowing the value connected to the external address bus 102 addresses the memory 2. As a result of the addressing, the character code is displayed on the external data bus 103 and fed to the input of the buffer register 24. Addressing the memory 2 also updates it.

At the end of the processor update cycle, the trailing edge of the RFRSH update output signal, after delaying and signaling the inverter 27, the capacitor 29, and the NEMES gate 28, flips the flip 20 to reset to buffer register 103 via line 203. then the address multiplexer 21 is reset. For the next clock signal, flip flop 19 and control of line 204 advances display address counter 22 one by one to correspond to the address of the next character while simultaneously controlling the DACK data acknowledgment input of the cathode ray tube controller 4. As a result of this, the reading of the character value stored in the buffer register 24 of the cathode ray tube controller 4 is completed and the character output is completed.

This process is repeated until all screen content is transferred. When the image is complete, an image synchronization signal is received through the line 200, which controls the display address counter 22 and resumes from the initial memory address a new update cycle for a full screen area.

If the cathode ray tube controller 4 does not need to import another character during the CPU refresh cycle, it does not control the output of the DRQ data request (e.g., during representational runtime), and the known traditional memory refresh applies. Switching between the two different update modes will inevitably result in asynchronities, but these will not cause any problems due to overfitting at least twice. Thus, as described herein, the screen is updated automatically during the cycles of the processor 1 when it needs to refresh the dynamic memory, thus saving the time required for the separate screen refreshment described above and requiring 8 ms per 20 msec image.

Reference is now made to Figure 3. A known part of the arrangement outlined here corresponds to the INTEL 8275 type controller and its operation is described in Chapter 7, pp. 43-90 of this manual. pages. This operation is referred to only to the extent necessary to understand the present invention.

The character generator 30 is a 1 kbyte read-only memory, which can be used to implement a standard 128-element character set with an 8x8 character matrix.

The cathode ray tube controller 4 stores a number of characters corresponding to a string and sends a code specific to each of the eight clock signals of the clock generator 39 to the character generator 30 via a 110-character bus that outputs a combination of eight characters for a given string of characters. it is written to the shift register 31 every hour. The shift register 31 is incremented by undivided clock signals so that at its serial data output, the video signal decoding and drive circuit 33 receives from 8 to 8 information bits per character and per line. The LCO ... LC3 outputs of the cathode ray tube controller 4 determine which of the 10 raster lines on the screen belongs to a given string. For example, under the last 3 rows, the LC3 output is high, and this controls the VT video block input of the circuit 33, i.e. the last two rows are always dark, which corresponds to a string of characters. Signals from the LCO ... LC2 outputs are sufficient to distinguish 8 lines within a character.

Upon receiving an attribute character, the cathode ray tube controller 4 transmits appropriate control signals to the pipe line register 32 via the control signal bus 111 and provides a state (e.g., highlight, blink, etc.) dependent on their value to the circuit 33.

The mode of displaying the 8x8 characters outlined herein is hereinafter referred to as "lowercase mode," and the arrangement of Figure 3 then operates in a known manner.

If the task is to display 16x16 characters, then the "lowercase mode" mentioned above is no longer appropriate. Larger character rendering gives you greater control over a greater distance, and can be used well in any area where less information is needed on the screen surface.

Displaying 16x16 size characters in the layout of Figure 3 is an optional feature that can be assigned via the data bus 103 depending on the contents of the single-bit capacity storage register 35. Operation is as follows.

The active state of the storage register 35 controls the SEL selection input of the multiplexers 36 and 37, and as a result, they are connected to the outputs with input B. It can be seen that line 303 is connected to output 16 instead of output 8, and line 302 to output 2 instead of output 1. This solution is essentially equivalent to halving the frequency of the clock generator 39 for the shift register 31 and the pipe line register 32.

On the 110-character bus of the cathode-ray tube controller 4, the code of all the characters corresponding to a single line is displayed per raster line. Referring to Fig. 3, it can be seen that the fastest changing LCO output is not wired in "uppercase mode", instead the LC1 ... LC3 outputs are connected to the inputs B1 ... B3, respectively. In this way, the character generator 30 proceeds by two rows per two raster lines, and the eight raster lines for displaying a single character string are read out over 16 raster lines. This results in a doubling of the vertical size of the displayed image.

The shift register 31 also reads twice as long, i.e. in the horizontal direction every second raspentent the circuit 33 receives new information by stepping the shift register 31. Characters with originally horizontal n \ olc grid points have now become 16 grid points wide. In this way, almost every 16th step is entered in the shift register 31, and now the hexadecimal clock of the 303 arriving at the LOAD input line fulfills this condition. In "uppercase" mode, the displayed character area has quadrupled.

It has been mentioned that the shift register 31 only receives new image information to the circuit 33 at every other clock rate. Since the control clock of the cathode-ray tube 4 has not changed through line 304 in capitalization mode, it may appear that every second character is lost during such operation. If we were to store the characters in memory 2 in the "lowercase" mode, that would be the case. However, in upper case mode, only up to 500 characters can fit on the screen compared to the 2000 discussed above, so it is easy to resolve each character in the text to be displayed at every second memory address.

In this way, every second memory space is freed up and the time needed to read it is available. According to one aspect of the invention, these are e.g. odd clock strokes and memory addresses can be used to transmit attribute characters. The layout of the attribute characters is transmitted to the cathode ray tube controller 4 in the same manner as the characters to be displayed, but the latter recognizes them and, upon arrival of the attribute character, transmits a neutral state for the character generator 30 to the character bus Control signal 111 transmits via bus 33 to pipe line register 32 which transmits code corresponding to the attribute character bus via control signal bus 111 to pipa line register 32 which brings the circuit 33 into a state corresponding to the attribute character. Since only every second clock is transmitting data from the shift register 31, the transmission of the attribute characters to the screen "remains invisible and does not affect the actual position of the displayed characters.

The layout shown in Figure 3 is thus capable of displaying 16x16 dimensional characters with a 1 kbyte character generator 30 and even assigning an attribute character to each character. The use of attribute characters does not interfere with the character display at any frequency.

Claims (9)

A processor arrangement with a Z 80 processor for performing terminal functions, comprising a processor (1), associated dynamic random access memory (2), read-only program memory (3), a DMA controller (5) providing direct memory access, between said units an internal and external address bus (100, 102) for establishing a connection, an internal and external data bus (101, 103), for establishing a connection between the external address and data bus (102, 103) and the memory (2) and program memory (3). coupling units, a bus drive circuit (17) coupled to the external data bus (103), a cathode ray tube controller (4), the data input (DATA IN) of which is connected to the external data bus (103) via a buffer register (24); data request output (DRQ) and data acknowledgment input (DACK) and display connected output, processor (1) has memory request output (MRQ) and An update output (RFRSH), comprising an address multiplexer (21), the output of which is connected to an external data bus (102), one input group is connected to the internal cfmbus (100), and the other input group is a display containing the initial display memory address. is connected to the output (22) of the address counter, the memory request output (MRQ) of the processor (1) is connected to the cycle inputs (RAS, CAS) of the memory (2) via a cycle control delay circuit (18), the update output (RFRSH) of the processor (1) connected to the stroke input (Cp) of the type flip .Top (20) and to the reset input via the delay circuit, the static input (D) of the flip flop (20) is connected to the data request output (DRQ) of the cathode ray tube controller (4). address multiplexer (21) for selection input (SEL) and buffer register (24) for scan input (Ld), inverted output controlled by clock of layout a second flip flop (19) connected to the static input (D) of the display address counter (22) on the one hand and the data acknowledgment input (DACK) of the cathode ray tube controller (4) on the other, and the display address counter (22) a line (200) of the sync signal of the controlled display is connected to the delete input. Processor arrangement according to claim 1, characterized in that the delay circuit is formed by a NEMES gate (28) connected directly to one of the inputs and the other input via an inverter (27) to the update output (RFRSH) line (202), A capacitor (29) is connected between its output 27 and its ground terminal. Processor arrangement according to Claim 1 or 2, characterized in that the cycle control delay circuit (18) is separated by an amplifier (40), four series inverters (41, 42, 43, 44) connected to its output and the last two comprising a capacitor (45) coupled between the inverter (43, 44) and ground. 4. A processor arrangement according to any one of claims 1 to 6, characterized in that the input of the display address counter (22) is connected to the display start address register (23) and its input is connected to the external data bus (103). 5. A processor arrangement according to any one of claims 1 to 6, characterized in that the update output (RFRSH) inverter (25) is connected to the enable input (En) of the bus drive circuit (17). 6. A processor arrangement according to any one of claims 1 to 6, characterized in that an interface (25) for connecting to the external storage bus (103) is connected to the mass storage devices. Arrangement for displaying small and large characters on a cathode ray tube controlled cathode ray tube monitor, wherein the cathode ray tube control (4) character bus (110) is connected to a small character generator (30) character selection input (A3 ... A9), ) output is connected to the parallel inputs of the shift register (31), its serial data output is connected to the input of a video decoding and drive circuit (33), the output of this circuit (33) is connected to a cathode ray tube monitor (34), associated with an input (32) of a pipe line register (32) connected to a further input of said circuit (33), a central clock generator (39) connected to a frequency divider (38) having an output (£) connected to the clock input (CL) of the cathode ray tube controller characterized by containing first the first input group of the multiplexer (36) connected to the character generating input (A0 ... A2), except for the highest local value, the character generator (30) being connected to the row determining outputs (LC0 ... LC3) of the cathode ray tube controller (4), the largest local value input of its second input group (to ground point B4, its other inputs (B1 ... B3) are connected to the remaining outputs (LC1 ... LC3) apart from the least significant local output (LC0) of said queuing outputs, and include a second multiplexer (37 ), one output line (302) of which is connected to the stroke input (Cp) of the shift register (31), the other output line (303) is connected to the internal input (LOAD) of the shift register (31) and the write input of the pipe line register (32) input group with clock generator (39) and first pitch output (8) of frequency divider (38), second input group pedi g is connected to the second and third split outputs of the frequency divider (: 2,: 16), the selector input (SEL) of the two multiplexers (36, 37) is used to determine the lowercase and uppercase mode. They are connected by 196,096 shoot lines. Arrangement according to claim 7, characterized in that the maximum location value output (Y4) of the first multiplexer (36) is connected to the video block input (VT) of the video signal decoding and drive circuit. Arrangement according to Claim 7 or 8, characterized in that the lower case mode has 8x8 raster point characters and the upper case mode 16x16 raster point characters, and the division output (B, 2,: 16) of the frequency divider (38), respectively. 8.2 and 16.