DD231971A3 - SCREEN REFRESH CONTROL - Google Patents

Abstract

The invention relates to a screen refresh control for systems with such microprocessors, the Refreshzyklen perform in the system existing dynamic memory. The aim of the invention is the avoidance of additional effort by a separate image refresh memory, performance degradation of the system by cyclic program interruptions and disturbances of Refreshdurchfuehrung dynamic memory. The object of the invention is a screen Refeshsteuerung using a DMA-capable CRT controller, which accesses in the transparent DMA mode, using refresh cycles on the image memory defined as part of the main memory, wherein the Refreshforderungen dynamic memory must be met. The object is achieved by performing with the aid of a flip-flop circuit and address counters and drivers during part of the refresh cycles DMA read cycles in such time sequence and with gapless, cyclically repeating address sequence that thus the Refreshdurchfuehrung for the read dynamic memory bank and by a common RAS line and thereby resulting RAS-only refresh is also ensured for the remaining memory banks. Fig. 1

Description

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Title of the Invention Bioframe Refresh Control Field of the Invention

The invention relates to a screen refresh control for systems having such microprocessors that perform refresh cycles for dynamic memories present in the system. 10

Characteristic of the known technical solutions

The most commonly used solution for refreshing a screen is the use of a separate refresh memory that is constantly accessible to the on-screen controller or the CRT (Cathode Ray Tube) controller (e.g., DE-OS 3,222,704). There must be the possibility of multiplexing the address, control and data lines, so that the microprocessor system to which the screen is connected, can also access the frame buffer. The access by the higher-level system is generally in the times in which the beam is returned to the beginning of the line or image to avoid collisions with access by the screen control.

This requires additional control effort.

Another technical solution, which is preferably when using one for DMA operation (DMA = Direct Memory Access)

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suitable CRT controller is to use as part of the image memory part of the system memory and access to this via a DMA controller in DMA mode. However, depending on the organization of the screen and the DMA traffic, up to 30 % of the time is required for the DMA operation required to refresh the screen, which results in a significant system degradation and problems with time-critical processes (Intel: Component Data Catalog pp. 9-358).

The proposed in DD-PS 148 267, a transparent DMA traffic using refresh cycles organizing and thus working without loss of time for the microprocessor system solution for refreshing a small LED display with relatively few places (eg 32) can not on the conditions transmit a screen typically representing about 2K characters, since in unfavorable instruction sequences with a minimum number of refresh cycles (and possibly additional use of WAIT phases), either the refresh cycles remaining for the refreshing dynamic memory are insufficient in number, in order to fulfill the refresh requirements (in general 128 refresh cycles per 2 ms are required) or not all of the 128 refresh addresses are detected in every 2 ms by the refresh process

 For the same reason, the principle proposed in DD-PS 201 213, with the refresh cycles left by the transparent DMA traffic under self address control, to perform an autonomous refresh, not to the conditions of the screen with its greater need for DMA cycles per Refresh period transferable. In addition, an additional effort is required to carry out the refresh process.

Object of the invention

The aim of the invention is a screen refresh control, the the known technology solutions inherent deficiencies - additional effort by separate image memory with devices for multiplexing the address, control and data lines;

Power reduction of the microprocessor system and cyclic program interruptions; Failure to Refresh Dynamic Memory with Transparent DMA Operation Using Refresh Cycles - Eliminated.

Explanation of the essence of the invention

Technical task

The invention has for its object to develop a screen Refreshsteuerung with a suitable for DMA operation CRT controller, which, without interrupting the current program of the microprocessor system, in the DMA mode using provided by the microprocessor refresh cycles on as Part of the main memory of the microprocessor system defined image refresh memory accesses, in spite of the use of refresh cycles for the DMA access, the refresh requirements of dynamic memory circuits, from which the image memory containing the RAM is constructed, should be met.

Features of the invention

According to the invention, the object is achieved in which realized with a DMA-capable CRT controller screen refresh control during a depending on the nature of the expiring commands more or less large part of the microprocessor provided refresh cycles using a flip-flop circuit and of address counters and drivers performs DMA read cycles for cyclically filling the in-controller line buffers. In this case, the refresh condition for the read dynamic memory bank is satisfied by the timing of the DMA read cycles and the gapless cyclically repeating address sequence, since refresh is performed when a memory cell is read in the entire addressed row. All dynamic memory banks are connected to a common RAS line, so that during DMA reading the picture memory contains

the bank is RAS-only refreshed for all other memory banks at the same time. The data transfer to the line buffer of the CRT controller takes place during DMA reading via an interposed 8-bit latch register, which takes over the data at the end of the DMA read cycle and stores it until the switch-off edge of the write pulse for the CRT controller. During the DMA read cycles, the CPU bus drivers are placed in the high-resistance state by a control line generated by the flip-flop circuit

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embodiment

The invention will be explained in more detail below with reference to an exemplary embodiment which contains the essential parts of a microprocessor system with a U 880D (UA 880 D) CPU in conjunction with a 64K byte composed of 1 6Z-bit DRAMS Memory shows. Furthermore, in the exemplary embodiment, a screen refresh control with a DMA-capable CRT controller of type 82 75 is shown, which performs screen refreshing by means of DMA access to a region in the 64K main memory. The accompanying drawings show:

Fig. 1: Block diagram of the essential parts of the microprocessor 'zessorsystems with 64 K memory, screen refresh and DMA control

Fig. 2: Explicit representation of the DMA controller Fig. 3: Diagram of a DMA read cycle

The CPU 1 is connected to the remaining parts of the system via address bus driver 2 for the address bus ABO-15, data bus driver 3 for the data bus DBO-7 and control bus driver 4 for the control bus MREQ, IORQ, ID, W and IT. Through the line BUSAK the ZVE1 can put the drivers 2-4 on the NAND gate 5 after previous bus requests in the high-resistance state.

The CRT controller 6 (type 8275) has two internal line buffers, each with max. 80 characters to represent a line of characters on the screen. While from one of the line buffer on the character generator 7, the shift register 8 for parallel-to-serial conversion and the synchronization circuit 9 (output signals VIDEO, SYNC, INTENS) a character line is displayed on the screen, the 2nd line buffer to the beginning of the following line of characters from the are filled in the main memory 10 arranged image content memory. For this purpose, for each character to be read, the CRT controller 6 outputs a DMA request signal DRQ which is asserted by the DMA controller (FIG. 2) by the DMA acknowledge signal DACK when the DMA read is performed. The data byte applied to the data inputs DO - D7 is written into the line buffer with the write pulse WR CRT.

For the DMA read refresh cycles are used, which are recognized on the always preceding M1 signal. When M1 and MREQ are active, flip-flop 11 (FIG. 2) and subsequently FF12 are turned on as shown in the diagram of FIG. The FF11 and 12 are causally needed to prematurely turn off by connection to the gate 13, the derived from MREQ = 0 RAS signal for the dynamic RAM and thus to meet the requirements of DRAM circuits with respect to the precharge time t _R p.

With respect to the DMA operation, F1 = 1 is used to assert the turning on of the bus repassing FF15 (Figure 2) while the DMA request signal DRQ = 1 is applied to AND gate 14. By "Fj = 0 at gate 5, the CPU-side bus drivers 2-4 are disabled (high impedance), whereas the drivers 16 which place the DMA address formed by the address counter 17 on the address bus are activated. to allow typical screen capacities of 16x64 or 24x80 characters, an 11-digit address sequence starting at 0, while the more significant 5 address bits at the inputs of the drivers 16 are selectively set to 0 or 1, thereby reducing the location of the image content -

Memory is set in the 64K memory 10. The address counter 17 is brought into the initial state 0 by a pulse derived from the beginning of the picture change signal in the synchronization device 9; the counting up takes place in accordance with the number of characters that can be displayed on the screen at the end of each DMA reading, so that a complete address sequence is created.

The flip-flop 18 (Figure 2) is delayed from FF 15 for half a clock period. By conjunctively linking F3 and the delayed F4 signal in Satter 13, RAS. = 0 for the DMA read cycle. RAS = 0 is applied to all four 1βΚ memory banks so that the memory bank selected by one of the signals CAS1-4 is read and in the rest a RAS-only refresh is performed.

The source signal for CAS1-4 is CAS * derived in gate 19 from RAS when either a DMA cycle is present (¥ 4 = 0) or access to the 64K DRAM area is not through MEMDI = 0 (memory lock signal, the but does not prevent CRT DMA access) or "CSPROM = 0 (activation of a PROM area, eg, initial loader) is prevented.

CAS * is delayed as S at the address multiplexer 20 where the address bits ABO-AB13 are present. By S is switched from the low-order 7 address bits (row address, taken over with RAS in the memory circuits) to the high-order 7 bits (column address, with CAS1-4 taken). The further delay of CAS * results in CAS which is linked in decoder 21 with AB14 / AB15 to CAS1-4.

The memory read data is applied to the data bus via the drivers 22; Activation of the drivers 22 is done by the control line "RD RAM, which is formed via gate 23 in the DMA read cycle by the conjunctive connection of 73 and F4.

Since, using commercially available memory circuits, the read data on the data bus can not be provided in a timely manner (the refresh cycle is generally limited to 2 clocks) to satisfy the required data set time of the CRT controller, the data will be at the end of the DMA read cycle

with the STB formed by gate 24 in the latch register 25 and to the end of the write pulse WR, CRT, which is formed by F4 and with the help of the open-collector gate 26 with the WR generated at OUTPUT commands of the ZVE 5 OR , saved.

The DMA read operation is completed by the acknowledge signal DACK formed with the gates 27 and returned to the CRT controller. If the line buffer is not yet filled, the CRT controller will then output the next DMA request DRQ, which will be processed in the next refresh cycle.

Claims (1)

-S- G06F / 257 932/2 invention claim Screen Refresh Control for systems with such microprocessors that perform refresh cycles for on-system dynamic memories, with a DMA-capable CRT controller, turn-off drivers for the address, data, and control buses of the microprocessor, and a DMA address counter with subsequent turn-offs Drivers, characterized in that the CRT controller (6) is provided with a DMA request line (DRQ) and a DMA acknowledge line (DACK) at one of the refresh cycles of the microprocessor (1) in the presence of DMA requests from the CRT controller (6) DMA controller which can be activated, constructed as a flip-flop circuit (15; 18) and which in turn is connected to the data, address and control bus drivers (2-4) of the microprocessor (1) and to the counting input of the 'DMA address counter (17) and the subsequent address bus drivers (16) is connected, wherein the reset input of the address counter (17) with a picture change signal processing stage in the synchronization circuit (9) "is connected to ensure the zero position of the address counter (17) at the start of the image that the flip-flops (15; 18) are connected together with gates (13; 19; 23) in such a way that the output of the gate (13) enables RAS-only refresh cycles in the remaining memory banks simultaneously with the RAS inputs during DMA read cycles in a memory bank all memory banks of the dynamic memory (10), the output of the gate (19) via a delay circuit with the address multiplexer (20) and the decoder (21) for the CAS inputs of the individual memory banks associated signals CAS1-4 and the output of the gate (23) are connected to the driver (22) for the memory read data and further that the strobe input STB of an input side of the driver (22) for the memory read data and the output side connected to the data inputs of the CRT controller (6) latch Register (25) is connected to the output of the gate (24) connected to the flip-flop (15; 18) of the DMA controller in such a manner that the in the latch register (25) is connected across the end of the DM A read-out memory provided data to the inputs of the CRT controller (6) and the write input WR CRT of the CRT controller (6) via a gate (26) with flip-flop (18) is connected.