DE2717700A1 - MEMORY ACCESS ARRANGEMENT - Google Patents

Description

Boeblingen, April 15, 1977 jo- sz

Applicant:

International Business Machines Corporation, Armonk, NY. 10504

Official file number:

Applicant's file number:

New registration BC 976 012

Representative:

Patent assessor Dipl. -Ing. O. Jost 7030 Boeblingen

Description:

Save access arrangement

709345/0874

SpeicherzuqiiiiSoi ι order,

The present invention relates to an all-in-one memory access arrangement Datenveraibei tuiicjssystem, with the key to control the memory access uses v / eidi.-n.

USA-Paieni 3.924.823 describes a multipio-processor system with control circuit and buffer devices, which ensure the addressability of an operand \ n- \ (kr execution of an instruction in one of the processors, ο bv / ofil an address translation buffer by another processor .-r - Einiruc), which is necessary for addressing this operand, is made invalid in an asynchronous operation. Due to the special buffer devices, the addressability of the cables which enihult the relevant operand is maintained until the current command has been completed. Addressing keys are not used with this sysler. Insurance V '. ! Shifting an acute program status word (PSW) into a special register for an old PSW, as well as entering a new PSW in the register for the acute program status word in the event of a machine error or a program interruption in order to obtain an address used by the interrupted program It has been known for a long time, for example, from the systems of the IBM System / 360 and IBM System / 370. These known methods or devices for maintaining addressability, however, are not ideally suited for all types of systems , here's an improvement on the

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Maintaining addressability in the event of errors and program interruptions specify which are particularly suitable for memory access systems in which keys are used for addressing will.

This object of the invention is achieved by what is specified in the main claim Characteristics.

Further advantageous refinements, developments and features of the The subject of the invention can be found in the subclaims.

When using the invention, the advantage is essentially achieved that, in the event of errors and program interruptions, the addressability of memory access systems that use address keys work, sustained.

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An example of the invention is illustrated below with the aid of drawings described. Show it:

Fig. IA-1 in general the principle of address lock selection to {', round from Storage access rights (ft; -St eucrsignal s), which identify the type of access;

Fig. IA-2 generally shows the principle of address translation for memory access, where the logical input address from a specially generated Ac'ressr.clilüssel and the address appearing in the program, consists}

FIG. 1B shows an overview of the various possible types of memory access; FIG.

IC in block form shows an overview of a data processing system with expandable main memory, which is described as an execution example;

Fiß. ID a specific embodiment of the arrangements shown in Fig. 1A;

Fig. 2Λ an overview representation of the processor operations and I / O operations occurring memory accesses, as well as the various Address ranges;

Fig. 215 is an explanatory diagram of memory access operations in I / O operations;

Fiß. 3Λ Details of an I / O subchannel that is sent with each subchannel command receives an address key and this for each data access for execution.

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Fig. 3Β the relevant parts of an, I / O lünials, the a plurality of Connecting lower channels with a memory rpri ori lätswahl schal tuug;

Fig. 3C in block form an i> pei cherpr iori täaur.wahlr.chal tunp with a Kana 1 a ii r. choice scha Ii imp ,, through which I / O channels and processor via the Haiipt ;; memory bus with memory and Uoborsel zer are connected, and the ever a selected address key and an address for memory access hand over;

Fig. 3D details of an act: i .vadressschlüsso l-Ausv / ahlsclia) t nng, in which also an Opc-randcnbereichs.Tb (; lei ch can be reached;

4 shows details of a processor which is used for memory access control with address keys are relevant;

Fig. 5 shows the partition format of the address key register in a preferred one Detailed example;

6 shows the content format of the segment registers provided in embodiment example 1;

Figure 7 shows details of the input and output control of a single bit position in the address key register;

8A schematically shows the processes when a command for loading is executed or storage of a segment register;

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Fin · Hb schomatically at the events. Execution of a Nciehls for loading or storing the · κ Adres <; scli] ü ;; se] register from or into a memory;

CC schematically shows the processes when a command for loading is executed or Abr.pi-.iche.rn of the address key register from or into a General registry;

9Λ and 915 a block diagram of a preferred embodiment of the Uebersel / er :; Geinnss Fig. IC, which converts a 19 hit long logical nose address into an ? A bit long physical address for memory access;

9C, 9D-1, 9D-2, 9K, 9F-1 and 9F-2 details of the in Fig. 9Λ / 9Β in Block form shown Uebcrsefzers;

Fig. 90 illustrates the operation of the look-ahead circuits shown in Fig. 9C for respective selection of the internal storage (basic storage), external storage (Additional storage) or asynchronous storage, as well as the interpretation of the 24 Bit Jangen physical address by the selected storage unit when accessing:

10 shows a circuit arrangement in the processor for selecting between the operating modes "memory protection without translation" and "memory protection with preferential translation";

Fig. 11 Memory protection control circuits for use in translation-free. Operating mode;

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12 shows the format of a Spe (Him - Hpeioher-Hefchl s;

Fig. 13Λ rc ·] cvnntc parts of the) Όπη; ιΙ ;; a Freißabc- / Spc: rrbef ulils to determine the Ho tr icbsart s with. r.special oil] er address range.saur.selection (e.g. (iber.'ic t zuiij ', ;; ire ic addressing with Speiehersehut v., memory protection with Weber setting, Op e.randenbcreichs comparison);

Fiß. 1315 consecutive. To the.tlindc of an address.ssschlii.süt'l grand general, If, in the event of an interruption, Operandcnreiclisabp.l.cich takes place;

Fiß. 14 a switching arrangement for an alternative storage mode before rscliutzbetriebsart with translation, what an alternative? .u the storage mode with address key translation; represents;

Γίβ. 15 schematically shows an alternative method for address key translation, that in a processor as an alternative to the translation process; with can serve multiple stacks of registers;

Fiß. 16 Access to parallel basic memory modules using several active ones Address key, in a multiprocessor system;

Fig. 17 shows control circuit details from the processor for performing the load / save segment register instruction shown in Fig. 8A;

18 schematically shows the processes for loading and storing in the event of class interruptions.

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1. Bcsrhrci bun ^ an embodiment

Pig. IA and Fig. IB show the essential characteristics of a Auslirunp.sbt: i game of F.rf iiuliinf · ,. Fiß. 1Λ shows a Λ dress key selection circuit ? .0, dit: depending on the type of memory access request (which are indicated by signals on the J_.leitungcn 21, 22, 23, 2-1 or 25) selects one of the key register sections 31, 32, 33, 34 or 3 5, which contain the following keys: CS key, IS key, OPl key, OP2 key and OP3 key. The one of these keys which corresponds to the present memory access request is determined by the AAS selection circuit 20 as the active address key (A.AS) advised. This active address key controls the addressing of the main memory of the system during the next memory access, i.e. Retrieval or storage of data in main memory. In this addressing operation, the active address key AAS determines the Upper part (higher-valued places) of the logical address that is used by the system for memory access.

The signals on the access request lines 21, 22, 23, 24 and each represent a different type of access request that can be made by the channels and processors that are accessing the

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have the same main memory. These request lines are designated as follows in FIG. JA: I / O access, command access, OP1 access, OP2 access and OP3 access. If only one of these access.required.'isi gnal s occurs, then the content of the. relevant address key registerabsc.hnitt s is output as AAS. If several request signals occur simultaneously, the sequence in which the relevant: n address keys are output as AAS is determined by priority switching in the AAS selection circuit 20. A certain order of priority is given so that 7..Vj. an I / O access request for a Cyclc-Steal-Operalion has priority in order to issue the CS key first. The command fetch request is served as the second to the IS-Schlüsscl ali; To issue AAS. Third, the OPI access request is served in order to output the OPI key as AAS; Finally, the OP2 and OP3 access requests are served as fourth and fifth in order to output the OP2 key or OP3 key as AAS.

So there is a certain relationship between the different ones Types of access requests and the special key register sections.

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In cinc: rn Pro / .cssor, an address key register (ASR) contains the following sections: the IS switch section (LSS), which is the command call request for access to each instruction, and the SirhUiKseJrei'.isierabfichnitU · for the Keys OPl (OPlS) to OPi (OP3S), which correspond to the different types of operands. Accesses that were required to execute the commands.

In addition, each I / O subchannel has a cut-language CS key register section (CSS). ICs can also happen that several K / O subchannels request access to the main memory at the same time. Therefore, CSS priority selection circuits are provided to help with simultaneous requirements the CS key in a given Output order.

In addition, if several processors have access to the same main memory further priority circuits are provided to meet the requirements to operate these processors in a predetermined, specific order.

1A illustrates the invention in a processor system and channel unit in which active address keys are used and in

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only a part of the memory access rights possible in a Dalenverarbeilungssyslem on and for Kieli is used. Fig. 1Π shows a larger number of different types of access. The memory access types that can be used in a suitable system are limited to those that can be identified by the circuitry of the system. That is, it is required in the system circuits various arias ¹ of memory access can see sanforderun gen, in each case at the time when the access request in question occurs. Fig. IB shows more access scenarios than the arrangement shown in Fig. 1A. In FIG. 11Ϊ, eight types of memory access are divided into three access categories: (1) command access, (2) operand access and (3) an access category which is assigned to the processor features. Each channel contains K subchannels, and each subchannel has three memory access categories: (1) channel command access, (2) I / O data access, and (3) an access category for I / O events.

Each access category has at least one memory access type.

For any particular installation, only the memory access modes which are provided in the machine construction by an identifying signal, i.e. a memory request signal.

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So κ. Jl. the command access category in the system by a command sabru fs request signal marked. The operand access category can be identified in the system by six different types of operand accesses (Fig. IB). These are

divided into direct and indirect operand access types, with the sub-category of direct accesses including those accesses which use addresses which. are derived directly from the instruction, while the: Unlerkalegoric relates to such operands of the indirect accesses where the addresses are derived indirectly from <] he operand address of an instruction. Each sub-category has three different operand access types, which can be identified by the circuitry of the system as request signals for source retrieval, sink storage and sink retrieval. Any of these six operand access scenarios can be included in the design of a plant, and the relevant plant identifiable signals can be derived from each instruction, from the opcode and from the operand fields. The source fetch operand type relates to data used as the source of instruction execution; it is not changed, it is only used to create the results of a command execution. On the other hand, the Scnkenabcicherung - operand type refers to accesses for which the results

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of a command execution. The sink call operand type is the result of an earlier command execution, which is saved as Source: use / .t wi rtl to execute a subsequent command. For many data processing systems, however, it has been found practical to the Senkenabspeiche- Opcrandeiityp in the construction and the .Senkenabruf- OperandIy ρ to a single sink abspeirherungs / 'fetch operand ty ρ to summarize.

Processor event accesses are caused by the occurrence of internal processor events. re, such as data fields, machine errors, addressing messages, etc., which belong to a long list of known events which cause the usual processor interruptions. H . internal interruptions. The category of processor event accesses can include, for example, access to an area of main memory which contains an interrupt processing program and other programs for processing signals associated with the interruption and in which data relating to the interruption is still stored Related, for example final recordings.

Each channel has a plurality of subchannels that contain a plurality of

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different types of access. Gd belongs, for example, to each subchannel one: F./A data access category with the accesses arlen K / A-Abrui and li / A-Aljüjiei clieruun. . Some systems these two are Ruktion by Konsl yu a single Zugriffslyp together, called "lon one I / O request / Abspeicherungszugriff. The accesses associated with sub-channel functions are signaled by interruptions which: are external to the processor, ie external interruptions. Ka are usually used many external interrupts, such as the Gerriteschlussunlerbrechung, Cleräte- f chi it disruptive, since th I / O ~ he failed interruptions, etc.

In summary, it can be said that the invention makes it possible to influence the addressing processes in the main memory separately for each of the different types of memory access shown in FIG. 1B. The types of access shown in FIG. IB include the eight different types of memory access which are available to each processor and the four different types of memory access which are available to each subchannel . These. The possibility of separate influencing is given by providing a separate key register section for each of the access types which are provided in a system . The execution

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example, wolclics shown in Fig. 1A, uses only four different procec: s »or access sartun, vvclclic in the selected i: n üei. ^c ; piel are represented by an address list that has four different registers. The number of register sections in the address key register ASK can, however, be selected as desired according to the number of different types of access that are provided in the construction of the system.

In any case, each is identifiable by the circuitry of the machine Access type an ASR register section or a CS register section provided with appropriate devices in the AAS-Aus. selection circuit to read out a selected register section, if the corresponding access request is served, where then the content of the selected register section the active address key which the system uses as an address component to influence the addressing process for the relevant memory access. The following can apply to the address component given by the active address key AAS: (1) It can have a direct relationship to the physical address by concatenating the AAS with the adrcssc program so that both together have a physical address result in main memory; (2) it can be a fixed one

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»Enable memory access in main memory, as in the example the fig. 11 shown i si; (3). ': I c can be used to determine a shift Address for storage areas identified by keys

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serve, being within jedci; BcreichesYPrograiiiinadre hü cn required, as shown in Fig. 15 i «; t; (4) it can be even more flexible Type for the determination of relocatable addresses, whereby even within the areas identified by the key Address shift is possible, as it is in the exemplary embodiment of Fig. IA is shown.

The main memory input address represented by that shown in FIG Arrangement is provided is the combination of an active Address key AAS with an address appearing in the program. The latter is an address that the facility is in execution the program located, such as the instruction call address in the example address register, and the operand addresses in the instructions of the program. When a program is written, only im Addresses appearing in the program known. The application programmer cares The AAS operations only insofar as it combines its operand data separately from the program. The system programmer generally specifies the processor event access

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bcrciche and their contents, and the I / O programmer generally specifies the I / O channel command and event access areas and contents. In Fig. 1A, the AAS-Kdinpoiiciilc has K bit positions in the higher; a total of one input address; it is available for the system with 16 -IK bits .

In the arrangement shown in FIG. 1A, the input address is inclusive of the AAS field cs a logical Masc hinen Adresse, for which still requires a translation to get a desired • Store to be reached in the data processing system. On the on the other hand, in the arrangement shown in FIG. 11, the active address key AAS is used as a directly used restriction on the physical Address used which is not translated.

A. Stack translators with registers

The translator shown in FIG. 1A contains a plurality of segment register stacks with the numbers 0 to 2. Each key register section in the processor or in a subchannel contains at least one key with K bits with which each of the stacks can be addressed.

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The active: AdressschlusseJ AAS is entered into a Slapelruliessiereinrithtung -10 and decoded in order to select Δί · .ι \ desired stack. Then a segment register (SIl) within the addressed stack is selected with the more significant bit positions 0 - P of the component appearing in the program of the input ;; angsadrc ;; se. Bit positions 0 to 12 of the selected segment register contain an assigned block number which represents bit positions 0 to 12 of the physical address of a particular physical block in main memory which is then accessed.

The remaining bit positions 13-23 of the physical address, which Comprises 24 bits, indicate the relative byte address (D) within the selected physical block; they are identical to the relative Byte address D in the input address, where it is in the non-significant Bit positions (PH) up to 15 are available. Access to a specific The physical block is also controlled by character bits in the remaining bit positions 13 - 15 in the selected segment register SR. the The division of the segment registers SR is shown in FIG. 6; the content of the Validity bit position 13 (V) indicates whether the content of the block number is is valid. If it is invalid (i.e. V = 0) the content of the selected segment register is not used to generate a physical

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Address are used, and an addressing exception suspension then takes place. The identifier bit position 1-1 indicates whether the adrefjsierle block me can be read. Kalis bit 14 set to one is not allowed to be written in the relevant block, and only polling accesses are then permitted. Bit 15 is not used. The second word with bit positions 16 to 31 is reserved and is used it is also not used for the present exemplary embodiment.

B. Detectable main memory

Fig. IC shows the configuration of a data display system that a new type of expandable main memory for processing translated Has addresses. The main memory consists of at least one internal memory part 51, hereinafter referred to as internal memory for short, the has a storage capacity of up to 64 K bytes. The first possible extension is the addition of an outer memory part 52, in the following briefly called external memory, through which the memory can be expanded by 64 K bytes, so that the main memory is then 128 K bytes includes. An expandable asynchronous memory 53, also referred to below as an asynchronous memory for short, can then be added with which the capacity of the main memory to maximum

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te-

24
16,777 ¹ ZlO bytes (ie 2) can be expanded.

A translator 59 is provided for the AclrcG translation Interface equipment contains for the connection of the external storage; 52 and the asynchronous memory 53 with the main memory configuration.

A main processor bus 56A (with bus are collectors designated) connects a processor 54 and an I / O can 55 via a memory priority selection circuit 56 having the main memory configuration. The main memory bus 56A is also with the translator 59 and connected to the internal memory 51.

Internal memory cycle signal lines 54Λ connect the internal memory directly to the memory priority selection circuit 56. They transmit internal memory cycle signals (ISZ signals) which are 16 bits long represent translated physical addresses generated by the processor if he works in non-translation mode. When the processor is operating in reverse mode, ISZ becomes five higher value bits provided by the translator; they contain a Card selection signal (which selects a certain card from up to four

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Cards from which the internal memory can be viewed) as well as the fields CSY and CSX (which select a specific memory area on the selected card, these areas comprising Λ 96 bits). The five higher bits. '; on the Adres.sbuslei tunken 00-04 are transferred from the Uebersctzcr to the processor in order to. to be used by this during an internal storage cycle 1SZ. Bits 13-22 are output from the processor's memory address register to select a specific word location in the memory area, and the last bit 23 selects a specific byte in that word when it is a write operation. Byte addressing by means of the bit is only used for write operations, since read operations only address whole words (1 word contains 2 bytes). For a write operation, the last address bit 23 is set either to 0 or to 1 in order to address either the toad or the right byte in a word.

If the processor only works with the internal memory (i.e. if in the System no storage and no asynchronous storage is provided), then the processor only addresses the internal memory with physical 16-bit addresses; those from the memory address register on bus 5-1A be delivered directly. The rC'Bit output by the processor is long

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Addresses are just sufficient for addressing the IIöchstkn.pazit.it of the internal storage (i.e. 6-JK). With this minimal configuration with the 16.BiI], - in few physical addresses memory key connections accordingly uses the nonsense:; et ζ in the gsspei rather schul /.scha It ungen, which are shown in Fig. Jl.

The memory protection locks use the option of separate Determination of the address range, which is provided by the address key register sections for different memory allocations see s. the Combination of the active address switch with the Spcichersrhut ^ keys also included in this description illustrated invention. The feature of the AklivaddresskeyschaHungcn by welclic separate address range delimitations depending on the type of memory access are possible, can be combined separately, either with the use of memory keys when using non-relocatable addresses, or with the use of address keys, when using relocatable Addresses.

If you want the possibility of address shifting, which allows • that the main memory has exceeded the capacity limit of the internal memory

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It

from 64K up; been erwc.ilort may be, must be a pre-Ucbersctzcr riehen as cn in Fig. JC is shown. An external memory can then be added, which can be connected to the Uccrsctzer by means of signal lines, which enable the external memory cycle control (OSZ) shown in FIG. 9G is shown.

The translator enables an additional extension of the
Main memory over the cap xiiätsgrcnze of 128K, which for the
Internal storage and external storage are valid, in addition through Ii η / .uf (ization of an asynchronous storage unit. The asynchronous storage unit uses the
translated 24-bit addresses in a different way than the Ausscnspeicher, as shown in Fig. 9G for the asynchronous storage cycle (ASZ). Bit positions 0 to 6 are used in the ASZ asynchronous memory cycle, and at least one 1 bit is in these bit positions because more than 16 bits are needed to represent a number that is larger than 128K. By using the bit positions 0 to 6, the asynchronous storage cycle differs from the Ausscnspeicher cycle, in which these bit positions are not used; Only bits 7 to 23 are used in the download cycle. These special conditions for bit positions 0 through 6 are used to set a pair of look-ahead bits shown in FIG. 9G, with the associated

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Schaltunj ^ cii and processes in further details in the ZuKnmmciilian « will be described with Figs. 9A and 9B.

The translator has a connection to the main memory bus interface Via which it receives logical addresses including the Aktivadrens.schlür.sel from the processor for the translation. The Ucberselzer contains also .interfaces for the external memory and the asynchronous memory.

C. Address Range Vc rtcilune;

Fig. 2Λ shows the relationships between the different types of memory access, which are caused by different types of process sensor and channel commands, and the corresponding data address areas, used in the embodiment. In Fig. 2A, only a subset of the access types are used that are used in Fig. IB were shown. As shown in Fig. 2A, instruction fetch is carried out in instruction address area 60 using the ISS. Besides that two different types of operand access are shown in Fig. 2A, which are executed in the data address areas 61 and 62 using the contents of the key register sections OPIS and OP2S.

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Kig. 2A illustrates memory access which can be used in various ways Processor errors start before | jcnommeii wci'ilen. A memory save command calls data in the OPIS data area 61 or in the OPZS data area 62 and causes the results to be stored in the OPZS data address area 62. A command for direct memory operations fetches its data from ISS address range 60 and stores its results

in the OPZS data address area 62 or in a general register (AR). A register store command moves data from a general one Register 63 for OP2S data address area 62; a memory registers command fetches data from the OP2S data address area 62 and stores it in a general register 63. A branch instruction fetches a branch target folder also from ISS address area 60.

C. 2. I / O subchannel address area distribution

Two different types of I / O subchannel errors are shown in Figure 2A shown. One type of command is a direct program control I / O command called (DPS I / O) and causes an I / O operation that is synchronous runs with the main program, i.e. the main program is not running

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continue until the Ε / Λ operation is finished, whereby both the I / O-Bi: failed and the data from the OP ?. S address area 62 can be taken.

The other type of I / O command effects the normal type of asynchronous I / O operations, which are generally referred to as Cycle Stcal I / O (CS) operations. Be saved for this second type of command has the I / O-Pro "ramme itself (ie the Kanalbcfehle) in the" Key ~ O Kanalpropramni adrcssbereich "(> Λ (see Fig. 2Λ), while the data accesses that are performed for the channel program, are controlled by keys which are specified in i \ cn concerned Kanalbefchlen so that through each channel command (zD GSB) another of the Adrcssbercichc. that can be selected at 65 to 66 so that each I / O device has its own sub-channel program, in which the commands have the option of entering a different keyword in the address key register section of each subchannel, so that it is possible for each subchannel to access a different address range for each channel error can be moved as required.

Fig. 2B shows in somewhat greater detail the manner in which the I / O operatiom

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their address keys can glow to different addresses in the Uaupi memory.

Y / ic in Fi [J. 2) 1 shown, the I / O program contains an I / O operation command, egg triggers an I / O operation, and that's why! himself the I / O drive command in the ISS acess area. The OP code portion of the command indicates that it is an I / O operation command, and that R2-Fcld designates a register, the content of which corresponds to the address field must be combined to produce an address that is direct or indirectly an "Indirect Gerälestcucrblock" (IGSB) in the OP2S address area designated. If indirect addressing is used, the indirect address itself is in the OP2S address range. The IGSB address is either a direct or an indirect address, depending on the value of the I bit in the I / O control command. That is, the I / O operation command is in the ISS address range and the IGSB is in the OP2S address range stands.

There are two types of IGSB indirect device control blocks: (1) one CS type, or (2) a D PS type. The channel command field CMD in the IGSB indicates whether a CS operation or a DPS operation is being initiated.

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If the IGSB is a DPS type, its second word contains direct data, which have either been transmitted to or received from the addressed device, depending on whether the channel command field CMD indicates whether it is an I / O read or write operation.

If the CMD field Show daps the IGSD is of the CS type, this contains second V / ortjm IGSB the address of the sub-channel program for the device, which is addressed by the GA field in the IGSB. The first canal failed (i.e. channel control word), which device control block 0 (GSB-O) is called is located in the address part of the IGSB. A field in the GSlI-O, which is called the link address indicates the location of the next sub-link control word, which is called GSB-I, and which also contains a link address that locates the next GSB etc. until the last GSB is found.

• The entire channel program is located in this exemplary embodiment in the "Key address area".

However, each device control block GSB stops in its first word position

EA has a key field, which is the address key for data which the GSB concerned accesses. GSB-O contains e.g. a key field,

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which as the key i.'üi '~ --- j' - i.> e draws wild, and which the AdrcSH area for a contiguous block of logical addresses which begins at the data address contained in the J-'cld of CSJi-O which is located at the point F.A-lM. The key to GSK-O can have any key value. Similarly, the next control word GSB-I eiVien key for OSB-I, of any Can have a key value to define the address range for the data which are addressed within GSB-I. The key value in GSB-I can therefore be different from the key value in GSB-O etc.

It can be seen from this that the invention results in a very large Flexibility in the selection of the address range during the operation of I / O devices in the system results. When using memory protection keys Without translation, different key values can be used in the device control blocks GSB to create a special to get selective memory protection for the I / O data accesses.

If, moreover, the system is working in translation mode, all I / O data addresses are read by the translator for each access Translated (see Fig. ID) in the same way as the processor address

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to be translated.

3A shows circuit details for the control of the GSB key operations. Each Κ / O subchannel cnth / ill a small processor-like control unit for controlling the operation of a connected I / O device, which can be of any type. This internal processor control unit controls the processing of the GSB keys through the relevant I / O sub-channel. The GSB key is entered into a GSB key register 301 in the sub-channel control unit from the I / O data bus of the channel whenever a GSB device control block is ^{removed from the key:} 0 address area.

A plurality of subchannels are connected to a single channel in the usual manner. Each subchannel can communicate with its channel using protocol signals specially provided for this purpose. A subchannel requesting service by the channel is selected by a calling process. After the selection by the calling process, the channel data bus transfers control signals and data between the subchannel and the main memory. A signal which reaches the sub-channel ROS control 311 from the call selection control 310 causes a word from the read-only memory ROS 312 to be stored in

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a ROS-D.tlcnregi.sler 313 is entered in order to obtain the necessary Unlcrkanalopovationr.n zn control. One of the sub-channel opq rationcn is a GSB retrieval of the next address field in the current GSB from the address area with key · = 0. The GSB-Abruffekl in a ROS word is decrypted by a ROS decoder 314, which then outputs a GSB-Abiufsteucrsignal that the AND gates 315 (0) 315 (1) and

315 (2) activated, which requires an entry in the GSB key register 301 cause that is a part of the register stack that the whole device control block GSB receives. After the GSB request has been carried out, the GSB is stored in the sub-channel, the GSB request signal is terminated and a "No GSB request control signal activated, which: the AND gates

316 (0), 316 (1) and 316 (2) enables the GSB key from the CSB key register output so that it is available as a CS key for the GSB data access operations. The CS key is transmitted over the condition code bus to the channel in Fig. 3B. Of the Channel then transmits the CS key to the CS key bus, which is with the memory priority selection circuit in Fig. 3C.

C. 3. Memory priority selection circuit

In Fig. 3C it is shown that the CS key from the channel bus of a

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Channel selection circuit 331 is supplied, which is connected to the channel buses of connected to all channels connected to the processor, and which gives priority to a CS key from one of the channels.

With every un-channel control unit, there is also a plurality of control " lines, including a control bus and an I / O address bus. The I / O address bus transmits the data address derived from the GSB. The I / O control bus includes a CS request. ■ line indicating whether an address is on the I / O address bus (Fig. 3B).

The memory priority selection circuit 56 is with CS cycle request lines of each of the channels 1 ... P connected, which are connected to a processor. Through the circuit 332, respectively a certain CS key is selected and sent to the channel selection system 331 issued, which transmits the CS key of the selected sub-channel to the AAS selection circuits 333, which also Obtain the processor address keys from the processor ASR buses. Under the control of the memory priority cycle circuit 332, the select AAS selection circuits 333 each have one of the received address keys as the active address key AAS of the system. Figure 3D

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xcigl details of AAS option 333. D. Processor

Fig. 4 shows! Details of the parts essential for the description: of the Sy slejnprO7.cs.sor s, which, if necessary, tries to access the memory at the same time as the CS keys. The processor ASR buses (collective lines) are connected to the outputs of the address key register ASR. The memory priority cycle training 33 ?. (Fig. 3C), which can be of known type, determines the order in which the competing requests access is granted, ie the order in which the corresponding address keys as active address keys AAS at the outputs of the AAS selection sounds (Fig. 3D) appear.

4 shows those control devices in the processor which cooperate with the address key register ASR. The ASR is loaded from the processor data bus (data collection line) by means of the input control (EG), and the various address keys are output from the address key register to the processor data bus with the aid of the output control (AG). The EG and AG control signals are

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from the processor JlOS decoder) · released. The content of the address key register ASR is continuously transferred to the processor ASK bus, namely the TSS bus, the OPZS bus, the OPIS bus and the OBA-JUis, which with inputs of the ASS ~ selection circuit 333 (Fig. 3C) are connected, details of which are shown in Figure 3D. the AAS selection circuits choose between these three Processor license and at about the same time present CS keys and thus determine which of these keys is the active one Adrcssschltisscl AAS will. Fig. 7 shows the ASR control circuit in detail based on the input and output circuits for a single bit position ties ASR. All other bit positions of the ASR have the same Tax scarfs.

From Fig. 4 it can be seen that the processor ROS decoder (Fcstspeicher-Dekodicrer) has output lines, each of which goes through a specific ROS word when entered into ROS data register 406 is activated to input and output at the ASR register sections ISS, OPIS and OP2S to control or to other processor operations to cause.

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HO

D. 1 register for the last active address code AAS

The process shown in Fig. 4 also contains a register Uw for the last active address key, with the entry side of which an AAS gate terminal -107 is connected, which on the one hand is connected to c) cn AAS bus from Pig. 3D is connected and on the other hand to an inverter which is connected to a processor error flip-flop 401. The output of the AAS-gate 407 is input 408 FTIR dan last active Adrcssschlüsscl AAS in das'Register when a processor memory cycle signal (from FIG. 17) is present. The register 408 stores every active address key from the processor access key register ASR ₁ present on your AAS bus, provided that the error toggle circuit 401 does not indicate an error on an error message.

If, however, a machine error (MCK) or a program error (PCK) occurs in the processor, the error toggle circuit 401 is set. as As a result, the AAS gate circuit 407 is blocked because the Fehlercrsperrsignal falls, thereby retaining the last active address key of the processor (LKSA) which was present at the time the Error toggle 401 has been set. The machine error signal (MCK) and the program error signal (PCK) are

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address «sdecodien.:r 402 entered (except during a segment register cycle), in order to be forced into the ROS control circuit 403 enter a read-only memory address which causes a diagnostic program to be called up which eliminates the error condition either by repeatedly executing the faulty function until it is executed correctly, or by performing a close operation (log-out) if the error is found to be one Is a permanent error. The AAS Rcgister 408 in the meantime keeps the LKSA in order to maintain the last valid address range definition while error cancellation operations are running in the processor, so that after the error condition has been eliminated, the system runs under Retention of the last used address range definition can resume work.

One of the last diagnostic operations that are carried out before the status of a processor can be changed is the storage of the overall status of the processor in a Nivcau status block (NSB) in the main memory, which includes the content of the address key register ASR. A signal AG AASR (output from the register for the last active address key) sends the content of register 408 (LKSA) to the processor

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data bus output; a simultaneously occurring signal EG OPIS causes the LKSA to be entered in the OPIK regi atcrab.section of the ASR for the diagnosis or troubleshooting operations (see section II. 3). When the debugging operations are complete, the last normal ASR value is reloaded from the NSR into memory to resume normal operation.

D. 2 commands to load / save the ASR

8B and 8C show the commands for controlling the following two operations: (1) loading the address key into the ASR either from a word location in main memory or from a designated general-purpose register AR; (2). the storage of address keys by the ASR either in a word position in the main memory or in a designated general register AR. 8B shows the processes when the command “ASR / Speichercr Load / Save ¹ ” is executed.

8B shows the division of the 16-bit long command "ASR / memory

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Load / save ¹¹ . ICr is characterized by the 5-bit OP code and the 3-bit modificator in bit positions 13 to 15. The K field in Bil-Po: .i! Ions 5 to 7 addresses the part of the ASR (or the entire ASR) to be entered or output. The K values 0, 1, 2 or 3 designate the register sections ISS, QPZS, OP] S or the entire ASR ₁ for use by this command. A logical master address is generated with the aid of the RB field in bit positions 8 and 9, which designates a base register, and the access mode bits 10 and 11 (AM) which indicate whether a word is an appended field to an instruction which is a Contains address field, the contents of the AM-Foldes and the RB-Regislers are combined in order to generate the effective address of that word position in the main memory, which is either loaded or saved by the execution of this instruction. Bit X in bit position 12 indicates whether it is a load command or a save command. If XO, then the content of the addressed word position is stored in that ASR part which is identified by the K-FcId. If the X bit = 1, then the indicated AKR part is saved in the addressed word position.

Similarly, Figure 8C illustrates the execution of the instruction

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7 0 984 5 / ^ 8

"ASR / Regi fiter J-iaden / Abspei clic rn" represent operations carried out; the only difference to Fig. 8) 3 is that instead of a) main memory word: when this instruction is executed, a general register AR is used. Accordingly, in Fig. 8C the R-FcId in i \ rn bit positions 8 to 10 denotes a specific AUgemein-Rcgi stcr AR, which is used for loading or storing one or more keys in or from the designated part (or the designated parts) of the ASR is used.

The corresponding operations are carried out in the processor on the basis of signals on the output lines labeled EG or AG of the processor ROS decoder 405 (FIG. 6 ), which with the signals occurring on the data path of the processor are those described in connection with FIG. 8B Initiate operations.

E. Ucber put r

Figures 9A and 9B contain details of the translator shown in Figure IC 59, which the translation processes described with Fig. IA for address shifts. This address shift translation circuit can use the physical address range of

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Increase 61 K (^) bytes to 16 million (Z ) bytes, which corresponds to a trine expansion of the internal memory of 64 K bytes.

The address area of the main memory is enlarged by the IJebersctzcr insofar as it combines the active address key AAS and the 16-bit address from the processor or from a subchannel as a logical access address; and converts this input address into a 24-bit physical address that has access to the internal memory, external memory or asynchronous memory.

This mapping process enables the dynamic allocation of physical storage capacity to logical address areas and the sharing of physical storage capacity of several logical address areas. 8 sets (stacks) of 32 segment registers each (SR) are provided for the 8 different possible values of the address key, which results in a total of 256 segment registers. Everyone invited SR stack can be a complete mapping of a storage area containing up to 64K bytes in blocks of 2K bytes each. can be distributed. With a stack, too an address range is addressed that has less than 64K bytes,

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in-dem iiuiii only the validity bit position in one or more the Scgmontre gis-; ler sets on one, BO (l; eat only those Scgincntregisier, where the VnIidit; iLs- 13it - 0, the blocks with 2K each Bytes of capacity denote which belong to an addressable area which is identified by an assigned address key is.

A separate Scgincnlrcgisterslapel is provided for each address key, to enable quick switching of the logical address areas without the need for backup and Ulider Storage of the address book memory map of the system.

The address shift converter shown in FIGS. 9A and 9B enables the main memory to be expanded by an external memory of up to 64K bytes in increments of 16K bytes on each card, which are designated as the fifth through eighth cards for the readout memory . The internal memory consists of the first to fourth cards, each of which has a capacity of 16K bytes. Extensions of the storage capacity beyond the 128 K bytes of the internal and external storage require an additional asynchronous storage unit (FIG. IC), through which the physical

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Memory of lZfiKUytos up to a maximum of 16 million bytes can be enlarged.

The address area that was statically addressable by the machine said hello, which is available to all programs running at the same time

stands when all segment reg) ster with different physical blocks
addresses are loaded is 2 bytes. This limit is determined

by the 19 bit long kingang address, which is shown in Fig. 1Λ, and that arises when a 3-bit long active address key is sent to the 16-bit long address appearing in the program is appended to create a 19-bit long logical machine input address for the Generate translator. For a single program there is the option of addressing up to three different address ranges, which are defined by the three sections of the ASR, namely ISS, OPIS and OP2S, which means that an address range can be addressed of max. 64 K up to max. 192 K bytes results.

That means: for a physical main memory with a capacity between 512 K bytes and 16 million bytes result in an addressing option of only up to 512K bytes for a certain loaded content the Segmcntrcgislcr; this is called the largest static machine

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ad rc s sic. called rability. If you now have an addressing via the 512K ByIeB wants to add to the static maximum, so must one reload the Scgmcntrcgi r.ter clurcli programs in order to have an addressability other <: r areas in main memory.

The static addressability can easily be increased by the addition of further bits to the address key in the ASR and through the enlargement of the associated circuits, thereby creating a corresponding to support a larger number of fragment register stacks.

If a converter is built into the system as shown in Fig. 1A is shown, its use is indicated by bit number 14 in the processor status word (PSW) controlled by output lines of the processor ROS decoder in FIG. 4 when that shown in FIG. 13A is present Enable / disable command. Bit 14 in the enable / disable command indicates whether or not an interpreter is provided in the system, and bit 7 indicates whether it should be enabled or disabled. The one shown in FIG Circuit determines whether the converter is released or not. if the translator is not enabled, and when the SP bit is set to 1 in the instruction shown in FIG. 13A, it becomes that shown in FIG Circuit used for memory protection when not translated. If

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Accessibility is only required in a small address area and if fast processing is desired, the translator can be blocked.

FIG. 9A and 9 D show in detail the circuits and bus lines SchnittstellenlciHingen for Uebersetzcr 59 of the system of Figure ₁ IC gemüsr "the following list.:

E. 1 interface processor / translator

(1) Memory address bus 901. It has 15 lines representing the logical Program address from the memory address register (SAR) of the processor; transferred to the translator. After the address translation will be the five most significant bits of the translation address are sent back to the processor in order, if necessary, to address the Internal storage 51 to be used. The 10 least significant bits (D field) do not need to be translated.

(2) Memory data bus 902 to memory .. It contains 16 data lines and two parity lines. It transfers memory data and segment register contents from the processor to the converter.

BC9-76-012 7η ο

(3) memory data bur; 903 from memory. It contains 16 data lines and two parity lines. He transfers the content of the scgmcnl rc |; i st he (SU) κ to the processor.

(4) Bus for active address key (AAS bus). These three lines transformers select the active Adro.s key AAS i) cr memory priority sauswahlschaltung (Fig. 3C) for "translator, uiti a bestimrnten Scgmentrcgislcrstapel in Ucbersetzer.

(5) Memory write OP 0. Single line from the processor, which signals to the translator that a write operation in the memory to be performed on the left byte of the word currently on the memory data bus to memory. This line is activated when the lowest bit number 23 of the 24-bit physical address is 0.

(6) Write memory OP 1. Single line from the processor, which signals to the translator that a write operation is in the memory is to be carried out with the right byte of the word that is on the memory data bus to the memory. This line will activated when the lowest bit number 23 of the 24-bit physical address is equal to 1.

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(7) Transfer. Single line, which is a processor .signal to the Uebersel / .cr that the UeberKelzer for his Function releases. This signal is activated by the enable / disable command.

(8) Memory request to Uebersctzor. Transfer this individual line a processor signal which requests the translator, translate the logical address from the memory address bus. A Microcycle (220 nanoseconds) is automatically skipped, to give the Uebersctzcr access to the relevant segment register to enable to determine the physical address and to determine whether an access to the internal memory, Ausscnspoieher or to asynchronous storage is required.

(9) Timer pulses A, B, C, D. These four lines carry processor timer pulses of 55 nanoseconds in duration, which establish synchronism between the processor and the translator.

(10) Transmit Uebcrselzer / SAR. The signal on this line is there indicates that the translator uses the five most significant bits of the

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set physi see memory address 55 nanoseconds after the start of this signal on the memory address bus. It causes the processor to forward bits 00-0-1 of the translated address from the address bus to the internal memory.

(11) Internal storage cycle (ISZ). This line transmits a from the Ueber-Kctzcr generated signal, which asks the processor, your interior pcicher 51 to provide a memory bit signal with each new physical address. If an outside storage or asynchronous storage cycle (OSZ or ASZ) is to be executed, this line is deactivated so that the internal memory is not selected.

(12) Translation memory occupied. This line transmits one of the

setter generated signal which indicates to the processor that he stop the clock signals. This line is only activated when the asynchronous storage unit 53 is accessed has received a corresponding response from the asynchronous storage unit 53, this line is deactivated and the clock signals are restored started to end the storage cycle. This shutdown of the storage clock signals by an asynchronous storage unit is the reason for their asynchronous mode of operation and the reason that their access

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handle cycle is longer than the access cycle for the internal storage or external storage 52. ■

(13) Built-in translator. This line transmits a dated. Translator generated signal which indicates to the processor that a translator 59 is installed in the system.

(14) Translator invalid memory address. This line transmits a Signal generated by the translator, which indicates to the processor that the logical address just transmitted to the translator is invalid; a program display (PCK) then appears.

(15) Translator memory protection display. This line transmits a Signal generated by the translator, which indicates to the processor that an attempt has been made to access a block in the memory write, in whose segment register bit 14 is set to 1, thereby indicating that read only operations for this block allowed are. .

(16) Monitoring program status or Cycle-Stcal cycle. These

Line transmits a signal generated by the processor to the

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Üebersctzcr, which indicates that this read-only bit 14 in the should ignore the addressed suction register because the present Memory access requirement either from the monitoring program or comes from a universal I / O channel.

(17) End of cycle. This line transmits a generated by the processor Signal which indicates to the translator that the storage cycle is now is terminated.

(18) Segment register cycle. This line transmits a from the processor

generated signal which indicates to the translator that the segment registers are activated. At the same time, the write memory OP 0 or write memory OP 1 lines are used to indicate whether the cycle is a read or write cycle as part of a "save segment register ¹ or" load segment register "command.

JS. 2 Translator / Ausscnspeicher interface

The interface from the translator to the external memory is shown in Fig. 9B. The following lines belong to it:

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(1) Card selection guide. These four lines, which are labeled with card selection 8OK, 96K, 112K and 128K, choose one memory each: h (* r card of 16K bytes in »store external number.

(2)!. Lines TCSX and TCSY. These six lines transmit X coordinates and Y coordinates for the selected map to select a particular area on that map.

(3) Lines "byte 0 write" and "byte 1 write". These four Lines carry timing signals to the four storage cards to write a byte.

If the Uebcrse.tzer the physical memory address of the corresponding Segment register receives, it determines whether an access to the internal memory, the external memory or the asynchronous memory has to be made; it only activates the interface lines to the external storage unit if a Storage cycle is required. The cable bridges, which are in of the external storage control (Fig. 9B), indicate which of the four cards of the external storage control are installed.

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271770Q

K. 3 Interface via sotzer / Asynchvoniipei ehe r

The interface from the Uebersctzcr to the Asynehron memory (3 · ^ j j ;. 9Λ and 9B) includes the following lines:

(1) Asynchronous storage output data / parity. These 16 data lines and two parity lines form the memory data bus to the asynchronous memory purity.

(2) Asynchronous memory input data / parity. These 16 data lines and two Parjlätslinien form the memory data bus from the asynchronous memory unit to the processor and to the channel.

(3) Asynchronous memory lower SAR off. These 13 lines transmit the 13 most significant bits of the physical address that make up the block address in the asynchronous storage unit. They form the top SAR bits 0-12 shown in the asynchronous memory cycle in Figure 9G.

(4) Asynchronous storage upper SAR off. These ten lines transmit the 10 lower bits 13-22 in the asynchronous memory cycle, but

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not bit 23 of the asynchronous memory cycle (Fig. 9G). Bits 13 to ? .Z address a word in the selected block.

(5) Byte 0 write. This line carries the lowest bit no.? .3 the physical address to indicate whether the left byte of the addressed word will be used for a Memory operation is used.

(6) Byte 1 write. This line informs the asynchronous memory, that the right byte of the currently addressed word is subject to a memory operation during the asynchronous memory cycle.

(7) Asynchronous memory selection. This line shows the addressed Memory module indicates that a memory cycle is to be started. This selection line is only activated during an asynchronous storage cycle, and if no logical command address and no memory protection indicator have been detected by the translator.

(8) Interface cycle and interface cycle 90. These two clock signals c have a period of 440 nanoseconds with a pulse duration of 50% per period. The two clock signals have a phase shift

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Shift of 90 against each other; they are only active when that Asynehron memory selection signal is also active. These clock signals can be used in the asynchronous memory function for the following: Synchronization within the storage unit, avoidance of problems with re-entry, saving of data in Flip-flops, and for generating response signals at the specified times.

(9) Reply. A signal from the asynchronous appears on this line Storage unit, if the addressed storage space is installed.

(10) Writing signal. This line to the selected asynchronous storage Before the rmodul is activated during the second half of the write cycle after the translator had received a response. The write indication signal is only activated if the selection is also activated.

. (H) Normal asynchronous memory cycle end. A timing pulse is emitted on this line when the response line receives a signal from the asynchronous memory. It is used by the selected asynchronous. memory unit used as a confirmation signal to reset the

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To achieve flip-flops that were set during the cycle, and to clic re-selection during the same cycle at To prevent falling of the asynchronous memory selection signal.

K ^ Λ Sc Kmentrofii stcrauswnhl

Details of the segment register control circuits are shown in Figure 9C. A segment register is selected by a concentration method. First of all, the required storage capacity is set in all register steps selected by addressing all registers with the higher-order ones Bilstelleii 0-4 of the logical address appearing in the program, so that the content of the selected register is output from each stack v.'ird. Then, with the help of the AAS-BiIs, a selection is made among the stacks made, whereby one of the eight preselected registers is finally selected by this selection. This is achieved by first using the The value of XAS bit 2 is used to first select four of the preselected segment registers for restriction, either from the even or odd stacks. Those acted upon by AAS bit 1 Lines with the signal real (T) and complement (C) become then used to select only one of the two groups of stack output signals, either stacks 0, 1 and 4, 5 or the

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Stacks 2,3 and 6,7. (Here dar means comma between <len stacking nines "or"). Kn so the output signals are used a pair of registers, either by the stacks 0,1 and -1, f>, AAS-1 wcitn bit is at 0, or from stacks 2, 3 and 6.7 when because »AAS bit 1 is in state 1. From the selected pair, an individual register is ultimately selected on the basis of the state of the SR-IIoch-Nicdrig selection bit (AAS bit 0), which is fed to the concentrator 921 in FIG meets a preselected pair of stacks and finally only outputs the output values from a single register from a selected stack.

K. 5 Control for loading / saving the segment register

Fig. 8A shows the operations of the load and save instructions the segment register (SR). Fig. 17 shows the processor memory control, and FIGS. 9A and 9B show the associated translator controls which; required to execute these commands.

Li Fig. 8A is shown how the command "SR Load" the input of a physical block address in a selected segment register of a addressed word storage location in main memory controls. The command

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¹¹ SK Storing "causes the content of a selected segment register to be copied into an addressed word memory location in the main memory.

The format of the 16-bit commands for loading and saving tier Segrncntregisler is determined by a 5-bit long OP code and a 3-bit long; Modification field, which in the bit positions 0 to 4 ~ or. 13 hi s 15 stand.

Bit X in bit position 12 of the SR command indicates whether it is a load or a store operation is involved. When X is set to 0, the content of the addressed word memory is in main memory loaded into the selected segment register. If the X bit is set to 1, then the content of the selected segment register stored in the addressed word memory location.

The R field in bit positions 5 to 7 addresses a general register " (AR), which contains the address of the selected segment register which is to be loaded or whose content is to be saved. In the general tab the key clfcld in bit positions 5 to 7 is a Batch number that identifies the selected batch and the AR bit

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Positions 0 to · 1 contain a Scgmciitrogislenniinmrr, which: this Selected segment register identifies which one is loaded or unloaded from your should be saved.

The desired word storage location in the main memory is addressed with the aid of a logical address which is generated using the. RB field in bit positions 8 and 9, which specify a base regi sler; the AM field in bit positions 10 and Jl (access type) indicates whether an access type word follows the instruction. The content of the access type word (AM-V / ort) and the RB register are combined, urn to generate the effective address of the main spcichorwortstcllc (ie that appears in the program) which is to be loaded by executing the instructions or to be saved from the. If the system is operating in the operating mode, the generated effective address is entered in the transcript (FIGS. 9A and 9B) together with the active address key AAS in order to form a logical communication address. The translator issues a 24-bit physical address with which access to the addressed word memory location is possible. It is thus possible that the previous content of the segment register that is to be loaded is used in a translation operation before this content is transferred to another through the segment register loader

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physical block press is prevented.

W (. 'In the processor not in translation mode, the generated effective address the physical address in main memory.

Bits 13 and 14 of the addressed workspace in the main memory contain the values for the validity bit V and the read-only hit K _1, which are to be loaded into the segment register in order to control its effect when it is used for a requested translation.

Fig. 17 shows the controls of the processor in use when executing the liefflile is used to load or save the segment register will. These control circuits in the processor generate a Scgmcnlregisterzyklussignal, which is used by the translator (Figs. 9A and 9B) to effect loading or storage of a segment register. By means of an instruction for loading or saving a segment register, microinstructions are called up in the processor which have a signal "Request to load / save a segment register "generate, and thereafter a signal for a processor request for a memory cycle. The first signal sets a toggle 481 "SR request follows" (Fig. I7), and the second signal goes to an AND gate 482, which

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is enabled by the T output of flip-flop 481. When the output signal of the AND gate 482 is active, an SR phase toggle circuit (J- ³ JI) is set for one cycle; the output signal of which activates the AND gate 48-1 when the translator is installed. The output of AND gate 484 sets a toggle 486 "SR request ¹ " to indicate that access to a segment register is required. The T output of toggle 486 enables AND gate 488 to provide an SR Generate cycle signal provided that there is no CS cycle request, since CS cycles have the highest priority, the SR cycle has the second highest priority, and a normal processor memory cycle has the lowest priority; this is effected by an AND gate 493 , which generates a processor storage cycle signal on line 494 only when there is no SR request signal from the C output of the trigger circuit 486. The other input of the AND gate 493 is connected to the T output of the processor cycle trigger circuit The T output of a multivibrator gives the real or true output signal, while the C output gives the complementary signal).

If during the execution of a load or save command of a segment register the AND gate 488 by the T output signal

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of flip-flop 486 is enabled, its other input receives that T output from processor cycle tumble 490, which is always it is then iikl.i fourth if a memory is called from the processor before the cycle is present. The flip-flop 490 is activated by an output of the AND gate 491 set; one input of which receives the "no CS cycle" signal for release (which occurs when there is no I / O memory access request present). The other input of the AND gate 491 receives the T output signal (true output signal) of the release Prozcs.sorspeichcran request toggle switch 49? · Which is always set when there is a processor request for a memory cycle.

A while there is a pulse trigger register cycle signal on line 923, will the segment register to be selected from the current address in the processor pcichcr address register SAR addressed. A selection operation is then performed for the segment register in the same way as it was explained in the description of the converter in the section "Selection of segment registers".

As mentioned earlier, the binary value of the X bit in the instruction determines whether a load or store operation is performed; for this purpose, the X bit selects a load or store microroutinc from the processor

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ieststore ROS. For a segment register loading operation, the micro-rotation calculates: first of all, it is a razocssoj- sjjcii'lHiranfordcning ; Word addressed by <\ cn SR- I'. fetched from the] run memory <: n vuid is entered into the l'rozcssorspeicherdatenregiKlcr SDR. The microroutine then outputs the request signal for. Loading / saving of the segment register, which is followed by a further processor request for a memory cycle. This causes the circuit in FIG. 17 to generate an SR cycle in the manner described above which selects the segment register and causes the contents of the memory data register SDR to be transferred to the selected segment register.

The "Save segment register" command is similar, but with reverse sequence of the microroutine., so that the circuit in Fig. 17 is caused to generate an SR cycle while the Segment register is selected and its content is transferred to the SDR memory data register. Then the micro-routine does a normal one Processor memory request which causes the content of the SDR to be transferred to the addressed memory stcllc in the main memory.

_K. 6 Stenciling for preliminary drafts

If at the address block, the block address part of the physical Address generated from hits 0-4 of the logical address is used for

709845/0874

Access for: Selection and reading of a segment register SR ProzesKortcikl cycle required. In further processes so rtaktzyklu s vunh · required for access (if the look-ahead circuits are not provided were J to decode the excluded block address to the interface bus ? .u to select the required storage unit, i.e. for Internal memory, external memory or asynchronous memory to which the physical block address must be transferred. When a Anticipatory sounding is provided, there is no need for an additional line to select the required interface bus, and you need the one that has been read out Not to decode block addresses in order to determine the required storage unit. This means that the access time is shortened by one processor clock cycle when the system is translated. During the translation process, the D bits in positions 5 to 15 of the logical address are always on the main memory bus from Processor memory address register SAR. No additional conversion time is therefore required for the D bits; they will be at the same time all three storage units delivered.

For the anticipatory sound, in each segment regulator (SR) in two bit positions are provided for each of the eight stacks (FIG. 9A), which are used as. Look ahead bits are designated. The division of the segment registers shows

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BADOBlGtNAt

Fig. 6. The two look ahead bits are generated and placed in the segment register used when the block number is processed by the process or memory control is inserted into the segment register; this control, which carries out the operations shown in FIG. 8A, is shown in FIG. the Before griffsbi t?; indicate whether the internal storage, the external storage or the asynchronous memory contains the block which corresponds to the block number in the SR. When the look ahead bits are set and the segment registers are loaded, the look-ahead bits are used with each memory access with translation to determine and select the required storage unit in parallel with the circuitry To execute the logical input address. The block number, but not the look-ahead bits, can be done by a program read that uses an SR memory command.

The look ahead bits are encoded in the manner shown in Figure 9G. That The left look-ahead bit is set to 1 if the associated block is in the inncnspcichcr. If the left bit is set to 0, the associated bit is available Block either in external storage or in asynchronous storage. The value of the right look ahead bit indicates whether the external memory or the asynchronous memory holds the block. If the right bit is equal to 0, the block is in the asynchronous storage unit.

7098A5 / 0874

BC9-76-012 -67-

The anticipation bits are only used by the circuits: and are for not visible to the programmer or the system user. They are only used to speed up memory access and are not Part of the Ul her settlement operation.

The circuitry for setting the look ahead bits is shown in Figure 9C. These include decoders 901 A and 902A, both of which are the higher order ones Part of the assigned block number is supplied, which is loaded into a segment register when executing a Segmcntrcgistcrbcfchls' as described in connection with Fig. 8A. The selected segment register is in one of the stacks Obis 7 (Figure 9C). The block number is issued by the "Load segment register" command, which contains the block number assigned by the program from the Memory location in main memory which is addressed by the command, "after which the block number in the memory data register SDR (Fig. 4) is used. The processor then puts the assigned block number from the SDR onto the processor data bus (Fig. 3C) which is connected to the memory data bus to the memory (Fig. 9A) is connected, via which the data are transmitted, which in an addressed segment register in a batches 0 to 7 are to be loaded. The Segmentrcgistcrladcweg is in Fig. 9C is shown in detail; the signals on the SR input lines

.7098A5 / 0874

3C9 --- 012 -63-

00-07 are used to generate the prefix bits. The lines 00 to 06 are connected to the input of the O decoder 902Λ, and the lines 00 to 07 are connected to the input of the O decoder rc rr; 901Λ connected. Each of the O decoders gives one: 1 al ;; Pre-attack signal from when all zeros are present at its inputs, and results in a 0 signal at the output when any of the inputs is equal to 1. If the decoder 901A detects all zeros in the bit positions 00 to 07, it transfers a 1 bit to the left: look-ahead bit position of the addressed segment register in the stacks; but if any of the input bits 0 through 7 is a 1, then the left look-ahead bit is set to zero. The decoder 90lAzcigl indicates whether the physical block whose address is being loaded is in internal memory or not; it depends on this whether an ISZ signal has to be generated.

When the decoder 902 A has all zeros in the SR input bit positions 0 to 6, then the right bit of the addressed segment register is set to 0. The reason for this is that if the left look-ahead bit indicates that the internal storage unit is not the affected storage unit and if bits 0 to 6 are all zero, then the Decoder 90EA indicates whether or not there is a 1-bit in bit position 7 of the physical address ^ being loaded; this ultimately indicates

BC9-76-012 70SL & A5 / 08 74

whether the referring block is in the external memory or in the asynchronous memory.

With every segment logistcr that is loaded, the look-ahead ubits set so that they indicate the storage unit which contains the assigned block. The SR load operation occurs during a SR cycle appearing on line 923 in concentrator 922 (Fig. 9A) from the Basic controls are displayed, which are shown in detail in Figs. 9D-Z is.

The slave address is input to the concentrator 922 through lines 05 through 07 of the memory address bus 901 (FIG. 9A). The segment register address is transferred from lines 00 through 04 of memory address bus 901 through the PH register to segment register stacks 0-7 (FIG. 9A). These address signals arrive on lines 00-07 of memory address bus 901 (see FIG. 3C) from memory address register SAR (FIG. 4) via the processor address bus. The content of the SAR comes from the general register, which was selected by the command "Load segment register" (FIG. 8A), from which general register bits 0-7 are the SR address bits on lines 00 to 07 of the Bus 901 are. (The general register AR is in level stack 431 (Fig. 4)

709845/0874

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selected by a level stack address given by the All field in the command "Load segment register" was derived).

The Concentrator 92 ?. the stack address then outputs the selected segment register on its following output lines: AS-Iiit 2, AAS-Ri ₁ I 1, and "SR high-low selection" (line 935). Line 935 provides an input to the basic controller in Figure 9B. These circuits are shown in detail in Fig. 9D-2; they generate the signals for the lines 932 and 933 which are connected to the Segmentregisterstapcln 0-7 to indicate the niederwertigcn Stapeladressbits, and true and complementary form corresponding uer] signal on line 07 of the memory address bus 901. The signals on line AAS Bit 1 correspond to the true and the complementary form of the signals on bus line 06; and the signal on line AAS bit 2 corresponds to the signal on bus line 05.

When a memory is accessed in translation mode, a stack register selected by the same type of concentration operation as described in the section "Segment Register Selection". From the The segment registers selected by the concentrator are read out at the same time as the other 16 bits. For the

709 8 * 4 5/0874

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Look ahead bit a separator concentrator 931 is used because it works faster than the further concentrator 921, which the block address bits selects for the corresponding segment register. At the output of the K0n7.cntrator 931 one of three output lines is activated at a time to generate the specified storage cycle, namely either ISZ, OSZ or ASZ, For the processor, the ISZ signal lines 54A from the processor are made internal memory through memory priority selection circuit 56 purity 51 (Fig. IC) used. Since the lines 54Λ on each pail exist, whether the system has a translator or not, the internal memory cycle control from the concentrator 931 with the Processor connected to cine ISZ. To initiate addressicropcration. The lines for the Ausscnspcicher cycle and the asynchronous memory cycle lead to FIGS. 9E and 9F-1 in order to enable the address selection in the to initiate the units concerned.

F. Operand range comparison

A specially provided facility is the operand area comparison (ODA). If this condition is set in the address key register ASR there is a special address status in which all operand calls are forced to take place in the O P2 S address area, • while the address range specified by the OPIS address key

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although the key is in the OPIS register section of the address key register ASR is not changed.

The OBA state of the system is brought about by the in Fig. 13Λ enable command shown if its OJiA bit 13 is set to 1 '/. t. if this bcfelil is executed causes the networked OBA bit that; the OBA register section is loaded accordingly in the relevant ASR by input from the processor ROS decoder (Fig. 4). It won't the key in the ASR changed when the OBA state is activated. However, the address range specified in the OPIiJ section is not accessed is defined as long as the OBA status is active in the ASR. The OBA facility is implemented by the circuit shown in Fig. 3D, in which an activation of the OBA-L citations from ASR is compulsory requires that the AAS output delivers the OPZS key every time if an access request is made when an instruction is executed in the processor is available either for an OP1 operand or an OP2 operand.

If the OBA state is ended by executing a lock command, whose OBA bit 13 is set to zero, the key becomes the value in the OPIS register section put back into use, and every OPl-

BC9-76-012 -73-

^ 09845/0874

Ope ran d c na nf or dc tion output.

G. Adresühbereichslu-stiinniung diircli ScIiIii.i; seleinirabo in the ASR

When the OBA facility is locked, the three Adrcssscliliissul The following function in the ASR address key register:

Each address key loaded into the ASR defines an address range, which can be accessed. Each address range is logically connected Memory area that can be accessed by the effective logical address without the aid of any programmed management function for the distribution of the existing Middle. Each logical address area contains up to 64K bytes. All call-offs take place in the address range defined by the ISS. All read operations that concern a data operand 1 (such as is defined in the memory command), take place in the address area defined by the OPIS is defined. (Due to the construction there are no write operations intended for operands 1). All writing and reading operations that relate to a data operand 2 (such as

provided when drafting the command structure), in the address book

t. ■

which is defined by the OP2 S.

709845/0874

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If, for example, ISS = - OPlS- OPZS, all memory: r accesses are made to the same logical address range with a capacity of 6-1K bytes. If ISS is not equal to OPl, but if OPlS π OPZS, then the instruction calls take place in the JSS-Adrc-ssbeveich and the data access takes place in the OPZ-Adrcssbcreich. If ISS / OPIS / OPZS, then the command is called in the ISS address area, every call of an operand 1 in the OPIS address area, and every call or every storage of an operand Z in the OPZS address area, with the 3 address areas different from each other child. The Dalen flow for a class of information in which three different address ranges are used is shown in FIG . The key values in the ASR can only be set if the processor is working in the monitoring program, ie if the commands for loading the ASR are privileged.

H. Loading the ASR in the event of an interruption

If there is an interruption in the processor, address keys for address ranges that may be required by the programs handling the interruption are entered into the ASR in preparation. There are a number of different types of interrupts in the system, each with its own specific programming support, the

BC9-76-012 -75-

709845/0874

again requires the whine of certain address keys. The processor interrupts include: interruptions to the monitoring program on call, I / O device interrupts, machine errors; r- / j ³ ro {; rani n · error bridges, program protocol interruptions, control panel interruptions and interruptions in the event of thermal siphon load. These processor interrupts are sometimes called class interrupts.

It is assumed that all interrupt routines are in the address range with key = 0. Therefore it has to be in the ISS section a 0 can be loaded if an interrupt occurs. Since the operand data which are used to handle a specific interrupt are required, can be accommodated in a different address area, the belonging to the special interruption data can Address key can be loaded into the OPIS register section. An OPl key is input when a class interrupt occurs (i.e. input of an input signal to the compulsory address circuit 402 in Fig. 4), namely to prepare the implementation of a memory-storage transfer operation from the interrupting address area (i.e. OPIS-Bcrcich) to the OP2S address area with key = 0. If a class break occurs, e.g. a level status block NSB in the OP2S

BC9-76-012

! Area saved, which key has - 0 (i.e. OP2S --- 0), where Dale ·, η VO) Ii OPlS report are called up. The content of the ASR is also entered in the NSB with a command /. to store the ASR.

Other states in which all: Schlünsclwertc; in ASR - 0 are set: Syr.tcm resetting and initial program loading, during which the OPA device, the overclzer, and the memory protection device are all blocked.

H, 1 interruption with monitoring, program call (SVC-Unlcrbn-chuni

For the SVC interruption operations discussed below, it is assumed that the monitoring programs are accommodated in the address area with key - 0 and that the user program is in a different address area, ie with key / 0. It is also assumed that an exchange of data between the user and the monitoring program is necessary. The data must be fetched from the address area of the user into the address area of the monitoring program and must later be transferred back to the user's Adrer.sbcrcich.

BC9-76-012

13B shows the load operations for the ASR in the event of an SVC interruption. Ks is assumed that initially in Use! ^ - each of the three user keys had the value ?. and that the. ΟΓ · Λ field = 0 is set. When a monitoring program: call command (SVC-13cfell 1) is executed in the processor of FIG. 4, the forced address circuit causes a sequence of ROS words to be called up and executed, whereby the processor is brought into the monitoring country. A level value block NSB is also stored, the content of OPZS is output to the content of OPIS, so that the address range. which contains the data that were involved in the generation of the interruption, becomes addressable. The zero output line (AG 0) from the processor -ROS decoder is activated and values are entered into the OP2S and ISS positions of the ASR via the processor data path.

Data is transferred from the user area to the monitoring program area Transmitted, and then the release command (Fig. 13A) with a 1 executed in bit position 13 to produce OBA state 4, which is shown in FIG. 13B is shown to bring about. This has the effect that all memory accesses in the address area take place with key 0 during the monitoring program is executed in the OBA state, whereby the possibility of access to the O PI address area is not lost.

BC9-76-012

If the monitoring program wants to transfer information to the OPIS area, the processor issues a lock command which resets the content of the OBA section in the ASR; this causes a return to the OPI-A <lres. ^c ; area. Then state 6 of FIG. 1315 is brought about by exchanging the fields OPIS and OP2S so that the monitoring program is given an addressing option for storing in the OPIS area. The monitoring program can then transfer the data from the monitoring program to the user area. Then the ASR is brought back to user country 7 (Fig. J3B) by loading the original contents of the ASR from the level status block NSB.

Fig. 18 shows the operations performed when an SVC instruction is issued. These operations include saving the old one

Contents of the ASR and loading of new content into the ASR accordingly of the following overview, whereby the section numbers of the overview and the circled numbers on the data paths in FIG. 18 correspond to one another. The execution of the SVC instruction in the processor happens in the following way:

(1) At the beginning of the execution of the SVC command, the content of the ASR

7 L! 9 04 5/00 74

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issued to the Arbeits sbercichregisler (ABR), namely About the processor data path by activating the signal ACl AS] I and of the signal KG ABU from the ROS decoder. This operation will indicated by the transfer of the ASR content into the register TEMPA in Fig. 18; it is believed that OPIS, OP2S and ISS have been set to the value 3.

(2) Output OP2S and input OPlS.

(3) Set OP2S - LSS - 0.

(4) The content of the level status register (NSR) is saved in the tempora rrcgisler (TEMPB ¹ ).

(5) In register NSR ¹ , the bit ii for the monitoring status is set, the bit for the sum mask is reset, and the protocol bit is also reset.

(6) The content of the BAR (instruction address register) is then increased by two units so that the next memory stcllc is now addressed where the beginning of the data or a pointer to the data is located.

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(7) When the processor detects the SVO state, the content the memory location 0010 in the address area with key - 0. This area contains an address (i.e. a Z ^ ciger) to a level memory block (i.e. NSP)), • which: r in turn also in the address area with key "0 is located.

(8) The NSB pointer in position 0010 is stored in the memory address registe r SAR (Fig. 4) transmitted.

(9) The contents of BAR, TEMPA, TEMPB, as well as the AUgemcin register 0-7 (NSB).

(10) The SVC number (indicating the type of SVC command identified) is copied from the SVC command in address area 1 into register Rl.

(11) The content of memory location 0012 is transferred to the BAR.

(12) The execution of the monitoring program now begins

routine, which starts at the memory location with address 0012.

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This is the routine called by SVC number 2.

At the beginning of the SVC routine, the ASR has the following Iiihali:

OPlS OP2S ISS

OP2S ¹ 0 0 (Note: OP2S ¹ is the

previous content of OP2S).

In the other class breaks, similar arias are used by Operations carried out to a certain state of charge of the ASR as shown below:

H. 2 G e erätebedingt Unterbrec hung

(1) Reset protocol, block OBA, and monitoring states $ et.

(2) Set ISS = OPlS = OP2S = 0.

(3) Insert the address of a device data block in register 1.

(4) The interrupt identification (ID) used by the interrupting

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Enter the K / O device in register 7.

The resulting content of the ASR is:
OPlS OPZS ISS

JI. 3 Interruption in the event of machine error and program error

(1) Reset protocol, block total mask, block OBA, and set monitoring status. Save the NSB in the address area with key - 0.

(2) Set ISS = OP2S - 0 .

(3) Save the LKSA in the OPlS.

(4) Save the content of the SAR in register 7 (except for the protocol bit).

The following content of the ASR results: OPlS OP2S ISS IjKSA 0 0 (Note: LKSA is the last in the

Register 408 in Fig. 4 stored keys when interrupt occurred).

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II. 4 Interruption from the control panel /

Untcrlircflninp, with thermal üc-hori: i st

U.N

(1) Reset protocol, lock control mask, lock OBA, and Ucbcrwarlnmoszusländi: put.

(2) Save NSB using the address key s

(3) Set ISS ^ OPlS ~ OPZS = 0.

The ASR is in the following state:

OPLS OP ?. S ISS

0 0 0

H. 5 Pi-ot okollauf zcirhn- interruption

(1) Reset protocol, block total mask, block OBA, and set Uc monitoring states. Save NSB in the address area with key =

(2) ISS transferred to OPIS.

BC9-76-012 -34- -

709 8-4 5/087;

(3) Set OP2S = ISS = - O.

the following content of the ASR results:

OPlS OP2S ISS

ISS ¹ 0 0 (Note: ISS ¹ corresponds to dorn y.ur

Time of interruption present JSS).

2. Circuits for memory protection without translator

The memory protection circuit shown in Fig. 11 for over settlement-free Addressing (UFA memory protection circuits) are used when the Address shift translator shown in Figs. 9A and 9B either not released or not installed in the system. The invention enables upward compatibility between a system with Uebcr-Hetzer and address key memory protection on the one hand and a system without translator with memory protection on the other hand. That means: programs and data used in a system associated with the UFA memory protection facility works, can without change in an. location that has an address shift translator. These Possibility to switch between two types of memory protection circuits is important for system users who have a relatively small spoke-1

709845/0874

r.C? "" -012 -85-Γ.

system that is inexpensive, and who want to start their memory want to expand later for a greener system.

When the address shift control is released, and the UFA storage school circuit is also enabled, the address shift is nu.be rs <jtz; cr blocked. The state of the UFA storage school facilities is controlled by the enable / lock command, which is in 13A is shown.

The UFA memory protection circuits make it possible to prevent undesired Access to a main storage location, be it through a Processor command or an I / O command that uses an untranslated address. Mild UFA storage devices become the main storage divided into blocks with a capacity of 2048 bytes each. For each block of main memory, there is a memory key register in one Regisler stack 501 (Fig. 11) is provided. Each register is a specific one Allocated block in internal memory, which is selected by the five most significant bits in a 16-bit physical address This is the address appearing in the program that is generated directly by a program that runs in the system. at Use of the UFA memory protection device are included in the program

BC9-76-01 2 -86-

appearing addresses the physical addresses; but if the translator is released, the address appearing in the program is part of the logical input address. Each register has at least three bit positions for an assigned memory key and a read-only bit R; it can also have a validity profile V (not shown). The bit positions are 0, 1 and ? For the three-bit storage keys. provided, which can be loaded by one of the usual commands for loading memory keys (such as in the IBM System / 360.

A comparison item belonging to the UFA memory protection operation corresponds to roughly how the memory key protection devices work, those in known systems such as ΙΒλΊ systems / 360 or IBM systems / 370 occur. The other parts of the UFA storage protection devices that work together are part of the new solution ', which is shown in this description, as well as its «combination with the special AAS selection circuit 333 (FIG. 3D).

For the comparison operation, the most significant bits 0-4 become the 16-bit physical address is used to select the register in the stack that is assigned to the dcmlnnenspcichcr block.

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The memory key in the selected register is retrieved. Of the AAS active address key is then selected with the one selected from the stack Storage keys in comparison circuit 502 (Fig. 11) are compared. If the comparison! · Indicates that the two keys are the same access is permitted provided that the UFA memory protection facility is enabled and that the access is either a fetch operation or a write operation, where the Mur read bit is set to 0. The UFA storage protection facility thus enables selective protection depending on the type of access; it can be used for addressing with no translation Separate memory protection for addresses in the areas OPIS, OPZS and ISS can be reached.

Another special feature of the UFA memory protection devices is the access control for shared memory areas, which is indicated by a special key value, and for accesses through I / O subchannels. Each user has access to the special memory areas, designated by keys, which are defined for the respective user in the ASR in the processor; all users can use the key -Ί in each register section of the ASR to define a memory area shared by the users

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7Π98Α5 / 0874

The circuit 505 controls the accesses to the shared memory areas.

A special access control for I / O operations when using the ÜFA memory protection devices is given by the circuits 50-1 and 505, which enable an I / O Cyclc Sleal access request to both the memory area for the relevant User is defined in his ASR, as well as can be made to the ingenious memory area with key = 7, whereby no I / O cycle steal access is prevented by the read-only bit in the memory key register used. In other words, I / O write access is always permitted regardless of the value of the read-only bit in the selected register in stack 501.

If the processor is in the monitoring program state, ie if bit 8 in the NSR (FIG. 4) is set, the memory key protection circuits are bypassed and all access to any block in the main memory is permitted.

In summary, it can be said that the address range selection control, which is given by the address key register ASR,

BC9-76-012 ^7ίΊ 9 ^ _5 / 08 7 4

is always used, both when the OFA memory protection facility is enabled as well as when using an additionally provided transfer device. The active address key AAS is either a CS key or eiji key that was selected more often from the ASR at Execution of a processor command, depending on which type Information is called up through the access (type of operand or Command).

If the UFA memory protection device is released, at least: one of the following conditions must be met, so that an attempted Memory access is allowed:

(l) The system is in the monitoring program state.

(?.) The memory key of the addressed block is 7. With a Attempt to write to memory must have the read-only bit ".

(3) The memory key of the addressed block must correspond to the active one Address key AAS must be the same. If a memory write operation is attempted, the read-only bit must be 0.

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'AVcnn none of the above conditions (]), (2) or (3) is met, the Inverter 507 (Fig. U) a memory access lock signal, read through a program error interruption (PCK) is caused which the corresponding bit in the processor status word register (PSW register) puts.

In the monitoring program status there is therefore free access to the internal Share the main memory given. Access to a memory area that has a memory protection key 7 is permitted regardless of the value of the active address key AAS or the values in the address key register ASR, if the system is not in the monitoring program state, provided that the value of the read-only bit for given the addressed block; Condition is not violated.

So it follows that within an individual, through a Address schilissei defined some addressable memory areas Blocks can be kept read-only while moving to others Blocks can be written to; this depends on the binary value of the read-only bit of the relevant blocks in the addressable Storage area. The read-only bit can be set by the monitoring program that loads the stack register.

7U984 5/0 874

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During the initial program load (IPL), both the UFA spcichcrs are protected zeinrichlungen as well as the overscraper facilities are both blocked, so that during the initial loading in every place of the main memory will be enrolled)! can. After the successful completion the introductory program load (IPL) can be either Storage protection devices are released, and in the event of occurrence from address keys in the ASR which are set to 0, the system goes into the monitoring program state.

Use the UFA memory protection device and the translator device although together the establishment of the active address key AAS, but they also have a number of characteristics that are different, such as:

(1) In the case of the UFA storage protection device, the monitoring program State of access to all parts of the main memory is allowed regardless of the memory key. In one System with translator can only be accessed in the monitoring program status to the memory area that is assigned by the. active address key AAS is defined.

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(2) The total storage capacity in a UFA storage protection system is defined by Adrcsschlür.scl is 6ΊΚ at most Bytes. All of the static memory used by the address key is definable in a translation system, can be used by everyone Time have a capacity of up to 512K bytes.

(3) In a translation system, it begins with the address key Defined address range at the logical address 0. In a UFA storage protection system the address range defined by the address key begins at various possible block boundaries each with a capacity of 2K bytes, but the address key always provides access control depending on the type.

(4) The instructions used to store the key register to load in the processor or to save from it are different from the instructions that are used in a System with translator to load the segment registers or to save them from them.

(5) For an I / O device in a system where a translator is enabled no memory protection error operation can occur,

7098 "45 /, 0874

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an I / O device in a system with a UFA memory protection device but can accept κ error operations for the access 7.U of an address that is not assigned to the CS key or by a key =? defined area belongs.

(6) Because of the flexibility given in a system with a translator for address translations are available if the UFA Spcicherschulz facilities are available certain conversions from logical to physical address areas are difficult to carry out, e.g. use of a common Area for only two address keys.

■ 3 · Alternative memory protection operating mode (ASB) for systems with wire translation

1A shows the control circuits for an alternative memory protection mode of operation (ASB) that can be used in a data processing system. This operating mode is an alternative to the one described above Type of translation, in which a multiple subdivided address- key register ASR (Fig. ID) is used. With this alternative There is no operating mode that depends on the type of memory access Adrcssicrbarkcit by the processor, which with the arrangement according to FIG. ID can be reached; however, it enables separate addressing areas for I / O memory access. The alternative mode of operation enables that Processor a different one, depending on an active address key

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Addressability for its various programs and data with different Bemil wheel key; but it also allows an interactive one Relationship of the user to the dear monitoring program, as far as necessary »- borrowed without losing the content of a user key register (DSR) 460 would have to be changed.

In the arrangement according to FIG. 1A, only a single address key can be used in the BSR-Rogistcr / «60 of the processor are loaded so that all Memory accesses for the execution of a user program and the corresponding Data can be accessed within a single address range defined by the user address key in BSR 460; this user address closure] cannot have a dBn value of zero because this is Value is reserved for the memory area in which the system monitoring programs and system data are available. I / O accesses are controlled by the CS key, which is entered from a subchannel in the CS key register 465 can be loaded.

The ASB operating mode is indicated for a processor by a bit position A im Level status register (NSR) 470 controlled. If the monitoring state is on, bit position S contains a one; when the ASB mode is switched on, bit position A contains a one.

If both bit positions S and A contain a one, a first type of processor operation is provided in which the monitoring program (which is contained in the address area with key = 0) with the address area of the current user address key (which is contained in the BSR 460)

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can work. This means that the monitoring program from the area with: Key = 0 works out, and thereby operands from the through the User-defined address range is used. The monitoring program but cannot access other address areas in the main memory which belong to other address part] iisse.l η. This mode of operation of the monitoring program with limited addressing space allows the programs for interrupt handling to access a currently interrupted user program and its data without the danger there is that the Ueberwachungsprogramin with its own disturbance the Disrupts the integrity of non-involved areas of the main memory. Furthermore A user program can never access the memory area of the monitoring program when it is executed, because every user program only to the memory area defined by its own user address key Has access.

A second type of processor operation occurs when the monitoring program bit S Kins and the ASB bit A are equal to zero . The monitoring program can work from the area with key = 0 without disturbing the current user key in the BSR 460. In this case, all command and operand access takes place only in the area with key = 0, and the monitoring program is not allowed to access any user area. This means that in this state the surveillance program has access neither to the user area which is identified by the current content of the BSR, nor to any other area defined by any other key. This type of system operation avoids the need to enter key - 0 into the BSR 460 at a time.

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A third type of processor operation is provided if the preferwatchprogramr.ibi t S is zero, where the value of the; ASB bit Λ without Is important. All output calls and operand accesses take place in this FnIl only in the area defined by user key ii;:;. el; to the main memory area with. the key = 0 then no accesses are allowed.

The ASB operating mode is defined in the processor by those in Tig. IA shown Circuit arrangement controlled. AND gate A62 is enabled when im KSR A70 both S-] iit and Λ-bit are set. This will make the. above described first type of processor operation initiated. Then will a signal on every command fetch request from the processor (Fig. A) AND gate 462, OR gate A66 and inverter A67 given to AND gate A61 to to block this during the command process. While dar, AND gate 461 is blocked, there is a zero signal, which represents the key = 0, to the AAS bus. A command call is therefore only permitted in the memory area of the monitoring program with the key = 0.

If there is no command call request (i.e. in the times between the command call requests) »the AND element A62 is not released, so that inverter A67 sends an active signal to AND gate A61 in order to put the user address key from BSR A60 onto the AAS bus, so that a command called up from the monitoring program to access operands that are in the area that belongs to the key in the BSR A60.

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BC9-7 <"012 -97-

If in the NSR the ASli bit Λ reset el It. Is (equal to zero), while the Ucberwac.hungsprogr.iimibit S is set (equal to one) · the AND-CIi ed 464 constantly released and blocks the AND gate "461, r.o." via inverter 467 that this constantly transfers the key = 0 to the AAS bus. From this it follows See the second type of processor operation described above, where the Monitoring program for all command calls and operand accesses to the Range of the key = 0 is restricted, regardless of the value of the User key s in the P.SR 460.

If the S bit in the NSR 470 is reset (equal to zero), AND gates remain 462 and 464 are permanently blocked, so that inverter 467 constantly supplies an enable signal to AND gate 461, which as a result, without interruption passes the user address key to the AAS-Rus. From it the third type of processor operation described above results in the all memory accesses, both for the processor and for I / O, in the Main memory area, the addressing of which is given by the user keys in BSR 460. The monitoring program can only work if Bit S is set (equal to one).

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Claims (7)

PATENT A NSPRUE CHü Spciilioi v.ucn iffsonoidnung in a data sharing system in which Key; ί.υι Sleueiuiig of saliva access used, marked by; Key selection devices (333, | ^: if | .3C) for delivering a key to memory train: iffseinrichtuii ^ en (Fig. 9A / 9B) ', Fehleidelektoroinrichtunrieri (421, Ί2?, | ^: Uj.4) for reporting errors - Signals l> if / machine or Piogram errors / a buffer jister (403, Fig /.), for recording the respective admissible passkey issued to the saliva access facilities; as eiiic gate sound (4C7, Fig. 4), whose control inputs with a line for a Prozrssoi cycle signal and with the Fehlerdetektoreinrichlungen are connected to only each time a processor cycle signal is present and in the absence of an error signal, one of the Key selection devices put the key in the buffer register transferred to. BC9-76-012 r <η «Η * / 0 P. 7 4 ORIGINAL INSPECTED 2. Speicherzugriff'cinoidnung yet / ^ nspiuch 1, characterized in that that an address key registration identification (420) is provided for storing several address keys, with at least one first registration key for an operand access key! and a second keiihleiubsclmill for a command key; that the exits of the Adiesssclilüsiellegisterunoidnung are connected to the entrances of the Sclilüvselausv / cihleinrichtungrui ) and that connections and other tools! Services are provided in order to transfer the last used address key from the buffer register (403) to the first regional section of the address key register arrangement when an error signal that causes an operating operation occurs (l ^: ig.4). BC9-70-012 -2- 3. memory access sanordnung according to claim 1 and / or 2, characterized characterized, i'ass forced address circuit (402, Fig. 4) is provided which are connected to c'en error detection devices (421, 422), and predetermined when error signals occur Deliver addresses to a control program read-only memory (ROS) in order to transfer the in the buffer register (408) stored last used address key in the address key register arrangement (402) necessary control signals by the decoder (40 5) of the control program read-only memory. 7 ü 9 9 4 S / 0 8 7 BC9-76-012 -3- 4. Memory access arrangement according to one or more of the claims 1 to 3, characterized in that the decoder (405) of the control program read-only memory (ROS) in the case of forced addressing i'by error signals also a control signal (AG 0) aligibt, which the entry of a key consisting of zeros in the instruction fetch register section (ISS) of the key register array cause, so that after the occurrence of an error both a key for a monitoring program address range for command retrieval as well as for the address area of the program interrupted by an error for operand access Are available. 709845/0874 BC9-76-012 -4- 5. Memory access arrangement according to one or more of the claims 1 to 4, characterized in that additional control circuits (Fig. 17) are provided for generating control signals, which when performing administrative operations (SEG.-REG. -cycle ^ or input / output operations (CS cycle ^ prevent the entry of a key by the gate circuit (407) in the buffer register (408). π r η ί λ πιο 7 ü 9 8 U_% J 0 8 7 4