WO1987002819A3 - Architecture de memoire de trame rapide utilisant des ram dynamiques - Google Patents

Architecture de memoire de trame rapide utilisant des ram dynamiques Download PDF

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Publication number
WO1987002819A3
WO1987002819A3 PCT/US1986/002185 US8602185W WO8702819A3 WO 1987002819 A3 WO1987002819 A3 WO 1987002819A3 US 8602185 W US8602185 W US 8602185W WO 8702819 A3 WO8702819 A3 WO 8702819A3
Authority
WO
WIPO (PCT)
Prior art keywords
frame store
data
bank
memory
banks
Prior art date
Application number
PCT/US1986/002185
Other languages
English (en)
Other versions
WO1987002819A2 (fr
Inventor
Billy Ernest Cates
Original Assignee
Eastman Kodak Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Eastman Kodak Co filed Critical Eastman Kodak Co
Publication of WO1987002819A2 publication Critical patent/WO1987002819A2/fr
Publication of WO1987002819A3 publication Critical patent/WO1987002819A3/fr

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

Mémoire de trame rapide incorporant un réseau de mémoires (28) possédant des blocs de mémoire sélectionnables (30-35) qui comprennent une pluralité de RAM dynamiques (DRAM) (10) relativement lentes. La mémoire de trame possède un circuit d'entrée tamponné (44) et un circuit de sortie tamponné (52) pour ralentir la cadence des données. Ces dernières peuvent être mémorisées en parallèle dans un bloc de mémoire sélectionné alors que d'autres données sont extraites simultanément en parallèle d'un autre bloc de mémoire. La régénération des DRAM d'un bloc non sélectionné a lieu simultanément avec le transfert de données vers la mémoire de trame ou à partir de celle-ci. Plusieurs blocs de mémoire de la mémoire de trame sont connectés à une ligne unique de sélection d'adresses de rangées (RAS), de sorte que lorsqu'un bloc de mémoire sélectionné est adressé pour le transfert de données, l'emplacement mémoire de plusieurs autres blocs non sélectionnés est régénéré.
PCT/US1986/002185 1985-10-23 1986-10-14 Architecture de memoire de trame rapide utilisant des ram dynamiques WO1987002819A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/790,691 US4725987A (en) 1985-10-23 1985-10-23 Architecture for a fast frame store using dynamic RAMS
US790,691 1985-10-23

Publications (2)

Publication Number Publication Date
WO1987002819A2 WO1987002819A2 (fr) 1987-05-07
WO1987002819A3 true WO1987002819A3 (fr) 1987-08-13

Family

ID=25151480

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1986/002185 WO1987002819A2 (fr) 1985-10-23 1986-10-14 Architecture de memoire de trame rapide utilisant des ram dynamiques

Country Status (4)

Country Link
US (1) US4725987A (fr)
EP (1) EP0246277A1 (fr)
JP (1) JPS63501179A (fr)
WO (1) WO1987002819A2 (fr)

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1293565C (fr) * 1986-04-28 1991-12-24 Norio Ebihara Memoire a semiconducteur
US4800530A (en) * 1986-08-19 1989-01-24 Kabushiki Kasiha Toshiba Semiconductor memory system with dynamic random access memory cells
US4773044A (en) * 1986-11-21 1988-09-20 Advanced Micro Devices, Inc Array-word-organized display memory and address generator with time-multiplexed address bus
US4875157A (en) * 1987-03-18 1989-10-17 International Telesystems Corporation Alternate memory addressing for information storage and retrieval
JPS63244393A (ja) * 1987-03-30 1988-10-11 Nec Corp 並列入出力回路を有する記憶装置
JPS63245567A (ja) * 1987-03-31 1988-10-12 Toshiba Corp 画像処理装置
JPS63282997A (ja) * 1987-05-15 1988-11-18 Mitsubishi Electric Corp ブロツクアクセスメモリ
US4875196A (en) * 1987-09-08 1989-10-17 Sharp Microelectronic Technology, Inc. Method of operating data buffer apparatus
US4918645A (en) * 1987-09-17 1990-04-17 Wang Laboratories, Inc. Computer bus having page mode memory access
JPS6484496A (en) * 1987-09-26 1989-03-29 Mitsubishi Electric Corp Semiconductor memory
US5280448A (en) * 1987-11-18 1994-01-18 Sony Corporation Dynamic memory with group bit lines and associated bit line group selector
US5093807A (en) * 1987-12-23 1992-03-03 Texas Instruments Incorporated Video frame storage system
JPH0821234B2 (ja) * 1988-01-14 1996-03-04 三菱電機株式会社 ダイナミック型半導体記憶装置およびその制御方法
US5301278A (en) * 1988-04-29 1994-04-05 International Business Machines Corporation Flexible dynamic memory controller
WO1990002780A1 (fr) * 1988-09-13 1990-03-22 Silicon Graphics, Inc. Procede et appareil pour effacer une region d'un tampon z
US5038297A (en) * 1988-09-13 1991-08-06 Silicon Graphics, Inc. Method and apparatus for clearing a region of Z-buffer
US5003475A (en) * 1988-11-25 1991-03-26 Picker International, Inc. Medical imaging system including means to increase data transfer speeds by simultaneously transferring data from latches to registers and from registers to latches
US5195182A (en) * 1989-04-03 1993-03-16 Eastman Kodak Company Frame buffer architecture for storing sequential data in alternating memory banks
US5408673A (en) * 1989-10-13 1995-04-18 Texas Instruments Incorporated Circuit for continuous processing of video signals in a synchronous vector processor and method of operating same
US5265228A (en) * 1989-12-05 1993-11-23 Texas Instruments Incorporated Apparatus for transfer of data units between buses
US5446321A (en) * 1990-06-19 1995-08-29 Texas Instruments Incorporated BICMOS tri-state circuit with full output voltage swing
DE69127518T2 (de) * 1990-06-19 1998-04-02 Dell Usa Lp Digitalrechner, der eine Anlage für das aufeinanderfolgende Auffrischen einer erweiterbaren dynamischen RAM-Speicherschaltung hat
US5479640A (en) * 1990-08-31 1995-12-26 International Business Machines Corporation Memory access system including a memory controller with memory redrive circuitry
US5465339A (en) * 1991-02-27 1995-11-07 Vlsi Technology, Inc. Decoupled refresh on local and system busses in a PC/at or similar microprocessor environment
DE4118154A1 (de) * 1991-06-03 1992-12-10 Philips Patentverwaltung Anordnung mit einer sensormatrix und einer ruecksetzanordnung
US5307314A (en) * 1991-07-15 1994-04-26 Micron Technology, Inc. Split read/write dynamic random access memory
US5276642A (en) * 1991-07-15 1994-01-04 Micron Technology, Inc. Method for performing a split read/write operation in a dynamic random access memory
US5321697A (en) * 1992-05-28 1994-06-14 Cray Research, Inc. Solid state storage device
US5506814A (en) * 1993-05-28 1996-04-09 Micron Technology, Inc. Video random access memory device and method implementing independent two WE nibble control
JP3386535B2 (ja) * 1993-11-26 2003-03-17 株式会社リコー 中央演算処理装置内汎用レジスタセット回路装置
FI104393B (fi) * 1996-03-06 2000-01-14 Nokia Satellite Systems Ab Dram-muistipankkien virkistys
US6504548B2 (en) 1998-09-18 2003-01-07 Hitachi, Ltd. Data processing apparatus having DRAM incorporated therein
WO1997035316A1 (fr) * 1996-03-21 1997-09-25 Hitachi, Ltd. Processeur a memoire dram integree
GB2379768B (en) * 2000-10-25 2003-08-20 Samsung Electronics Co Ltd Memory device, method of accessing the memory device, and reed-solomon decoder including the memory device
KR100370239B1 (ko) * 2000-10-25 2003-01-29 삼성전자 주식회사 고속 블럭 파이프라인 구조의 리드-솔로몬 디코더에적용하기 위한 메모리 장치와 메모리 액세스 방법 및 그메모리 장치를 구비한 리드-솔로몬 디코더
GB2380035B (en) 2001-09-19 2003-08-20 3Com Corp DRAM refresh command operation
KR100403634B1 (ko) * 2001-10-17 2003-10-30 삼성전자주식회사 고속 파이프라인 리드-솔로몬 디코더에 적용하기 위한메모리 장치와 메모리 액세스 방법 및 그 메모리 장치를구비한 리드-솔로몬 디코더
JP4975288B2 (ja) * 2005-09-05 2012-07-11 ソニー株式会社 共有メモリ装置
KR20160063726A (ko) * 2014-11-27 2016-06-07 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
KR102296740B1 (ko) * 2015-09-16 2021-09-01 삼성전자 주식회사 메모리 장치 및 그것을 포함하는 메모리 시스템

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0149757A2 (fr) * 1983-12-30 1985-07-31 International Business Machines Corporation Système à mémoire numérique apte à l'usage d'une mémoire tampon d'image

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3905023A (en) * 1973-08-15 1975-09-09 Burroughs Corp Large scale multi-level information processing system employing improved failsaft techniques
GB1568379A (en) * 1976-02-19 1980-05-29 Micro Consultants Ltd Video store
US4079462A (en) * 1976-05-07 1978-03-14 Intel Corporation Refreshing apparatus for MOS dynamic RAMs
JPS54132135A (en) * 1978-04-06 1979-10-13 Sony Corp Memory control unit
US4185323A (en) * 1978-07-20 1980-01-22 Honeywell Information Systems Inc. Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations
US4241425A (en) * 1979-02-09 1980-12-23 Bell Telephone Laboratories, Incorporated Organization for dynamic random access memory
US4513374A (en) * 1981-09-25 1985-04-23 Ltv Aerospace And Defense Memory system
JPS5891590A (ja) * 1981-11-27 1983-05-31 Fujitsu Ltd メモリシステム
JPS58182185A (ja) * 1982-04-19 1983-10-25 Nec Corp 半導体記憶装置
US4636942A (en) * 1983-04-25 1987-01-13 Cray Research, Inc. Computer vector multiprocessing control
US4616310A (en) * 1983-05-20 1986-10-07 International Business Machines Corporation Communicating random access memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0149757A2 (fr) * 1983-12-30 1985-07-31 International Business Machines Corporation Système à mémoire numérique apte à l'usage d'une mémoire tampon d'image

Non-Patent Citations (5)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Volume 17, No. 3, August 1974, (New York, US), WILLIAMS: "High-Speed Random-Access Memory with Simultaneous Read/Write Operation", pages 933-934, see the whole article *
IBM Technical Disclosure Bulletin, Volume 25, No. 5, October 1982, (New York, US), GRIMES, MARTINEZ & WYATT: "Access Rate/Availability Improvement Logic for Dynamic Memories", pages 2678-2682 *
PATENT ABSTRACTS OF JAPAN, Volume 3, No. 153, (E-159) 15 December 1979 & JP, A, 54-132135 (Sony K.K.) 13 October 1979 *
PATENT ABSTRACTS OF JAPAN, Volume 7, No. 192, (1337) (P-218) 23 August 1983, & JP, A, 58-91590 (Fujitsu K.K.) 31 May 1983 *
PATENT ABSTRACTS OF JAPAN, Volume 8, No. 27, (P-252) (1464) 4 February 1984, & JP, A, 58-182185 (Nippon Denki K.K.) 25 October 1983 *

Also Published As

Publication number Publication date
EP0246277A1 (fr) 1987-11-25
US4725987A (en) 1988-02-16
WO1987002819A2 (fr) 1987-05-07
JPS63501179A (ja) 1988-04-28

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