WO1987000944A1 - Image processor - Google Patents
Image processor Download PDFInfo
- Publication number
- WO1987000944A1 WO1987000944A1 PCT/JP1986/000405 JP8600405W WO8700944A1 WO 1987000944 A1 WO1987000944 A1 WO 1987000944A1 JP 8600405 W JP8600405 W JP 8600405W WO 8700944 A1 WO8700944 A1 WO 8700944A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- image
- image processing
- frame memory
- memory
- processor
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/60—Memory management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T2200/00—Indexing scheme for image data processing or generation, in general
- G06T2200/28—Indexing scheme for image data processing or generation, in general involving image processing hardware
Definitions
- the invention is a processing device for an image to be displayed on a display device such as a CRT display, and more specifically, an image operation for recognizing a feature of an object in an image.
- the present invention relates to an image processing device that can be regulated according to a pattern.
- a buffer memory such as a frame memory having a storage area corresponding to the display screen, and is included in the image data.
- Object position discrimination and shape recognition are realized by performing a predetermined image processing operation using all the information in the frame memory.
- An object of the present invention is to provide an image processing apparatus capable of realizing efficient image processing by designating the validity / invalidity of the function for each pixel.
- the image processing device that displays the image from the sensor on the display device performs the image processing operation.
- the processor and the image to be processed are stored.
- a control circuit is provided for reading data and drawing the data on the display device.
- the image processing device which has been developed in the above manner, has a window memory with a size corresponding to the frame memory in the window memory. Since the bit pattern that specifies the validity / invalidity of this operation is stored, it is possible to execute image processing while referring to the validity bit. Therefore, the calculation speed can be increased, and large-capacity memory is required for complicated data processing such as filtering and filtering. , ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ It has fruit.
- FIG. 1 is a block diagram illustrating an embodiment of an image processing apparatus according to the present invention
- FIG. 2 is an example of a CRT controller used in the image processing apparatus according to the present invention.
- FIG. 1 is a block diagram of an image processing apparatus of the present invention
- FIG. 2 is an example of an internal configuration of a CR controller ⁇ used in the image processing apparatus of the present invention.
- FIG. 1 denotes an image processing operation, which is connected to a frame memory 2 by a processor.
- the frame memory 2 is prepared for a plurality of sheets, and each stores the image data two-dimensionally as a plurality of vertical and horizontal pixel data.
- Reference numeral 3 denotes an AD converter, which converts an analog image from the video camera into a digital signal and transmits the digital signal through a bus transmitter receiver 4. And write it to frame memory 2.
- Reference numeral 5 denotes a window memory of a size corresponding to the frame memory 2 described above, which specifies whether the image processing operation executed by the processor 1 is enabled or disabled. A bit pattern for this purpose.
- This window memory 5 is connected to a CRT controller 6 having a drawing control function and is connected to a program. It is also connected to Sessor 1.
- the CRT controller 6 generates a synchronizing signal for capturing image data from the video camera, and outputs an image one frame at a time to the frame memory 2 described above.
- a control circuit that has a function of reading a predetermined image from a frame memory 2 on a display device (CRT) not shown in the drawing and storing the data in a host CP'U It is connected to the 7 main bus 8. Then, this CRT controller 6 is a bit pattern that is stored in a command specified by the host CPU 7 and stored in a window memory 5. It also has the function of causing the robot to translate, rotate, or rotate the stored bit turn to a predetermined position.
- reference numeral 9 denotes a bus transmitter receiver similar to the one in 4 above, which can transfer pixel data at high speed with the frame memory 2
- the DMA bus 10 and the above-mentioned main bus 8 are connected.
- the above CRT controller 6 is composed of three processors, each of which is independently controlled by a microprogram in the controller shown in FIG. 2, and a drawing processor. 11, display processor 12, timing processor ⁇ 13, the interface 14 on the host CPU 7 side, and the CRT side It consists of the interface 15.
- the drawing processor 11 interprets the commands and / parameters transferred from the host CPU 7 and draws the data to the window memory 5. Perform image processing. That is, the drawing pro
- the sensor 11 sequentially generates a drawing address based on the graphic generation algorithm, and performs a data operation on the designated pixel of the image data. It is possible.
- the display processor 12 controls the display address of the frame memory 2 according to the screen format displayed on the CRT.
- the timing processor 13 generates various timing signals required inside the CRT synchronization signal (controller 6).
- the interface 14 on the host CPU 7 has an asynchronous path interface control function for enabling kneading with a general-purpose microprocessor, and a DMA core. Equipped with a control function for the controller and an interrupt control function, and a bit from the host CPU 7 to the window memory 5. You can write turns and read them back to write them.
- the interface 15 on the CRT side is used to input / output synchronous control signals and image data signals to / from the video camera and CRT, and write data to and from the interface.
- the configuration is such that the dress and the display address can be dynamically switched according to various operation modes.
- the image processing apparatus is configured as described above, and the processor 1 accesses a predetermined image data of the frame memory 2 by the processor 1.
- the size corresponding to the frame memory is added to the window memory 5.
- the bit memory that is regulated according to the pin memory is the command from the host CPU 7. It can be rotated appropriately according to the CRT controller 6 and can be moved in parallel, and if necessary, displayed on the display device from the CRT controller 6. However, it is possible to easily change and set the pattern.
- the image processing apparatus uses the CRT content ⁇ which is conventionally set in the frame memory as a window pointer.
- the size of the window corresponding to the frame memory connected to the camera is stored in the memory, and the validity / invalidity of the operation is calculated for each pixel of the image data. Because it is specified, the performance speed can be increased, and the capacity is large for complicated data processing such as filtering operation. It does not require a large amount of memory, but has an operational effect such as realizing efficient image processing.
- the image processing apparatus of the present invention is not limited to the above embodiment, and various methods are possible for the configuration of a CRT controller.
- the image processing apparatus is capable of performing image processing on a processor in a window memory of a size corresponding to the frame memory.
- the bit pattern for specifying the validity / invalidity of the image data is recorded and the validity / invalidity of the function is specified for each pixel of the image data. Therefore, the present invention is suitably applied to a display device for displaying a working state of a robot for industrial use.
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Image Processing (AREA)
- Image Generation (AREA)
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019870700303A KR910000202B1 (ko) | 1985-08-08 | 1986-08-07 | 화상 처리장치 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60/174739 | 1985-08-08 | ||
JP60174739A JPS6234281A (ja) | 1985-08-08 | 1985-08-08 | 画像処理装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1987000944A1 true WO1987000944A1 (en) | 1987-02-12 |
Family
ID=15983824
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1986/000405 WO1987000944A1 (en) | 1985-08-08 | 1986-08-07 | Image processor |
Country Status (5)
Country | Link |
---|---|
US (1) | US4829454A (ja) |
EP (1) | EP0245504A4 (ja) |
JP (1) | JPS6234281A (ja) |
KR (1) | KR910000202B1 (ja) |
WO (1) | WO1987000944A1 (ja) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62278682A (ja) * | 1986-05-27 | 1987-12-03 | Fanuc Ltd | 画像処理装置 |
GB8804023D0 (en) * | 1988-02-22 | 1988-03-23 | Crosfield Electronics Ltd | Image assembly |
US4947257A (en) * | 1988-10-04 | 1990-08-07 | Bell Communications Research, Inc. | Raster assembly processor |
US5043923A (en) * | 1988-10-07 | 1991-08-27 | Sun Microsystems, Inc. | Apparatus for rapidly switching between frames to be presented on a computer output display |
EP0411836A3 (en) * | 1989-07-31 | 1993-02-03 | Kabushiki Kaisha Toshiba | Image processing apparatus |
US5327243A (en) * | 1989-12-05 | 1994-07-05 | Rasterops Corporation | Real time video converter |
EP0660266A4 (en) * | 1993-06-30 | 1996-01-03 | Sega Enterprises Kk | IMAGE PROCESSING METHOD AND DEVICE THEREFOR. |
JP3932379B2 (ja) * | 2001-10-02 | 2007-06-20 | 株式会社日立製作所 | 画像処理装置と撮像素子 |
TW201215149A (en) | 2010-09-17 | 2012-04-01 | Alpha Imaging Technology Corp | Notebook computer for processing original high resolution images and image processing device thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53124946A (en) * | 1977-04-08 | 1978-10-31 | Agency Of Ind Science & Technol | Operation mask unit |
JPS53148233A (en) * | 1977-05-30 | 1978-12-23 | Fujitsu Ltd | Image-data scrolling system |
JPH0627084A (ja) * | 1992-07-08 | 1994-02-04 | Mitsubishi Heavy Ind Ltd | 座金非破壊検査装置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3175773D1 (en) * | 1980-06-10 | 1987-02-05 | Fujitsu Ltd | Pattern position recognition apparatus |
US4400728A (en) * | 1981-02-24 | 1983-08-23 | Everett/Charles, Inc. | Video process control apparatus |
US4479145A (en) * | 1981-07-29 | 1984-10-23 | Nippon Kogaku K.K. | Apparatus for detecting the defect of pattern |
US4589139A (en) * | 1982-02-04 | 1986-05-13 | Nippon Kogaku K. K. | Apparatus for detecting defects in pattern |
JPS58174753A (ja) * | 1982-04-05 | 1983-10-13 | Nhk Spring Co Ltd | ロツク機構付回転力伝達装置 |
US4437114A (en) * | 1982-06-07 | 1984-03-13 | Farrand Optical Co., Inc. | Robotic vision system |
JPS5951536A (ja) * | 1982-09-14 | 1984-03-26 | Fujitsu Ltd | パタ−ン認識方法及びその装置 |
JPS59119385A (ja) * | 1982-12-27 | 1984-07-10 | 株式会社ピーエフユー | ビツト・マツプ・メモリ上のウインドウ移動制御方式 |
JPS6027084A (ja) * | 1983-07-25 | 1985-02-12 | Fanuc Ltd | 画像のウインドウ処理方式 |
JPS60146366A (ja) * | 1984-01-10 | 1985-08-02 | Mitsubishi Electric Corp | 画像処理装置 |
JPS61291944A (ja) * | 1985-06-20 | 1986-12-22 | Agency Of Ind Science & Technol | 摺動面用材料 |
US4707647A (en) * | 1986-05-19 | 1987-11-17 | Gmf Robotics Corporation | Gray scale vision method and system utilizing same |
-
1985
- 1985-08-08 JP JP60174739A patent/JPS6234281A/ja active Pending
-
1986
- 1986-08-07 EP EP19860904924 patent/EP0245504A4/en not_active Ceased
- 1986-08-07 US US07/046,919 patent/US4829454A/en not_active Expired - Fee Related
- 1986-08-07 KR KR1019870700303A patent/KR910000202B1/ko not_active IP Right Cessation
- 1986-08-07 WO PCT/JP1986/000405 patent/WO1987000944A1/ja not_active Application Discontinuation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53124946A (en) * | 1977-04-08 | 1978-10-31 | Agency Of Ind Science & Technol | Operation mask unit |
JPS53148233A (en) * | 1977-05-30 | 1978-12-23 | Fujitsu Ltd | Image-data scrolling system |
JPH0627084A (ja) * | 1992-07-08 | 1994-02-04 | Mitsubishi Heavy Ind Ltd | 座金非破壊検査装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP0245504A4 * |
Also Published As
Publication number | Publication date |
---|---|
JPS6234281A (ja) | 1987-02-14 |
KR910000202B1 (ko) | 1991-01-23 |
KR880700357A (ko) | 1988-02-22 |
EP0245504A1 (en) | 1987-11-19 |
US4829454A (en) | 1989-05-09 |
EP0245504A4 (en) | 1989-12-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9479693B2 (en) | Method and mobile terminal apparatus for displaying specialized visual guides for photography | |
US9071750B2 (en) | Semiconductor integrated circuit and multi-angle video system | |
WO1987000944A1 (en) | Image processor | |
WO1987001223A1 (en) | Image processor | |
WO2020047742A1 (zh) | 手写板、手写板装置及书写控制方法 | |
JPS61251967A (ja) | 画像処理装置 | |
CN101472126A (zh) | 数字基频处理器及其之操作方法、以及无线装置及其方法 | |
JP3154741B2 (ja) | 画像処理装置及びその方式 | |
US5333259A (en) | Graphic information processing system having a RISC CPU for displaying information in a window | |
JPS6334658A (ja) | 画像処理用dmaコントロ−ラ | |
JPS59214944A (ja) | 図形出力端末装置 | |
TWI755849B (zh) | Fpga多主從硬體架構之即時物件追蹤系統 | |
JP6752311B2 (ja) | 表示装置及び表示方法 | |
JP2510219B2 (ja) | 画像処理装置 | |
JP2004094498A (ja) | 画像表示システム及び表示装置 | |
JPS60114926A (ja) | 二次元座標データの変換装置 | |
JPH0424748B2 (ja) | ||
JPH10326249A (ja) | Dma転送領域の制御方法および装置 | |
JPH07307895A (ja) | 静止画像表示装置及びその操作盤 | |
JPS61202284A (ja) | 画像処理装置 | |
JPS6242274A (ja) | 画像処理装置 | |
JPH03100695A (ja) | マトリクス方式フラットディスプレイ装置 | |
JPS62175875A (ja) | メモリプロテクト方式 | |
JPH04130945A (ja) | 情報処理装置 | |
JPH05204371A (ja) | 画像表示制御装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): DE FR GB |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1986904924 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1986904924 Country of ref document: EP |
|
WWR | Wipo information: refused in national office |
Ref document number: 1986904924 Country of ref document: EP |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1986904924 Country of ref document: EP |