Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/121—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/22—Secondary treatment of printed circuits
  • H05K3/28—Applying non-metallic protective coatings
  • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/531—Shapes of wire connectors
  • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
  • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/551—Materials of bond wires
  • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
  • H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
  • Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Definitions

• the invention relates to a method for encapsulating microelectronic hybrid semiconductor circuits or microelectronic semiconductor components.
• housings are used for this, which are hermetically sealed or soldered.
• Such housings e.g. Kovar housing, as well as the associated encapsulation technologies, e.g. the roll seam, ring hump, electron or laser beam welding or the glass soldering as well as the tempering techniques are very complex or expensive and thermally not uncritical for microcircuits.
• Hybrids that are densely populated with bonded ICs or small, discrete components cannot be laminated without pressure, without voids, without cavities, and with adhesive strength, so that when the temperature changes between -65 ° and + 125 ° C, detachments or wire deformations occur. which also affect the electrical functional properties.
• this is achieved in that the components located on a substrate are covered with a soft, sealable plastic layer, covered with a plastic-metal composite film and then encapsulated with synthetic resin.
• the lining of the film with a non-porous, non-corrosive, soft-elastic cover, which is firmly connected to the circuit and to the plastic-metal film, in connection with the metal film solves the problems previously encountered.
• Fig. 2 shows schematically the steps of a first
• Fig. 3 shows a second variant of the method.
• Fig. 1 shows the basic structure of a circuit encapsulated by the inventive method.
• a substrate S which suitably consists of Al-, 0 3 , adheres, for example, with Si_N. passi 4 4 fourth microelectronic component B, which is electrically connected to the conductor tracks LB in a known manner with bonding wires D, which consist of gold, aluminum or other highly conductive metal.
• the building block B and the bonding wires are located within a soft plastic layer W. This is covered with a film F which contains a metal layer and the structure of which is described below.
• epoxy resin H with a high-purity SiO or chalk filling.
• a complete solution according to the invention consists in that the microelectronic circuit B, which is passivated, for example, with Si N. and bonded to a substrate S, is coated with a plastic layer W which is soft in the operating temperature range and which can be deformed with a heat and crack-free deformation Plastic-metal-plastic composite film F can be sealed or glued and, if necessary, encapsulated and solidified with a highly filled, highly cross-linked synthetic resin H.
• the proven heat-sealing method according to FIG. 2 is particularly well suited for the efficient implementation of the method according to the invention.
• the bonded component B is initially on the substrate S.
• the bond wires D electrically connect the component B to the conductor tracks LB.
• Passivation P prevents unwanted corrosion.
• the prepared circuit is first preheated.
• a low-viscosity, liquid elastomer W is then applied in accordance with step b).
• the resulting layer W is heat sealable.
• the metal composite film F is placed and pressed onto the soft layer W with a hollow stamp ST heated to approximately 200 ° C.
• the plastic side of the film F facing the layer W connects to it under the influence of heat and pressure.
• the filling W solidifies.
• deformation of the composite film during punching has proven to be advantageous.
• This process is therefore based on the fact that, for example, silicones modified with polyolefins can be easily deformed and sealed with polypropylene films at 160-190 ° C. under pressure.
• a metal layer preferably rolled copper or aluminum foils, as a cover for high-purity polypropylene-polyethylene, polyethylenetereplethalate, polycarbonate, polyimide foils.
• a delamination or cracking is unknown with such composite films, the gas and moisture permeability is many orders of magnitude smaller than with epoxy resin or silicone elastomer packaging. Diffusion and permeation is only possible along the approximately 10-100 ⁇ m thick but millimeter-long boundary layer between the semiconductor circuit and the aluminum layer.
• the rolled metal foil which is electrically insulated on both sides, also facilitates rapid temperature compensation in the case of power semiconductor circuits or power hybrid circuits.
• the substrate S with the components is located on a carrier consisting of the inner part Ti and the outer part Ta.
• the edge of the substrate protrudes beyond the inner part Ti of the carrier and is printed on the back with a solder ring LK.
• the conductor tracks are insulated from the solder ring with a dielectric layer.
• Method step b) takes place as in the example according to FIG. 2.
• process step c) ie when the film is applied, a film F preformed in accordance with the topology of the components is used here.
• the stamp ST is also adapted to the shape of the film. After the film has been applied, it is folded over at the edges of the substrate after removal of the outer part TA of the carrier and is soldered to the solder ring as shown in FIG. 3d.
• the element can then be cast with epoxy resin H.
• Copper foils laminated on one side are particularly suitable for soldering.
• the epoxy resin quartz potting serves as mechanical protection.
• the chip or the passivated semiconductor circuit is placed on the carrier and bonded at the connections.
• the chip and all bond connections are coated with a low-viscosity plastic, which is characterized by very low gas and water vapor permeability, high flexibility and sealability.
• a polyolefin-modified silicone solution in petrol is applied to the substrate primed with p-methyldisiloxane-methyl methacrylate.
• a cap dimensioned for the chip is hot (approx. 120 °) punched, put over the chip carrier with a die bonder and sealed with the soft potting compound by means of a hot hollow stamp.
• the approximately 180 ° C hot stamp presses the film with the liquid soft casting onto the substrate in such a way that the sealing layer is less than approx. 20 ⁇ .
• the cap or encapsulated circuit is cast with high-purity, flexible epoxy resin / quartz powder casting compounds.
• a resin is suitable as a potting compound
• the thixotropic casting compound is applied mixed at 140 ° and cured for five hours.
• a thick-film hybrid circuit with semiconductor chips and discrete components is coated with a hot polyethylene / xylene solution, covered with a suitably cut, possibly preformed composite film, pressed to the substrate, glued or sealed.
• the encapsulated hybrid circuit is then molded or filled with a filled epoxy resin.
• a bonded hybrid circuit is preheated to approximately 100 ° C., placed on a vacuum holding device and covered with a copper (25 ⁇ ) adhesive film which is pre-punched and pre-shaped in accordance with the circuit.
• the conductor tracks of the circuit are covered with dielectric paste at the intended contact or soldering points during screen printing. Before the film is sealed, these areas are printed with solder paste.
• the film is folded under vacuum, sealed with the resin, then soldered and encapsulated or cast with a filled epoxy resin.

Landscapes

• Engineering & Computer Science (AREA)
• Manufacturing & Machinery (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
• Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
• Non-Metallic Protective Coatings For Printed Circuits (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

Family

ID=6250592

Family Applications (1)

Country Status (5)

Cited By (3)

Families Citing this family (54)

Citations (4)

Family Cites Families (16)

• 1984
  • 1984-11-17 DE DE19843442131 patent/DE3442131A1/de active Granted
• 1985
  • 1985-11-18 US US06/909,118 patent/US4784872A/en not_active Expired - Fee Related
  • 1985-11-18 EP EP85905776A patent/EP0202279B1/de not_active Expired
  • 1985-11-18 WO PCT/DE1985/000475 patent/WO1986003055A1/de not_active Ceased
  • 1985-11-18 JP JP60505156A patent/JPH0626223B2/ja not_active Expired - Lifetime

Patent Citations (4)

Non-Patent Citations (2)

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