Classifications

• • G—PHYSICS
  • G02—OPTICS
  • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
  • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
  • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
  • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
  • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
  • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
  • G02F1/1362—Active matrix addressed cells
  • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
  • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
  • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
  • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
  • G09G3/3611—Control of matrices with row and column drivers
  • G09G3/3648—Control of matrices with row and column drivers using an active matrix
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2300/00—Aspects of the constitution of display devices
  • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
  • G09G2300/0809—Several active elements per pixel in active matrix panels
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
  • G09G2330/08—Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared

Definitions

• the present invention relates to an active matrix display screen with double addressing transistor.
• An active matrix display screen is a device formed by a mosaic of memory points distributed over the entire surface of a support. These memory points store the video signal during the entire display period of an image.
• An electronic transducer for example a liquid crystal
• This transducer is excited for the entire duration of an age, whereas, in systems without electronic memory, the transducer is only requested during the duration of the excitation of the point. The optical effect and the multiplexing rate are therefore improved.
• the thin film trans stor lends itself well to the realization of such a device.
• Each memory point is then located at the crossroads of a row and an addressing column and it is consumed by an addressing TCM and a capacitor.
• the reinforcements of the capacitor are constituted by the electrodes of the liquid crystal cell themselves.
• the memory point therefore boils down to a TCM and a capacitor, one of the armatures of which is formed by the electrode d placed on one of the walls of the cell which contains the liquid crystal, the other armature being formed by the counter-electrode placed on the other wall of the cell.
• FIG. 1 Such a structure is shown in FIG. 1.
• a lower wall 10 carrying conductive columns 12 and lines conductive 14, a TCM 20 and a transparent electrode 22, and on the other hand, a top wall 24 covered with a counter electrode 26 also transparent.
• the addressing of such a device is carried out in the following manner.
• the lines are brought sequentially to a potent which corresponds to the grid tens on able to make the TCM conductive.
• the video signals are applied successively to the various columns, which has the effect of exciting all the display points (or "pixels") of the line. .
• the command of a line being completed, we pass to the next line, etc.
• FIG. 2 illustrates for example a technique described by AJ SNELL et al. in an article entitled “Application of Amorphous Si licon Field Effect Transistors in Adressable Liquid Crystal Display PaneLs" published in "Applied Physics", 24, 357-362 (1981).
• the TCM is formed by a grid G in chromium deposited on an insulating substrate 30, a layer of amorphous silicon 34 (aSi), a drain D and a source S of aluminum.
• the lower armature of the capacitor is formed by a layer 38 of oxide tin and indiu.
• connection between the TCM and the armature is made by the drain D extended by a lug 40 which borrows a contact hole 42.
• the entire circuit consists of a plurality of such structures arranged in matrix form.
• the gri gles G are formed by connection lines 44 and the sources by columns 46.
• TCM presents its source and drain contacts at the lower part and its chip at the upper part.
• This technique is described by M. MATSUMURA et al. in the article entitled “Amo rphous-Si li con Integrated Circuit", published in “Proceedings of the IEEE", vol.68, n ⁇ 10, October 1980, pages 1349-1350.
• a layer 102 of transparent conductive material for example tin oxide and i ndi um (a); - first photogravure, to give La layer 102 the form of columns 104 and pavers 106 provided with a rectangular appendage 108 (b);
• the TCMs are located in the overlapping areas of the lines 116 and the columns 104.
• the source and the drain are respectively constituted by the appendix 108 and the part of the column 104 located under the line 116 ; the control grid consists of the part of line 116 which is located between appendix 108 and column 104.
• the invention recommends using no more than one but two addressing transistors per pixel, these two trans stors being connected to adjacent genes and columns.
• an electrode Pn, p which traditionally was connected to a line Ln and to a column Cp by an addressing transistor Tn, p is also connected, to the following line Ln + 1 and to the column su boasts Cp + 1 by a second transistor noted Tn + 1, p + 1 ( in these notations n and p are integers between 1 and N and P respectively, if N and P are the numbers of L genes and columns of L 'display).
• FIG. 1 already described, schematically represents a display point of an active matrix
• FIG. 2, already described illustrates a known method for producing an active matrix
• FIG. 3, already described illustrates another known method for producing an active matrix
• FIG. 4 schematically represents the principle of a display screen according to the invention
• FIG. 5 shows an exemplary embodiment of such a screen.
• Figure 4 shows, schematically. The principle of the active matrix display screen according to the invention.
• only two address lines are shown, of rank n and n + 1 and • only two columns of rank p and p + 1. These rows and columns are noted Ln, Ln + 1 and Cp, Cp + 1.
• a display point is identified by a double index, the first relating to the line above it and the second to the column preceding it.
• the display point, or pixel, denoted Pn, p is the point located under the Line Ln and to the right of the column Cp.
• each display point Pn, p is connected to two addressing transistors: a first transistor Tn, p which connects it to Ln and Cp and a second transistor Tn + 1, p + 1 which connects it at Ln + 1 and at Cp + 1.
• the addressing is carried out in the following manner. When Line Ln is active, Pn, p is excited through Tn, p When column Cp receives the appropriate video signal. But Pn, p is energized a second time when L 'ine Ln + 1 is active and when the column Pc + 1 receives the video signal. It is therefore the second excitation which is finally memorized.
• the columns of the screen can be interdigitated, that is to say connected one in two to the addressing circuit by connections located either at the top or at the bottom of the screen.
• Two columns which are adjacent in one of the half addressing systems are in fact not adjacent in the overall system. These are, for example, columns Cn + 1, Cn + 3 or Cn and Cn + 2.
• the effects of breaks in two adjacent columns are suppressed.
• any of the methods described above can be used, with this adaptation consisting in providing two transistors per pixel instead of one.
• Each display point includes a rectangular (or square) block 106 with two appendices 108 and 108 which extend along two adjacent columns 114 and which engage under two adjacent lines 116.
• the first addressing transistor is located in the zone of overlap of a line 116 with respectively a column 114 and the first appendix 108.
• the second transistor is located in the zone of overlap of the line sui ⁇ vvaannttee aavveecc rreessppeeccttiivvement the second appendix 108 and the next column.

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• Physics & Mathematics (AREA)
• Engineering & Computer Science (AREA)
• Nonlinear Science (AREA)
• General Physics & Mathematics (AREA)
• Chemical & Material Sciences (AREA)
• Crystallography & Structural Chemistry (AREA)
• Mathematical Physics (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Optics & Photonics (AREA)
• Computer Hardware Design (AREA)
• Theoretical Computer Science (AREA)
• Liquid Crystal (AREA)
• Devices For Indicating Variable Information By Combining Individual Elements (AREA)
• Liquid Crystal Display Device Control (AREA)

Priority Applications (1)

Applications Claiming Priority (2)

Publications (1)

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ID=9308737

Family Applications (1)

Country Status (7)

Families Citing this family (12)

Citations (3)

Family Cites Families (6)

• 1984
  • 1984-10-17 FR FR8415899A patent/FR2571913B1/fr not_active Expired
• 1985
  • 1985-10-11 DE DE8585904986T patent/DE3576087D1/de not_active Expired - Lifetime
  • 1985-10-11 US US06/882,906 patent/US5003302A/en not_active Expired - Lifetime
  • 1985-10-11 JP JP60504478A patent/JPS62500744A/ja active Granted
  • 1985-10-11 EP EP85904986A patent/EP0197992B1/fr not_active Expired - Lifetime
  • 1985-10-11 WO PCT/FR1985/000289 patent/WO1986002464A1/fr not_active Ceased
  • 1985-10-16 CA CA000493092A patent/CA1261954A/fr not_active Expired

Patent Citations (3)

Non-Patent Citations (1)

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