US9953859B2 - SOI wafer manufacturing process and SOI wafer - Google Patents

SOI wafer manufacturing process and SOI wafer Download PDF

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US9953859B2
US9953859B2 US15/241,431 US201615241431A US9953859B2 US 9953859 B2 US9953859 B2 US 9953859B2 US 201615241431 A US201615241431 A US 201615241431A US 9953859 B2 US9953859 B2 US 9953859B2
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substrate
active layer
oxide film
soi wafer
layer
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Yoshihiro Koga
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Sumco Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H01L21/84—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN

Definitions

  • the present disclosure relates to an SOI wafer manufacturing process and to an SOI wafer.
  • An silicon on insulator (SOI) wafer structurally includes a support substrate, above which an insulating film of, for example, oxide silicon (SiO 2 ), and a single crystal silicon layer used as a device active layer are formed in this order.
  • a bonding method is one of typical methods of manufacturing an SOI wafer. The bonding method is a method of manufacturing an SOI wafer by forming an oxide film (a buried oxide [BOX] layer) on at least one of the support substrate and the substrate to be used as the active layer, and subsequently by superposing these substrates on each other via the oxide film and subjecting the superposed substrates to bonding thermal processing at a high temperature of approximately 1200° C.
  • oxide film a buried oxide [BOX] layer
  • Patent Literature 1 describes a bonded SOI wafer manufacturing process, including implanting ions to a substrate to be used as the active layer to form a strain region (a gettering site), subsequently forming the oxide film on the substrate to be used as the active layer or on the support substrate according to a thermal oxidization method, and subsequently superposing both the substrates and subjecting the superposed substrates to bonding thermal processing.
  • the present disclosure is to provide an SOI wafer manufacturing process that allows production of an SOI wafer having a high gettering ability and a small resistance variance in the thickness direction of the active layer, at high productivity.
  • the present inventor has conducted earnest studies to solve the above problems and found the following.
  • one of two silicon wafers bonded together that includes a portion finally constituting the active layer of the SOI wafer is called the “substrate to be used as the active layer” or the “first substrate”
  • the other one of the two silicon wafers that constitutes a supporting portion of the SOI wafer is called the “support substrate” or the “second substrate”.
  • the ion implantation layer is formed on the support substrate and subsequently, an oxide film is similarly formed on the support substrate. Furthermore, when an oxide film is formed on both the substrate to be used as the active layer and the support substrate according to the thermal oxidization method to produce the SOI wafer including an overall thick oxide film within a short period of time, regardless of which one of the substrates the ion implantation layer is formed on, the ion implantation layer is deemed to disappear, as can be understood.
  • an oxide film may be formed without occurrence of the aforementioned phenomenon, by adopting a method of depositing an oxide film by accelerating and emitting ionized silicon and oxygen to the substrate on which the oxide film is to be formed while heating the substrate.
  • An oxide film of an SOI wafer is known to be formed by using a deposition technology, such as a chemical vapor deposition (CVD) method and an atomic layer deposition (ALD) method.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • the method of accelerating and emitting ionized silicon and oxygen while the temperature of the substrate is maintained at a high temperature is applied first time to form an oxide film of the bonded SOI wafer by the present inventor who has developed a dedicated device for this purpose.
  • An SOI wafer manufacturing process including:
  • a method of forming the oxide film in the second step is called the “ionization deposition method” in the present disclosure.
  • the first substrate is an epitaxial silicon wafer including a bulk silicon substrate and a silicon epitaxial layer formed on a surface of the bulk silicon substrate, and, in the fourth step, the bulk silicon substrate is removed to obtain the active layer formed by the silicon epitaxial layer.
  • the SOI wafer manufacturing process according to the present disclosure allows production of an SOI wafer having a high gettering ability and a small resistance variance in the thickness direction of the active layer, at high productivity.
  • An SOI wafer according to the present disclosure has a high gettering ability and a small resistance variance in the thickness direction of the active layer.
  • FIG. 1 is a schematic sectional view illustrating an SOI wafer manufacturing process according to the first embodiment of the present disclosure
  • FIG. 2 is a schematic sectional view illustrating an SOI wafer manufacturing process according to the second embodiment of the present disclosure
  • FIG. 3 is a schematic sectional view illustrating an SOI wafer manufacturing process according to the third embodiment of the present disclosure
  • FIG. 4 is a schematic sectional view illustrating an SOI wafer manufacturing process according to the fourth embodiment of the present disclosure
  • FIG. 5 is a schematic sectional view illustrating an SOI wafer manufacturing process according to the fifth embodiment of the present disclosure
  • FIG. 6 is a schematic sectional view illustrating an SOI wafer manufacturing process according to the sixth embodiment of the present disclosure.
  • FIG. 7 is a schematic sectional view illustrating an SOI wafer manufacturing process according to Comparative Example 2;
  • FIG. 8 is a schematic view illustrating a plasma ion emission device used to form an oxide film in embodiments of the present disclosure
  • FIG. 9 is a graph illustrating a concentration profile of an implanted element after an oxide film is formed in Comparative Example 1;
  • FIG. 10A is a graph illustrating a concentration profile of an implanted element after an oxide film is formed in Comparative Example 2.
  • FIG. 10B is a graph illustrating a resistivity distribution in an active layer after bonding in Comparative Example 2.
  • first embodiment firstly, light element ions are implanted to a surface of a substrate (i.e., the first substrate) 10 to be used as an active layer to form, in the substrate 10 to be used as the active layer, a modified layer 12 in which the light element ions are present in solid solution. Subsequently, an oxide film 16 is formed on the surface of the substrate 10 to be used as the active layer according to bonding thermal processing.
  • a substrate i.e., the first substrate
  • an oxide film 16 is formed on the surface of the substrate 10 to be used as the active layer according to bonding thermal processing.
  • the substrate 10 to be used as the active layer and a support substrate (i.e., the second substrate) 20 are bonded together in a manner such that the modified layer 12 and the oxide film 16 are located between the substrate 10 to be used as the active layer and the support substrate 20 , according to bonding thermal processing. Subsequently, the substrate 10 to be used as the active layer is thinned to obtain the active layer 22 .
  • the SOI wafer 100 includes the support substrate 20 , the oxide film 16 located above the support substrate 20 , and the active layer 22 located above the oxide film 16 , and, in the vicinity of an interface of the active layer 22 with respect to the oxide film 16 , the SOI wafer 100 also includes the modified layer 12 in which the light element is present in solid solution.
  • light element ions are implanted to a surface of the substrate (i.e., the first substrate) 10 to be used as the active layer to form, in the substrate 10 to be used as the active layer, the modified layer 12 in which the light element ions are present in solid solution. Furthermore, an oxide film 18 is formed on a surface of the support substrate (i.e., the second substrate) 20 according to the ionization deposition method.
  • the substrate 10 to be used as the active layer and the support substrate 20 are bonded together in a manner such that the modified layer 12 and the oxide film 18 are located between the substrate 10 to be used as the active layer and the support substrate 20 , according to bonding thermal processing. Subsequently, the substrate 10 to be used as the active layer is thinned to obtain the active layer 22 .
  • the SOI wafer 200 includes the support substrate 20 , the oxide film 18 located above the support substrate 20 , and the active layer 22 located above the oxide film 18 , and, in the vicinity of an interface of the active layer 22 with respect to the oxide film 18 , the SOI wafer 200 also includes the modified layer 12 in which the light element is present in solid solution.
  • the present embodiment light element ions are implanted to a surface of the support substrate (i.e., the second substrate) 20 to form, in the support substrate 20 , a modified layer 14 in which the light element ions are present in solid solution. Furthermore, the oxide film 16 is formed on a surface of the substrate (i.e., the first substrate) 10 to be used as the active layer by the ionization deposition method. After that, the substrate 10 to be used as the active layer and the support substrate 20 are bonded together in a manner such that the modified layer 14 and the oxide film 16 are located between the substrate 10 to be used as the active layer and the support substrate 20 , according to bonding thermal processing. Subsequently, the substrate 10 to be used as the active layer is thinned to obtain the active layer 22 .
  • the SOI wafer 300 includes the support substrate 20 , the oxide film 16 located above the support substrate 20 , and the active layer 22 located above the oxide film 16 , and, in the vicinity of an interface of the support substrate 20 with respect to the oxide film 16 , the SOI wafer 300 also includes the modified layer 14 in which the light element is present in solid solution.
  • the fourth embodiment of the present disclosure firstly, light element ions are implanted to a surface of the support substrate (i.e., the second substrate) 20 to form, in the support substrate 20 , a modified layer 14 in which the light element ions are present in solid solution. Subsequently, the oxide film 18 is formed on the surface of the support substrate 20 by the ionization deposition method. After that, the substrate (i.e., the first substrate) 10 to be used as the active layer and the support substrate 20 are bonded together in a manner such that the modified layer 14 and the oxide film 18 are located between the substrate 10 to be used as the active layer and the support substrate 20 , according to bonding thermal processing. Subsequently, the substrate 10 to be used as the active layer is thinned to obtain the active layer 22 .
  • the substrate 10 to be used as the active layer is thinned to obtain the active layer 22 .
  • the SOI wafer 400 includes the support substrate 20 , the oxide film 18 located above the support substrate 20 , and the active layer 22 located above the oxide film 18 , and, in the vicinity of an interface of the support substrate 20 with respect to the oxide film 18 , the SOI wafer 400 also includes the modified layer 14 in which the light element is present in solid solution.
  • the present embodiment firstly, light element ions are implanted to a surface of the support substrate (i.e., the second substrate) 20 to form, in the support substrate 20 , the modified layer 14 in which the light element ions are present in solid solution. Subsequently, the oxide film 18 is formed on the surface of the support substrate 20 by the ionization deposition method. Furthermore, the oxide film 16 is also formed on a surface of the substrate (the first substrate) 10 to be used as the active layer by the ionization deposition method.
  • the substrate 10 to be used as the active layer and the support substrate 20 are bonded together in a manner such that the modified layer 14 and the oxide films 16 and 18 are located between the substrate 10 to be used as the active layer and the support substrate 20 , according to bonding thermal processing. Subsequently, the substrate 10 to be used as the active layer is thinned to obtain the active layer 22 .
  • the SOI wafer 500 includes the support substrate 20 , an oxide film 24 located above the support substrate 20 , and the active layer 22 located above the oxide film 24 , and, in the vicinity of an interface of the support substrate 20 with respect to the oxide film 24 , the SOI wafer 500 also includes the modified layer 14 in which the light element is present in solid solution.
  • the oxide film 24 includes the oxide film 16 , formed on the substrate 10 to be used as the active layer, and the oxide film 18 , formed on the support substrate 20 , that are bonded together.
  • light element ions are implanted to a surface of the substrate (i.e., the first substrate) 10 to be used as the active layer to form, in the substrate 10 to be used as the active layer, the modified layer 12 in which the light element ions are present in solid solution.
  • the oxide film 16 is formed on the surface of the substrate 10 to be used as the active layer by the ionization deposition method.
  • light element ions are implanted to a surface of the support substrate (i.e., the second substrate) 20 to form, in the support substrate 20 , the modified layer 14 in which the light element ions are present in solid solution.
  • the oxide film 18 is formed on the surface of the support substrate 20 by the ionization deposition method.
  • the substrate 10 to be used as the active layer and the support substrate 20 are bonded together in a manner such that the modified layers 12 and 14 and the oxide films 16 and 18 are located between the substrate 10 to be used as the active layer and the support substrate 20 , according to bonding thermal processing.
  • the substrate 10 to be used as the active layer is thinned to obtain the active layer 22 .
  • the SOI wafer 600 includes the support substrate 20 , the oxide film 24 located above the support substrate 20 , and the active layer 22 located above the oxide film 24 , and, in the vicinity of an interface between the active layer 22 with respect to the oxide film 16 , the SOI wafer 600 also includes the modified layer 12 , and in the vicinity of an interface of the support substrate 20 with respect to the oxide film 24 , the SOI wafer 600 also includes the modified layer 14 in which the a light element is present in solid solution.
  • the oxide film 24 includes the oxide film 16 , formed on the substrate 10 to be used as the active layer, and the oxide film 18 , formed on the support substrate 20 , that are bonded together.
  • An element to be ionized may be any light element that contributes to gettering and preferably includes at least one selected from H, He, C, Ar, and Si. The reason is that these elements do not affect electric resistivity of an SOI wafer.
  • Ions to be implanted may be monomer or cluster ions.
  • cluster ions refer to a cluster, that is to say, an aggregate of a plurality of atoms or molecules that are ionized with a positive or a negative charge.
  • a cluster is a group of (normally, approximately from 2 to 2000) agglomerated atoms or molecules bonded to each other. From the viewpoint of achieving a higher gettering ability, cluster ions are preferably implanted.
  • the modified layer 12 by implanting ions to the substrate 10 to be used as the active layer.
  • the modified layer 12 is located closer to the active layer.
  • the presence of the modified layer itself might be a cause of leak failure.
  • any impurity elements that may pass an oxide film may be captured in the modified layer.
  • Conditions such as an accelerating voltage, a dose amount, and a cluster size during emission of cluster ions, applied for ion implantation may be any known or general conditions that may be adopted in consideration of gettering ability. Furthermore, any conventional monomer ion generation device and cluster ion generation device may be used.
  • the ionization deposition method is a method of depositing an oxide film by accelerating and emitting ionized silicon and oxygen to a substrate on which an oxide film is to be formed while heating the substrate.
  • the oxide film is deposited on the substrate by a combination of accelerating energy of the ionized element and thermal energy of the heated substrate.
  • the method provides an elaborate better-quality oxide film compared with a plasma deposition method only using accelerating energy of an ionized element for deposition and the CVD method only using thermal energy for deposition.
  • silicon and oxygen are ionized through plasma processing and accelerated onto the substrate, and thus, the oxide film is deposited on the substrate.
  • a plasma ion emission device 40 includes a plasma chamber 41 , a gas inlet 42 , a vacuum pump 43 , a pulse voltage application unit 44 , a wafer fixture 45 , and a heater 46 .
  • the substrate 10 to be used as the active layer and/or the support substrate 20 are/is mounted and fixed to the wafer fixture 45 disposed in the plasma chamber 41 .
  • the pressure inside the plasma chamber 41 is reduced by the vacuum pump 43 , and then, a source gas is introduced into the plasma chamber 41 through the gas inlet 42 .
  • a pulsed negative voltage is applied to the wafer fixture 45 (and to the substrates 10 and 20 ) by the pulse voltage application unit 44 .
  • source gas plasma including silicon and oxygen is generated, and source gas ions contained in the generated plasma are accelerated and emitted toward the substrates 10 and 20 .
  • the emitted silicon ions and oxygen ions react on the substrate, and the oxide film is deposited.
  • the source gas may include one, or two or more, of monosilane, dichlorosilane, trichlorosilane, trimethylsilane, silicone tetrachloride, or the like as a silicon source and may also include oxygen as an oxygen source.
  • the chamber pressure inside the plasma chamber 41 is 100 Pa or less. With a chamber pressure of more than 100 Pa, plasma is unstabilized, and the plasma state is not maintained.
  • the pulse voltage applied to the substrates 10 and 20 is set so that the accelerating energy of silicon and oxygen with respect to the surface of the substrate is from 10 eV to 1 keV.
  • the accelerating energy of silicon and oxygen with respect to the surface of the substrate is from 10 eV to 1 keV.
  • an accelerating energy of less than 10 eV bonding energy between silicon and oxygen is insufficient, and this might hinder formation of the oxide film.
  • an accelerating energy of more than 1 keV silicon and oxygen are implanted from the surface to the inside of the substrate, and this hinders formation of the oxide film.
  • the frequency of the pulse voltage determines the number of times ions are emitted to the substrates 10 and 20 .
  • the frequency of the pulse voltage is preferably from 10 Hz to 50 kHz.
  • a frequency of 10 Hz or more variation in ion emission is absorbed, and this stabilizes the amount of emitted ions.
  • a frequency of 50 kHz or less glow discharge plasma is formed stably.
  • the pulse width of the pulse voltage determines a time period over which ions are emitted to the substrates 10 and 20 .
  • the pulse width is preferably from 1 ⁇ second (microsecond) to 10 m seconds (miliseconds). With a pulse width of 1 ⁇ second or more, ions are emitted to the substrates 10 and 20 stably. With a pulse width of 10 m seconds or less, glow discharge plasma is formed stably.
  • the accelerating energy of ions is controlled mainly by the applied voltage. Furthermore, as supplementary control, resistance between the wafer and the pulse application unit (e.g., resistance of the fixture, and resistance between the fixture and the pulse application unit), and timing of voltage application may be adjusted, and by doing so, the distance between a plasma region and the wafer may be adjusted.
  • resistance between the wafer and the pulse application unit e.g., resistance of the fixture, and resistance between the fixture and the pulse application unit
  • timing of voltage application may be adjusted, and by doing so, the distance between a plasma region and the wafer may be adjusted.
  • the temperature of a substrate is preferably 500° C. or more.
  • the temperature of the substrates is set to be a low temperature of from approximately 100° C. to 300° C., and accordingly, an elaborate oxide film is hardly obtained, and deterioration in quality of the oxide film and peeling of the film at the time of bonding thermal processing are more likely to occur compared with cases according to the thermal oxidization method.
  • an elaborate good-quality oxide film may be formed. This in turn improves pressure-resistance characteristics of the oxide film.
  • a result of TZDB measurement performed under a judgement current of 1 ⁇ 10 ⁇ 4 A/cm 2 may be 8 MV/cm 2 or more.
  • the temperature of the substrate is preferably 900° C. or less.
  • a dopant contained in the active layer is prevented from being diffused to the oxide film, and thus, a decrease in dopant concentration in the vicinity of the active layer with respect to the oxide film is prevented.
  • an element implanted in a modified layer is prevented from being diffused through the active layer, and thus, a non-uniform concentration profile of the implanted element in the thickness direction of the active layer and a resulting decrease in gettering ability are prevented.
  • Forming an oxide film according to the ionization deposition method described above provides the following operational advantages. Firstly, since, unlike the thermal oxidization method, the ionization deposition method does not consume silicon in the superficial portion of a substrate, the problem described in the findings (A) that a modified layer might disappear is avoided. Accordingly, an SOI wafer having a high gettering ability may be obtained. Secondly, unlike the thermal oxidization method, the ionization deposition method does not create a layer with variable resistance due to the fixed charge, in the vicinity of a substrate with respect to the oxide film, and therefore, the problem described in the findings (B) is avoided. Accordingly, an SOI wafer having a small resistance variance in the thickness direction of the active layer may be obtained.
  • the thermal oxidization method takes 1 or more months to form an oxide film of from 5 to 10 ⁇ m
  • the ionization deposition method is much faster in film formation rate, taking approximately 3 hours to form an oxide film of the same thickness. Accordingly, productivity is improved.
  • the ionization deposition method is very effective for forming a thick oxide film.
  • An oxide film may be formed on one or both of the substrate 10 to be used as the active layer and the support substrate 20 . From the viewpoint of obtaining an overall thick oxide film within a short period of time, an oxide film is preferably formed on both the substrate 10 to be used as the active layer and the support substrate 20 .
  • the substrate 10 to be used as the active layer is required to be highly pure since it is used as the device region. From the viewpoint of reducing the chance for the substrate 10 to be used as the active layer to be exposed to impurity contamination to the minimum possible, an oxide film is preferably formed only on the support substrate 20 which is not used as the device region, so that the influence of impurity contamination from the device may be eliminated to the minimum possible level.
  • bonding thermal processing is performed in the state where a surface to be bonded of the substrate 10 to be used as the active layer is in contact with a surface to be bonded of the support substrate 20 .
  • Bonding thermal processing allows production of an SOI wafer with excellent bonding strength.
  • Bonding thermal processing is preferably performed under conditions that the temperatures of the substrates are from 400° C. to 1200° C. for a time period of from 10 minutes to 6 hours in an oxidizing gas atmosphere or an inert gas atmosphere. When the temperatures of the substrates are less than 400° C., bonding strength might not be achieved satisfactorily, and when the temperatures of the substrates are more than 1200° C., slippage might occur.
  • the temperatures of the substrates are preferably 900° C. or less. Furthermore, in cases where carbon is ion implanted to the substrate to be used as the active layer to form a modified layer, depending on the amount implanted, excessive oxygen donors might be generated due to thermal diffusion caused by bonding thermal processing and might generate the resistance variance in the modified layer. In these cases, therefore, the temperatures of the substrates are preferably 600° C. or less.
  • a thinning step preferably, well-known plane-polishing and mirror-polishing methods may be used. Other thinning technologies, such as a well-known smart-cut method, may also be used in the thinning step.
  • a surface side of the substrate 10 to be used as the active layer is subject to grinding processing to be thinned, and then, the surface is mirror-polished to obtain an SOI wafer having the active layer of a desired thickness.
  • a single crystal silicon wafer made of silicon single crystal may be used as the support substrate 20 .
  • the single crystal silicon wafer may be the one obtained by slicing, by a wire saw or the like, a single crystal silicon ingot grown by the Czochralski (CZ) method or the floating zone (FZ) melting method.
  • CZ Czochralski
  • FZ floating zone
  • carbon and/or nitrogen may be added.
  • any impurity may be added to make the substrate n-type or p-type.
  • the substrate 10 to be used as the active layer is a wafer to be used as a device active layer, and similarly to the support substrate 20 , a single crystal silicon wafer made of silicon single crystal may be used.
  • the substrate 10 to be used as the active layer it is also possible to use an epitaxial silicon wafer including a bulk silicon substrate and a silicon epitaxial layer formed on a surface of the bulk silicon substrate.
  • the silicon epitaxial layer 14 may be formed by the CVD method under common conditions, and the thickness of the silicon epitaxial layer 14 is preferably in the range of from 0.1 to 20 ⁇ m, more preferably in the range of from 0.2 to 5 ⁇ m.
  • the substrate 10 to be used as the active layer is the epitaxial silicon wafer and where a modified layer is formed in the epitaxial silicon wafer by ion implantation, and/or, an oxide film is formed on the epitaxial silicon wafer by the ionization deposition method, the modified layer and/or the oxide film are/is formed in/on the silicon epitaxial layer.
  • the fourth step the step of thinning the substrate to be used as the active layer
  • the bulk silicon substrate is removed.
  • the active layer 22 may be formed by the silicon epitaxial layer, and crystal quality of the active layer is improved. In applications where the entire region of the active layer is used as the device region, by making the active layer entirely formed by the epitaxial layer, crystal quality of the active layer is improved.
  • an epitaxial layer is formed on the surface of the active layer 22 after bonding, oxygen contained in the active layer 22 is diffused to the epitaxial layer due to high-temperature thermal processing during epitaxial growth.
  • oxygen donors might be generated in the epitaxial layer and adversely affect resistivity in the epitaxial layer.
  • the surface of the silicon epitaxial layer is mirror-polished before the third step (the bonding step), since, by doing so, bonding strength may be reinforced.
  • the thickness of the silicon epitaxial layer is preferably determined in consideration of a desired thickness of the active layer and the thickness of an oxygen diffusion region formed by oxygen diffusion from the bulk silicon substrate into the silicon epitaxial layer, and in the fourth step (the thinning step), the oxygen diffusion region in the silicon epitaxial layer is preferably also removed.
  • the active layer of 10 ⁇ m is required and where the oxygen diffusion region with a thickness of 1 ⁇ m is generated within the epitaxial layer in the process of epitaxial growth.
  • the epitaxial layer of 11 ⁇ m may be formed, and after bonding, may be thinned to remove the oxygen diffusion region. By doing so, the active layer without the oxygen diffusion region is obtained.
  • a low oxygen (9 ⁇ 10 17 atoms/cm 3 or less) silicon wafer and/or a high resistance (100 ⁇ cm or more) silicon wafer are/is preferably used.
  • Oxygen contained in the bulk silicon substrate is prevented from being diffused to the epitaxial layer due to high-temperature thermal processing during epitaxial growth.
  • high resistance prevents a resistance variance occurring in the epitaxial layer due to a dopant contained in the bulk silicon substrate being diffused to the epitaxial layer.
  • SOI wafers of Examples 1 to 7 and Comparative Examples 1 to 4 were prepared.
  • substrates to be used as the active layers as illustrated in Table 1, single crystal silicon wafers (which are each represented as “Si substrate” in Table 1) and epitaxial silicon wafers (which are each represented as “EP-Si” in Table 1) were prepared.
  • support substrates as illustrated in Table 1, single crystal silicon wafers (which are each represented by “Si substrate” in Table 1) were prepared.
  • Phosphor was used as a dopant of the substrates, and dopant concentrations are illustrated in Table 1.
  • Ar monomer ions were implanted to a surface of at least one of the substrate to be used as the active layer and the support substrate (which is represented as “implanted site” in Table 1) at the corresponding accelerating voltage and dose amount illustrated in Table 1.
  • an oxide film of the corresponding thickness illustrated in Table 1 was formed on a surface of at least one of the substrate to be used as the active layer and the support substrate (which is represented as “formed site” in Table 1).
  • the temperature of the substrates in the thermal oxidization method was 1000° C.
  • the oxide film was deposited according to the aforementioned method by using the device illustrated in FIG. 8 , and at this time, the temperature of the substrates was 500° C.
  • Examples 1 to 5 used 50 sccm of trimethylsilane, 200 sccm of oxygen, a chamber pressure of 10 Pa, an accelerating energy of 150 eV, a frequency of 25 kHz, and a pulse width of 1.5 ⁇ 10 ⁇ 3 seconds
  • Examples 6 and 7 used 45 sccm of trimethylsilane, 150 sccm of oxygen, a chamber pressure of 8 Pa, an accelerating energy of 120 eV, a frequency of 25 kHz, and a pulse width of 1.0 ⁇ 10 ⁇ 3 seconds.
  • the substrate to be used as the active layer and the support substrate were bonded according to bonding thermal processing.
  • the temperatures of the substrates were set to 800° C. for 2 hours and subsequently set to 1150° C. for 1 hour.
  • each substrate to be used as the active layer was subject to grinding processing to be thinned, and then, the surface was mirror-polished to obtain the SOI wafers having the active layers of a thickness illustrated in Table 1.
  • a surface of the active layer of the SOI wafer according to each of Comparative Examples and Examples was intentionally contaminated with a Ni contaminated liquid (1.0 ⁇ 10 12 /cm 2 ) according to the spin coat contamination method, and subsequently, was subject to thermal processing at 900° C. for 1 hour under a nitrogen atmosphere. After that, the sample was immersed in a Wright solution for 3 minutes, and then, the presence of pits (Ni silicide pits) were observed by an optical microscope. Table 1 shows a result of the evaluation.
  • resistivity in the active layer of the SOI wafer was measured by the spread resistance (SR) profiling method, and non-uniformity, that is, ((the maximum value ⁇ the minimum value)/(the minimum value) ⁇ 100) (%), in resistivity distribution in the thickness direction of the substrate to be used as the active layer was calculated.
  • the result is shown in the column “resistance variation” in Table 1.
  • the resistivity distribution of Comparative Example 2 is illustrated in FIG. 10B .
  • Comparative Example 2 is an SOI wafer manufactured according to the flow illustrated in FIG. 7 . That is to say, light element ions were implanted to a surface of the substrate 10 to be used as the active layer to form the modified layer 12 in the substrate 10 to be used as the active layer, and the oxide film 18 was formed on surfaces of the support substrate 20 according to the thermal oxidization method, and subsequently, the substrate 10 to be used as the active layer and the support substrate 20 were bonded according to bonding thermal processing, and then, the substrate 10 to be used as the active layer was thinned to obtain the active layer 22 . In this case, as illustrated in FIG. 10A , the peak of the implanted element did not disappear, and pits were not observed on a surface of the active layer.
  • a layer 16 with variable resistance is formed in the vicinity of the support substrate with respect to the oxide film due to the thermal oxidization method, and after bonding, a layer 18 with variable resistance is also formed in the vicinity of the substrate to be used as the active layer with respect to the oxide film. Results that support the above fact are shown as resistance variations illustrated in FIG. 10B and in Table 1.
  • a time zero dielectric breakdown (TZDB) measurement was conducted on the SOI wafer according to Example 6 under a judgement current of 1 ⁇ 10 ⁇ 4 A/cm 2 .
  • the active layer formed above an oxide film was processed into an island shape with 1.8 mm sides by photolithography and etching processing, and, with the processed island serving as an electrode and with the support substrate side being set to zero (0) V, a voltage was applied to the electrode by increasing the voltage from 0 V by increments of 0.1 V step.
  • a current value per unit area obtained by dividing a measured current value by an electrode area was defined as the judgment current.
  • SOI wafers that are the same as Example 6 except for that the temperatures of the substrates during the formation of the oxide films were changed to 300° C., 400° C., 800° C., 900° C., and 1000° C. were prepared, and the pressure-resistant characteristics of the oxide films were evaluated similarly. Table 2 shows a result of the evaluation.
  • the present disclosure provides an SOI wafer manufacturing process that allows production of an SOI wafer having a high gettering ability and a small resistance variance in the thickness direction of the active layer, at high productivity.

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