US9853141B2 - Semiconductor device with front and rear surface electrodes on a substrate having element and circumferential regions, an insulating gate type switching element in the element region being configured to switch between the front and rear surface electrodes - Google Patents

Semiconductor device with front and rear surface electrodes on a substrate having element and circumferential regions, an insulating gate type switching element in the element region being configured to switch between the front and rear surface electrodes Download PDF

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US9853141B2
US9853141B2 US15/107,132 US201415107132A US9853141B2 US 9853141 B2 US9853141 B2 US 9853141B2 US 201415107132 A US201415107132 A US 201415107132A US 9853141 B2 US9853141 B2 US 9853141B2
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region
trench
gate
semiconductor substrate
front surface
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US20170040446A1 (en
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Jun Saito
Hirokazu Fujiwara
Tomoharu IKEDA
Yukihiko Watanabe
Toshimasa Yamamoto
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Denso Corp
Toyota Motor Corp
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Denso Corp
Toyota Motor Corp
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Definitions

  • the technique disclosed in this description relates to a semiconductor device.
  • Patent Literature 1 discloses a semiconductor device including a cell region in which a MOS structure is provided, and a circumferential region on a periphery of the cell region. A plurality of trenches is provided in the circumferential region so as to circumscribe the cell region, and an insulating layer is filled in each trench. A p-type bottom-surface surrounding region is provided at a lower end of each trench in the circumferential region.
  • a MOSFET When a MOSFET is turned off, a depletion layer extends from the cell region to the circumferential region. At this occasion, the respective bottom-surface surrounding regions enhance the extension of the depletion layer. Due to this, a high voltage resistance can be obtained by this structure.
  • a semiconductor device disclosed herein comprises a semiconductor substrate; a front surface electrode provided on a front surface of the semiconductor substrate; and a rear surface electrode provided on a rear surface of the semiconductor substrate.
  • the semiconductor substrate comprises: an element region in which an insulated gate type switching element configured to switch between the front surface electrode and the rear surface electrode is provided, and a circumferential region adjacent to the element region.
  • the insulated gate type switching element comprises: a first region of a first conductivity type connected to the front surface electrode; a second region of a second conductivity type connected to the front surface electrode and being in contact with the first region; a third region of the first conductivity type provided under the second region and separated from the first region by the second region; a gate insulating film being in contact with the second region; and a gate electrode facing the second region via the gate insulating film.
  • a first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench.
  • a fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench.
  • a fifth region of the first conductivity type continuous from the third region is provided under the fourth region.
  • the first trench and the second trench are provided in the circumferential region, and the fourth region is provided across the bottom surface of the first trench and the bottom surface of the second trench.
  • a depletion layer extends from the element region to the circumferential region.
  • the depletion layer reaches the fourth region, the depletion layer extends from an entirety of the fourth region into the fifth region. That is, a region under the plurality of trenches is depleted at once. Due to this, the depletion layer can quickly be expanded in the circumferential region. Due to this, this semiconductor device has a high voltage resistance.
  • a low area density region may be provided in a region within the fourth region and between the first trench and the second trench.
  • An area density of second conductivity type impurities measured along a thickness direction of the semiconductor substrate may be lower in the low area density region than in a region within the fourth region and under the first trench and in a region within the fourth region and under the second trench.
  • the region under the first trench may be separated from the region under the second trench by the low area density region.
  • the aforementioned “region between the first trench and the second trench” refers to the fourth region that is positioned between the first trench and the second trench when the semiconductor substrate is seen in a plan view along its thickness direction.
  • the low area density region can be depleted.
  • the fourth region on a first trench side is separated from the fourth region on a second trench side by the depletion layer. Due to this, a potential difference can be generated within the fourth region, and a potential can be distributed in the circumferential region more evenly. Due to this, such a semiconductor device has even a higher voltage resistance.
  • the semiconductor substrate may be configured of SiC, and the area density in the low area density region may be lower than 3.2 ⁇ 10 13 cm ⁇ 2 .
  • the semiconductor substrate may be configured of Si, and the area density in the low area density region may be lower than 2.0 ⁇ 10 12 cm ⁇ 2 .
  • the low area density region can be depleted.
  • the semiconductor substrate may be configured of SIC, and the area density in the region under the first trench and the area density in the region under the second trench may be equal to or higher than 1.5 ⁇ 10 13 cm ⁇ 2 .
  • the semiconductor substrate may be configured of Si, and the area density in the region under the first trench and the area density in the region under the second trench are equal to or higher than 1.9 ⁇ 10 19 cm ⁇ 2 .
  • the region under the first trench and the second trench can be suppressed from being depleted. Due to this, upon when the insulated gate type switching element turns off, a generation of a high electric field in a vicinity of a lower end of each trench can be suppressed.
  • the fourth region may contain B and Al.
  • a density ratio of B with respect to Al may become larger at a position farther away from the bottom surface of the first trench.
  • a density ratio of B with respect to Al may become larger at a position farther away from the bottom surface of the second trench.
  • a second conductivity type impurity concentration of the fourth region under the first trench and the second trench can be made high, and a second conductivity type impurity concentration of the fourth region between the first trench and the second trench can be made low.
  • a gate trench may be provided in the front surface of the semiconductor substrate in the element region.
  • a gate insulating film and a gate electrode may be provided in the gate trench.
  • a sixth region of the second conductivity type including Al may be provided in a range in the semiconductor substrate. The range may include a bottom surface of the gate trench.
  • the sixth region having a high second conductivity type impurity concentration can be provided in the range including the bottom surface of the gate trench. Due to this, a generation of a high electric field in a vicinity of a lower end of the gate trench can be suppressed.
  • FIG. 1 is an upper view of a semiconductor device 10 (a diagram that omits depiction of an electrode and insulating films on a front surface);
  • FIG. 2 is a vertical cross-sectional view of the semiconductor device 10 along a line II-II in FIG. 1 ;
  • FIG. 3 is an enlarged view of a p-type region 56 ;
  • FIG. 4 is a graph showing a relationship between an area density and a leak current.
  • FIG. 5 is an enlarged view of a p-type region 56 of a second embodiment.
  • a semiconductor device 10 shown in FIG. 1 comprises a semiconductor substrate 12 configured of SIC.
  • the semiconductor substrate 12 comprises a cell region 20 and a circumferential region 50 .
  • the cell region 20 includes a MOSFET provided therein.
  • the circumferential region 50 is a region between the cell region 20 and end faces 12 a of the semiconductor substrate 12 .
  • a front surface electrode 14 and an insulating film 16 are provided on a front surface of the semiconductor substrate 12 .
  • the insulating film 16 covers the front surface of the semiconductor substrate 12 within the circumferential region 50 .
  • the front surface electrode 14 is in contact with the semiconductor substrate 12 within the cell region 20 .
  • a region under a contact region where the front surface electrode 14 is in contact with the semiconductor substrate 12 is the cell region 20
  • a region on an outer circumferential side (end face 12 a side) than the contact region is the circumferential region 50 .
  • a rear surface electrode 18 is provided on a rear surface of the semiconductor substrate 12 .
  • the rear surface electrode 18 covers substantially an entirety of the rear surface of the semiconductor substrate 12 .
  • Source regions 22 , body contact regions 24 , a body region 26 , a drift region 28 , a drain region 30 , p-type floating regions 32 , and gate trenches 34 are provided in the cell region 20 .
  • the source regions 22 are n-type regions containing n-type impurities at a high concentration.
  • the source regions 22 are provided within ranges that are exposed on an upper surface of the semiconductor substrate 12 .
  • the source regions 22 make an ohmic connection to the front surface electrode 14 .
  • the body contact regions 24 are a p-type region containing p-type impurities at a high concentration.
  • the body contact regions 24 are provided to be exposed on the upper surface of the semiconductor substrate 12 at a position where the source regions 22 are not provided.
  • the body contact regions 24 make an ohmic connection to the front surface electrode 14 .
  • the body region 26 is a p-type region containing p-type impurities at a low concentration.
  • the p-type impurity concentration of the body region 26 is lower than the p-type impurity concentration of the body contact regions 24 .
  • the body region 26 is provided under the source regions 22 and the body contact regions 24 , and is in contact with these regions.
  • the drift region 28 is an n-type region containing n-type impurities at a low concentration.
  • the n-type impurity concentration of the drift region 28 is lower than the n-type impurity concentration of the source regions 22 .
  • the drift region 28 is provided under the body region 26 .
  • the drift region 28 is in contact with the body region 26 , and is separated from the source regions 22 by the body region 26 .
  • the drain region 30 is an n-type region containing n-type impurities at a high concentration.
  • the n-type impurity concentration of the drain region 30 is higher than the n-type impurity concentration of the drift region 28 .
  • the drain region 30 is provided under the drift region 28 .
  • the drain region 30 is in contact with the drift region 28 , and is separated from the body region 26 by the drift region 28 .
  • the drain region 30 is provided in a range that is exposed to a lower surface of the semiconductor substrate 12 .
  • the drain region 30 makes an ohmic connection to the rear surface electrode 18 .
  • the plurality of gate trenches 34 is provided in the upper surface of the semiconductor substrate 12 within the cell region 20 .
  • Each of the gate trenches 34 extends straight and parallel to each other in the front surface of the semiconductor substrate 12 .
  • Each of the gate trenches 34 is configured to penetrate its corresponding source regions 22 and the body region 26 , and reach the drift region 28 .
  • a bottom insulating layer 34 a In each of the gate trenches 34 , a bottom insulating layer 34 a , a gate insulating film 34 b , and a gate electrode 34 c are provided.
  • the bottom insulating layers 34 a are thick insulating layers provided respectively at bottom portions of the gate trenches 34 .
  • each gate trench 34 above the bottom insulating layer 34 a is covered by the gate insulating film 34 b .
  • the gate electrodes 34 c are provided inside the gate trenches 34 above the bottom insulating layers 34 a .
  • the gate electrodes 34 c face the source regions 22 , the body region 26 , and the drift region 28 via the gate insulating films 34 b .
  • the gate electrodes 34 c are insulated from the semiconductor substrate 12 by the gate insulating films 34 b and bottom insulating layers 34 a .
  • An upper surface of each gate electrode 34 c is covered by an insulating layer 34 d .
  • the gate electrodes 34 c are insulated from the front surface electrode 14 by the insulating layers 34 d.
  • the p-type floating regions 32 are provided in ranges within the semiconductor substrate 12 that are respectively in contact with bottom surfaces of the gate trenches 34 . Peripheries of the p-type floating regions 32 are surrounded by the drift region 28 . The p-type floating regions 32 are separated from each other by the drift region 28 .
  • the aforementioned body region 26 , drift region 28 , and drain region 30 extend to the circumferential region 50 .
  • the drift region 28 and the drain region 30 extend to end faces 12 a of the semiconductor substrate 12 .
  • the body region 26 terminates within the circumferential region 50 .
  • the drift region 28 is provided between the body region 26 and the end faces 12 a of the semiconductor substrate 12 .
  • a plurality of circumferential trenches 54 is provided in the upper surface of the semiconductor substrate 12 in the circumferential region 50 .
  • the circumferential trenches 54 are configured to penetrate the body region 26 and reach the drift region 28 .
  • An insulating layer 53 is provided in each of the circumferential trenches 54 .
  • the circumferential trenches 54 are provided in ring shapes that circumscribe the cell region 20 when the semiconductor substrate 12 is seen from above.
  • the body region 26 in the circumferential region 50 is separated from the body region 26 in the cell region 20 .
  • Each of the circumferential trenches 54 is separated from each other with intervals in between.
  • P-type regions 56 are provided in ranges within the semiconductor substrate 12 that are in contact with bottom surfaces of the circumferential trenches 54 .
  • the bottom surface regions 56 are respectively provided along the circumferential trenches 54 so as to cover entireties of the bottom surfaces of the circumferential trenches 54 .
  • Each of the p-type regions 56 is connected to the other adjacent p-type regions 56 .
  • FIG. 3 shows an enlarged view of the respective p-type regions 56 in FIG. 2 .
  • each region 56 b positioned between two circumferential trenches 54 has a higher area density of p-type impurities in a thickness direction than each region 56 a under each of the circumferential trenches 54 within the p-type regions 56 .
  • the area density in the regions 56 a is a value that integrated the p-type impurity concentration of the regions 56 a along the thickness direction of the semiconductor substrate 12 (that is, a value that integrated the p-type impurity concentration along a line A-A in FIG.
  • the area density of the regions 56 b is a value that integrated the p-type impurity concentration of the regions 56 b along the thickness direction of the semiconductor substrate 12 (that is, a value that integrated the p-type impurity concentration along a line B-B in FIG. 3 ).
  • the regions 56 b will be termed low area density regions, and the regions 56 a will be termed high area density regions.
  • a voltage that brings the rear surface electrode 18 to be charged positively is applied between the rear surface electrode 18 and the front surface electrode 14 .
  • the MOSFET in the cell region 20 turns on by a gate-on voltage being applied to the gate electrodes 34 c . That is, channels are generated in the body region 26 at positions facing the gate electrodes 34 c , and electrons flow from the front surface electrode 14 toward the rear surface electrode 18 through the source regions 22 , the channels, the drift region 28 , and the drain region 30 .
  • the channels disappear and the MOSFET turns off.
  • a depletion layer extends from a pn junction at a boundary between the body region 26 and the drift region 28 into the drift region 28 .
  • the depletion layer reaches the p-type floating regions 32 in the cell region 20 , the depletion layer extends from the p-type floating regions 32 into the drift region 28 as well. Due to this, the drift region 28 between pairs of p-type floating regions 32 is depleted effectively. Accordingly, a high voltage resistance in the cell region 20 is thereby facilitated.
  • the aforementioned depletion layer extending from the pn junction reaches the p-type region 56 under the circumferential trench 54 positioned closest to the cell region 20 side. Then, due to all of the p-type regions 56 being connected, the depletion layer extends from all of the p-type regions 56 into the drift region 28 . Accordingly, in the semiconductor device 10 of the present embodiment, the depletion layer extends into the drift region 28 substantially simultaneously from the p-type regions 56 under the respective circumferential trenches 54 , so the expansion of the depletion layer in the circumferential region 50 is extremely fast.
  • the depletion layer extends within the p-type regions 56 as well.
  • the respective low area density regions 56 b are depleted over their entireties in the thickness direction, while in the respective high area density regions 56 a , the depletion layer does not extend to regions 56 c shown by dotted lines in FIG. 3 (regions 56 c covering the bottom surfaces of the circumferential trenches 54 ).
  • regions 56 c shown by dotted lines in FIG. 3 (regions 56 c covering the bottom surfaces of the circumferential trenches 54 ).
  • the area density is high in the high area density regions 56 a . Accordingly, due to the p-type regions 56 c at the lower ends of the circumferential trenches 54 not being depleted, a concentration of an electric field in vicinities of the lower ends of the circumferential trenches 54 is suppressed.
  • the p-type regions 56 c under the circumferential trenches 54 are separated from each other by the depletion layer. Due to this, a potential difference is generated between each circumferential trench 54 . Due to this, a potential can be distributed evenly within the circumferential region 50 .
  • the depletion layer can be expanded quickly within the circumferential region 50 since the depletion layer expands from the entireties of the p-type regions 56 in the circumferential region 50 . Further, since the p-type regions 56 c under the circumferential trenches 54 are separated from each other when they are depleted, the potential can be distributed among the circumferential trenches 54 . Further, even in the event where the depletion has expanded within the circumferential region 50 , the electric field concentration at the lower ends of the circumferential trenches 54 can be suppressed due to the p-type regions 56 c remaining under the circumferential trenches 54 . Due to this, this semiconductor device 10 has a high voltage resistance.
  • the area density of the low area density regions 56 b is preferably less than 3.2 ⁇ 10 13 cm ⁇ 2 .
  • a voltage required for its depletion would exceed an avalanche voltage resistance, thus it cannot be depleted.
  • the area density is lower than this value, it is possible to deplete the low area density regions 56 b over their entireties in the thickness direction by adjusting the voltage, and the aforementioned effect can be achieved.
  • the semiconductor substrate 12 is Si
  • the low area density regions 56 b can be depleted completely by setting the area density to be less than 2.0 ⁇ 10 12 cm ⁇ 2 .
  • the area density of the high area density regions 56 a is preferably equal to or higher than 1.5 ⁇ 10 13 cm ⁇ 2 .
  • FIG. 4 is a graph showing a relationship between the area density of the high area density regions 56 a and a leak current that flows in vicinities of the circumferential trenches 54 . With an application voltage at practical level, as shown, the leak current can be minimized when the area density is equal to or higher than a predetermined threshold. In a case where the semiconductor substrate 12 is configured of SiC, this threshold is 1.5 ⁇ 10 13 cm ⁇ 2 .
  • the area density of the high area density regions 56 a is preferably 1.5 ⁇ 10 13 cm ⁇ 2 .
  • the area density of the high area density regions 56 a may be set to equal to or higher than 3.2 ⁇ 10 13 cm ⁇ 2 .
  • the threshold is 1.9 ⁇ 10 19 cm ⁇ 2 .
  • the area density of the high area density regions 56 a is preferably equal to or higher than 1.9 ⁇ 10 19 cm ⁇ 2 .
  • the area density of the high area density regions 56 a may be set to equal to or higher than 2.0 ⁇ 10 12 cm ⁇ 2 .
  • the aforementioned p-type regions 56 can be formed as follows. Firstly, the circumferential trenches 54 are formed in the circumferential region 50 . Then, p-type impurities (for example, B (boron)) are implanted to the bottom surfaces of the circumferential trenches 54 , after which the boron is diffused.
  • p-type impurities for example, B (boron)
  • the concentration of the boron becomes high in the vicinities of the lower ends of the trenches, and the concentration of the boron becomes lower at positions that are more apart from the lower ends of the trenches.
  • the low area density regions 56 b and the high area density regions 56 a can be distributed as aforementioned.
  • the p-type impurities may be implanted again to the bottom surfaces of the trenches after the diffusion step of the p-type impurities. According to this method, the p-type impurity concentration in the vicinities of the lower ends of the trenches can further be increased.
  • the p-type regions 56 contain Al (aluminum) and B as their p-type impurities. Ranges in which Al is distributed is primarily in the vicinities of the lower ends of the circumferential trenches 54 . B is widely distributed from the lower ends of the circumferential trenches 54 to their peripheries. Due to this, in the p-type regions 56 , a density ratio of Al is high in the vicinities of the lower ends of the circumferential trenches 54 , and a density ratio of B with respect to Al increases at positions that are more apart from the lower ends of the circumferential trenches 54 .
  • the area density of the low area density regions 56 b is lower than the area density of the high area density regions 56 a .
  • the floating regions 32 in the cell region 20 contain Al as their p-type impurities.
  • the p-type regions 56 and the floating regions 32 in the semiconductor device 200 of the second embodiment are formed as follows. Firstly, the gate trenches 34 and the circumferential trenches 54 are formed on the front surface of the semiconductor substrate 12 . These may be formed simultaneously, or may be formed separately. Next, Al is implanted in the bottom surfaces of the gate trenches 34 and the bottom surfaces of the circumferential trenches 54 . Then, B is implanted in the bottom surfaces of the circumferential trenches 54 . This implantation of B is performed so that B is not implanted to the bottom surfaces of the gate trenches 34 . Thereafter, the semiconductor substrate 12 is heated to diffuse Al and B that have been implanted.
  • each of the floating regions 32 is formed in a state of being separated from other floating regions 32 .
  • each Al distributed region 56 d containing large quantity of Al within the p-type regions 56 is formed in a state of being separated from other Al distributed regions 56 d .
  • the Al concentration in the floating regions 32 and the Al distributed regions 56 d is high.
  • B is widely diffused in the peripheries of the bottom surfaces of the circumferential trenches 54 after the diffusion step. Due to this, widely distributed B enables the p-type regions 56 under the respective circumferential trenches 54 to connect to their adjacent other p-type regions 56 . Thus, as shown in FIG. 5 , the p-type regions 56 are thereby formed.
  • the semiconductor device 200 of the second embodiment operates substantially similar to the semiconductor device 10 of the first embodiment. That is, upon when the MOSFET is off, the depletion layer extends in the drift region 28 from the entireties of the p-type regions 56 . At this occasion, the low area density regions 56 b within the p-type regions 56 are depleted over their entireties in the thickness direction. Due to this, the respective high area density regions 56 a (that is, Al distributed regions 56 d ) are separated from each other, and the potential distribution of the circumferential region 50 is made uniform.
  • the semiconductor device 200 of the second embodiment also has a high voltage resistance.
  • the circumferential trenches 54 are formed in ring shapes that circumscribe the periphery of the cell region 20 , however, the circumferential trenches 54 do not necessarily need to be in such a ring shape.
  • the circumferential trenches 54 may be provided only partially in the circumferential region 50 at portions where voltage resistance becomes problematic.
  • the circumferential trenches 54 are provided between the cell region 20 and the end faces 12 a of the semiconductor substrate 12 , however, they may be provided at other locations.
  • a circumferential trench 54 may be provided between two element regions 20 .
  • the MOSFET is provided in the cell region 20 , however, an IGBT may be provided.
  • the body region 26 extends into the circumferential region 50 , however, the body region 26 may not be provided in the circumferential region 50 .
  • the p-type floating regions 32 are provided at the lower ends of the gate trenches 34 , however, p-type regions connected to a predetermined potential may be provided instead of the p-type floating regions 32 .

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JP6946824B2 (ja) * 2017-07-28 2021-10-06 富士電機株式会社 半導体装置および半導体装置の製造方法
CN109346467A (zh) * 2018-08-17 2019-02-15 矽力杰半导体技术(杭州)有限公司 半导体结构、驱动芯片和半导体结构的制造方法
WO2022158053A1 (ja) * 2021-01-25 2022-07-28 富士電機株式会社 半導体装置
CN112928156B (zh) * 2021-04-07 2022-04-12 四川大学 一种浮空p柱的逆导型槽栅超结IGBT
KR102407121B1 (ko) * 2022-03-30 2022-06-10 (주) 트리노테크놀로지 감소된 손실을 가지는 전력 반도체 장치 및 그 제조 방법

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US20170040446A1 (en) 2017-02-09
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