US9728147B2 - GOA circuit of LTPS semiconductor TFT - Google Patents

GOA circuit of LTPS semiconductor TFT Download PDF

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US9728147B2
US9728147B2 US14/422,700 US201514422700A US9728147B2 US 9728147 B2 US9728147 B2 US 9728147B2 US 201514422700 A US201514422700 A US 201514422700A US 9728147 B2 US9728147 B2 US 9728147B2
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type transistor
electrically coupled
source
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gate
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US20160343323A1 (en
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Juncheng Xiao
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0417—Special arrangements specific to the use of low carrier mobility technology
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0291—Details of output amplifiers or buffers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving

Definitions

  • the present invention relates to a display technology field, and more particularly to a GOA circuit of LTPS semiconductor TFT.
  • GOA Gate Drive On Array
  • TFT Thin Film Transistor
  • the GOA circuit comprises a pull-up part, a pull-up controlling part, a transfer part, a pull-down part, a pull-down holding part and a boost part in charge of boosting voltage level.
  • the boost part generally comprises a bootstrap capacitor.
  • the pull-up part is mainly in charge of outputting the inputted clock signal (Clock) to the gate of the thin film transistor as being the driving signals of the liquid crystal display.
  • the pull-up control part is mainly in charge of activating the pull-up part, and is generally functioned by the signal transferred from the former GOA circuit.
  • the pull-down part is mainly in charge of rapidly pulling down the scan signal (i.e. the voltage level of the gate of the thin film transistor) to be low voltage level after outputting the scanning signal.
  • the pull-down holding circuit part is mainly in charge of maintaining the scanning signal and the signal of the pull-up part in an off state (i.e. the set negative voltage level).
  • the boost part in mainly in charge of performing a second boost to the voltage level of the pull-up part for ensuring the normal output of the pull-up part.
  • the LTPS-TFT LCD With the development of the LTPS semiconductor TFT, the LTPS-TFT LCD also becomes the focus that people pay lots of attentions. Because the LTPS semiconductor has better order than amorphous silicon (a-Si) and the LTPS itself has extremely high carrier mobility which can be more than 100 times of the amorphous silicon semiconductor, which the GOA skill can be utilized to manufacture the gate driver on the TFT array substrate to achieve the objective of system integration and saving the space and the cost of the driving IC.
  • the single type (single N-type or single P-type) GOA circuit has issues that the structure is complex, and the circuit property is poor, and particularly the power consumption is large.
  • the power consumption is an important index of the performance. Therefore, how to reduce the power consumption and strengthen the circuit structure and the stability of the entire performance has become an important agenda faced by the GOA circuit of LTPS semiconductor TFT.
  • An objective of the present invention is to provide a GOA circuit of LTPS semiconductor TFT to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the LTPS with single type TFT elements; the problem of TFT leakage of the single type GOA circuit can be solved to optimize the performance of the circuit; meanwhile, the ultra narrow frame or frameless designs can be realized.
  • the present invention provides a GOA circuit of LTPS semiconductor TFT, employed for forward-backward bidirectional scan transmission, comprising a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and comprises a transmission part, a transmission control part, an information storage part, a data erase part, an output control part and an output buffer part;
  • the transmission part is electrically coupled to a first low frequency signal, a second low frequency signal, a driving output end of an N ⁇ 1th GOA unit which is the former stage of the Nth GOA unit, a driving output end of an N+1th GOA unit which is the latter stage of the Nth GOA unit and the information storage part;
  • the transmission control part is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, the driving output end of the N ⁇ 1th GOA unit which is the former stage of the Nth GOA unit, an M ⁇ 2th sequence signal, a high voltage source, a low voltage source and the information storage part;
  • the information storage part is electrically coupled to the transmission part, the transmission control part, the data erase part, the high voltage source and the low voltage source;
  • the data erase part is electrically coupled to the information storage part, the output control part, the high voltage source and the reset signal end;
  • the output control part is electrically coupled to the data erase part, the output buffer part,
  • first low frequency signal and the second low frequency signal are switched along with the forward-backward scan, and the first low frequency signal is equivalent to a direct current high voltage level, and the second low frequency signal is equivalent to a direct current low voltage level as forward scan; the first low frequency signal is equivalent to a direct current low voltage level, and the second low frequency signal is equivalent to a direct current high voltage level as backward scan;
  • the transmission part comprises:
  • a third P-type transistor and a gate of the third P-type transistor is electrically coupled to the first low frequency signal, and a source is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and a drain is electrically coupled to a second node;
  • a fourth N-type transistor and a gate of the fourth N-type transistor is electrically coupled to the second low frequency signal, and a source is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and a drain is electrically coupled to the second node;
  • the transmission control part comprises:
  • the sixth P-type transistor and a gate of the sixth P-type transistor is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and a source is electrically coupled to the drain of the fifth P-type transistor, and a drain is electrically coupled to a source of a seventh N-type transistor;
  • an eighth N-type transistor and the gate of the eighth N-type transistor is electrically coupled to the driving output end of the N+1th GOA unit which is the latter stage of the Nth GOA unit, and the source is electrically coupled to the drain of the sixth P-type transistor, and a drain is electrically coupled to the low voltage source;
  • the tenth N-type transistor and a gate of the tenth N-type transistor is electrically coupled to the drain of the sixth P-type transistor, and the source is electrically coupled to the drain of the ninth P-type transistor, and a drain is electrically coupled to the low voltage source;
  • a gate of the eleventh P-type transistor is electrically coupled to the drain of the sixth P-type transistor, and a source is electrically coupled to a source of a twelfth N-type transistor, and a drain is electrically coupled to the M ⁇ 2th sequence signal;
  • the information storage part comprises:
  • a thirteenth N-type transistor and a gate of the thirteenth N-type transistor is electrically coupled to the source of the eleventh P-type transistor, and a source is electrically coupled to a drain of a fourteenth P-type transistor, and a drain is electrically coupled to the low voltage source;
  • the fourteenth P-type transistor and a gate of the fourteenth P-type transistor is electrically coupled to the source of the eleventh P-type transistor, and a source is electrically coupled to the high voltage source, and the drain is electrically coupled to the source of the thirteenth N-type transistor;
  • a fifteenth P-type transistor and a gate of the fifteenth P-type transistor is electrically coupled to the source of the thirteenth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a sixteenth P-type transistor;
  • the sixteenth P-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the fifteenth P-type transistor, and a drain is electrically coupled to a source of a seventeenth N-type transistor;
  • the seventeenth N-type transistor, and a gate of the sixteenth P-type transistor is electrically coupled to the first node, and the source is electrically coupled to the drain of the sixteenth P-type transistor, and a drain is electrically coupled to a source of an eighteenth N-type transistor;
  • the eighteenth N-type transistor and a gate of the eighteenth N-type transistor is electrically coupled to the source of the eleventh P-type transistor, and the source is electrically coupled to the drain of the seventeenth N-type transistor, and a drain is electrically coupled to the low voltage source;
  • a nineteenth P-type transistor and a gate of the nineteenth P-type transistor is electrically coupled to the gate of the thirteenth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a twentieth P-type transistor;
  • the twentieth P-type transistor and a gate of the twentieth P-type transistor is electrically coupled to the second node, and the source is electrically coupled to the drain of the nineteenth P-type transistor, and a drain is electrically coupled to a source of a twenty-first N-type transistor;
  • the twenty-first N-type transistor and a gate of the twenty-first N-type transistor is electrically coupled to the second node, and the source is electrically coupled to the drain of the twentieth P-type transistor, and a drain is electrically coupled to a source of a twenty-second N-type transistor;
  • the twenty-second N-type transistor and a gate of the twenty-second N-type transistor is electrically coupled to the source of the thirteenth N-type transistor, and the source is electrically coupled to the drain of the twenty-first N-type transistor, and a drain is electrically coupled to the low voltage source;
  • the data erase part comprises:
  • a twenty-third P-type transistor and a gate of the twenty-third P-type transistor is electrically coupled to the reset signal end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the drain of the sixteenth P-type transistor and the drain of the twentieth P-type transistor;
  • the output control part comprises:
  • a twenty-fourth P-type transistor and a gate of the twenty-fourth P-type transistor is electrically coupled to the drain of the sixteenth P-type transistor and the drain of the twentieth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the driving output end;
  • a twenty-fifth N-type transistor and a gate of the twenty-fifth N-type transistor is electrically coupled to the drain of the sixteenth P-type transistor and the drain of the twentieth P-type transistor, and a source is electrically coupled to the driving output end, and a drain is electrically coupled to the low voltage source;
  • a twenty-sixth P-type transistor and a gate of the twenty-sixth P-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a twenty-ninth N-type transistor;
  • a twenty-seventh N-type transistor and a gate of the twenty-seventh N-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to a drain of the twenty-ninth N-type transistor, and a drain is electrically coupled to the low voltage source;
  • a twenty-eighth P-type transistor and a gate of the sixteenth P-type transistor is electrically coupled to the sequence signal, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the source of the twenty-ninth N-type transistor;
  • the twenty-ninth N-type transistor and a gate of the twenty-ninth N-type transistor is electrically coupled to the sequence signal, and the source is electrically coupled to the drain of twenty-sixth P-type transistor, and a drain is electrically coupled to the source of the twenty-seventh N-type transistor;
  • the output buffer part comprises:
  • a thirtieth P-type transistor and a gate of the thirtieth P-type transistor is electrically coupled to the source of the twenty-ninth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a thirty-first N-type transistor;
  • the thirty-first N-type transistor and a gate of the thirty-first N-type transistor is electrically coupled to the source of the twenty-ninth N-type transistor, and the source is electrically coupled to the drain of the thirtieth P-type transistor, and a drain is electrically coupled to the low voltage source;
  • the thirty-third N-type transistor and a gate of the thirty-third N-type transistor is electrically coupled to the drain of the thirtieth P-type transistor, and the source is electrically coupled to the drain of the thirty-second P-type transistor, and a drain is electrically coupled to the low voltage source;
  • a thirty-fourth P-type transistor and a gate of the thirty-fourth P-type transistor is electrically coupled to the drain of the thirty-second P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to the output end;
  • a thirty-fifth N-type transistor and a gate of the thirty-fifth N-type transistor is electrically coupled to the drain of the thirty-second P-type transistor, and a source is electrically coupled to the output end, and a drain is electrically coupled to the low voltage source.
  • the GOA circuit further comprises a second output control part, a second output buffer part;
  • the second output control part is electrically coupled to the output control part, the driving output end, an M+1th sequence signal, the high voltage source and the low voltage source;
  • the second output buffer part is electrically coupled to the second output control part, an output end of the N+1th GOA unit, the high voltage source and the low voltage source;
  • a thirty-sixth P-type transistor and a gate of the thirty-sixth P-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a thirty-ninth N-type transistor;
  • a thirty-seventh N-type transistor and a gate of the thirty-seventh N-type transistor is electrically coupled to the driving output end, and a source is electrically coupled to the drain of the thirty-ninth N-type transistor, and a drain is electrically coupled to the low voltage source;
  • the thirty-ninth N-type transistor and a gate of the thirty-ninth N-type transistor is electrically coupled to the M+1th sequence signal, and the source is electrically coupled to the drain of the thirty-sixth P-type transistor, and the drain is electrically coupled to the source of the thirty-seventh N-type transistor;
  • the second output buffer part comprises:
  • a fortieth P-type transistor and a gate of the fortieth P-type transistor is electrically coupled to the source of the thirty-ninth N-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a forty-first N-type transistor;
  • the forty-first N-type transistor and a gate of the forty-first N-type transistor is electrically coupled to the source of the thirty-ninth N-type transistor, and the source is electrically coupled to the drain of the fortieth P-type transistor, and a drain is electrically coupled to the low voltage source;
  • a forty-second P-type transistor and a gate of the forty-second P-type transistor is electrically coupled to the drain of the fortieth P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to a source of a forty-third N-type transistor;
  • the forty-third N-type transistor and a gate of the forty-third N-type transistor is electrically coupled to the drain of the fortieth P-type transistor, and the source is electrically coupled to the drain of the forty-second P-type transistor, and a drain is electrically coupled to the low voltage source;
  • a forty-fourth P-type transistor and a gate of the forty-fourth P-type transistor is electrically coupled to the drain of the forty-second P-type transistor, and a source is electrically coupled to the high voltage source, and a drain is electrically coupled to an output end of the N+1th GOA unit;
  • a forty-fifth N-type transistor and a gate of the forty-fifth N-type transistor is electrically coupled to the drain of the forty-second P-type transistor, and a source is electrically coupled to the output end of the N+1th GOA unit, and a drain is electrically coupled to the low voltage source.
  • all the source of the first P-type transistor, the source of the second N-type transistor, the gate of the fifth P-type transistor, the gate of the seventh N-type transistor are electrically coupled to an activation signal end of the circuit.
  • the first P-type transistor and the second N-type transistor construct a forward transmission gate, employed to forward transmit a driving output signal of the N ⁇ 1th GOA unit to the information storage part;
  • the third P-type transistor and the fourth N-type transistor construct a backward transmission gate, employed to backward transmit a driving output signal of the N+1th GOA unit to the information storage part.
  • the fifth P-type transistor, the sixth P-type transistor, the seventh N-type transistor, the eighth N-type transistor construct a NOR gate logic unit; the ninth P-type transistor, the tenth N-type transistor construct an inverter; the eleventh P-type transistor, the twelfth N-type transistor construct a transmission gate; the transmission control part is employed to control the M ⁇ 2th sequence signal and transmits it to the information storage part.
  • the fifteenth P-type transistor, the sixteenth P-type transistor, the seventeenth N-type transistor, the eighteenth N-type transistor construct a forward sequence inverter; the nineteenth P-type transistor, the twentieth P-type transistor, the twenty-first N-type transistor, the twenty-second N-type transistor construct a backward sequence inverter; the thirteenth N-type transistor, the fourteenth P-type transistor construct an inverter; the information storage part is employed to save and transmit the signals from the driving output end of the N ⁇ 1th GOA unit, the driving output end of the N+1th GOA unit and the M ⁇ 2th sequence signal.
  • the data erase part is employed to erase the voltage level of the driving output end of the circuit in due time.
  • the twenty-sixth P-type transistor, the twenty-seventh N-type transistor, the twenty-eighth P-type transistor and the twenty-ninth N-type construct a NAND gate logic unit; the twenty-fourth P-type transistor, twenty-fifth N-type transistor construct an inverter; the output control part is employed to control a scan signal outputted by the output end to output the scan signal according with time sequence.
  • the thirtieth P-type transistor and the thirty-first N-type transistor, the thirty-second P-type transistor and the thirty-third N-type transistor, the thirty-fourth P-type transistor and thirty-fifth N-type transistor respectively construct three inverters, employed to adjust the scan signal with a done sequence adjustment, and meanwhile, to strengthen a band loading capacity.
  • the thirty-sixth P-type transistor, the thirty-seventh N-type transistor, the thirty-eighth P-type transistor, the thirty-ninth N-type transistor construct a NAND gate logic unit, employed to control the scan signal outputted by the output end of the N+1th GOA unit to output the scan signal according with time sequence; in the second output buffer part, the fortieth P-type transistor and the forty-first N-type transistor, the forty-second P-type transistor and the forty-third N-type transistor, the forty-fourth P-type transistor and the forty-fifth N-type transistor respectively construct three inverters, employed to adjust the scan signal with a done sequence adjustment, and meanwhile, to strengthen a band loading capacity; the second output control part and the second output buffer part output a scan signal of the latter stage from the output end of the N+1th GOA unit according to the outputted signal of the driving output end and the M+1th sequence signal to realize that the single stage GOA unit controls two stage circuits forward-backward bi
  • the sequence signal comprises four sets of sequence signals: a first sequence signal, a second sequence signal, a third sequence signal, a fourth sequence signal, and the M ⁇ 2th sequence signal is the third sequence signal when the sequence signal is the first sequence signal, and the M ⁇ 2th sequence signal is the fourth sequence signal when the sequence signal is the second sequence signal, and the M+1th sequence signal is the first sequence signal when the sequence signal is the fourth sequence signal.
  • the present invention provides the GOA circuit of LTPS semiconductor TFT, employed for forward-backward bidirectional scan transmission.
  • the Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors, comprising a transmission part, a transmission control part, an information storage part, a data erase part, an output control part and an output buffer part.
  • the transmission part comprises the transmission gate; the transmission control part comprises the NOR gate logic unit, the inverter and the transmission gate; the information storage part comprises the sequence inverter, the inverter; the output control part comprises the NAND gate logic unit, the inverter; the output buffer part comprises the inverter; the transmission gate is employed to perform the former-latter level transferring signal, and the NOR gate logic unit and the NAND gate logic unit are employed to convert the signals, and the sequence inverter and the inverter are employed to save and transmit the signals to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the LTPS with single type TFT elements, and the problem of TFT leakage of the single type GOA circuit to optimize the performance of the circuit; by setting the second output control part and the second output buffer part to realize sharing the driving output end to make the single stage GOA unit control two stage circuits forward-backward bidirectional scan output, the amount of the TFTs can be reduced to realize the ultra narrow frame or frameless designs.
  • FIG. 1 is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention
  • FIG. 2 is a circuit diagram of the first stage connection of the GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention
  • FIG. 3 is a circuit diagram of the last stage connection of the GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention
  • FIG. 4 is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the second embodiment of the present invention.
  • FIG. 5 is a waveform diagram of the key nodes in the GOA circuit of LTPS semiconductor TFT as forward scan according to the present invention
  • FIG. 6 is a waveform diagram of the key nodes in the GOA circuit of LTPS semiconductor TFT as backward scan according to the present invention.
  • FIG. 1 is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the first embodiment of the present invention.
  • the GOA circuit of LTPS semiconductor TFT employed for forward-backward bidirectional scan transmission comprises a plurality of GOA units which are cascade connected, and N is set to be a positive integer and an Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors and comprises a transmission part 100 , a transmission control part 200 , an information storage part 300 , a data erase part 400 , an output control part 500 and an output buffer part 600 ;
  • the transmission part 100 is electrically coupled to a first low frequency signal UD, a second low frequency signal DU, a driving output end ST(N ⁇ 1) of an N ⁇ 1th GOA unit which is the former stage of the Nth GOA unit, a driving output end ST(N+1) of an N+1th GOA unit which is the latter stage of the Nth GOA unit and the information storage part 300 ;
  • the transmission control part 200 is electrically coupled to a driving output end ST(N+1) of an N+1th GOA unit which is the latter stage of the Nth GOA unit, the driving output end ST(N ⁇ 1) of the N ⁇ 1th GOA unit which is the former stage of the Nth GOA unit, an M ⁇ 2th sequence signal CK(M ⁇ 2) a high voltage source H, a low voltage source L and the information storage part 300 ;
  • the information storage part 300 is electrically coupled to the transmission part 100 , the transmission control part 200 , the data erase part 400 , the high voltage source H and the low voltage source L;
  • first low frequency signal UD and the second low frequency signal DU are switched along with the forward-backward scan, and the first low frequency signal UD is equivalent to a direct current high voltage level, and the second low frequency signal DU is equivalent to a direct current low voltage level as forward scan; the first low frequency signal UD is equivalent to a direct current low voltage level, and the second low frequency signal DU is equivalent to a direct current high voltage level as backward scan;
  • the transmission part comprises 100 a first P-type transistor T 1 , and a gate of the first P-type transistor T 1 is electrically coupled to the second low frequency signal DU, and a source is electrically coupled to the driving output end ST(N ⁇ 1) of the N ⁇ 1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to a first node P(N); a second N-type transistor T 2 , and a gate of the second N-type transistor T 2 is electrically coupled to the first low frequency signal UD, and a source is electrically coupled to the driving output end ST(N ⁇ 1) of the N ⁇ 1th GOA unit which is the former stage of the Nth GOA unit, and a drain is electrically coupled to the first node P(N); a third P-type transistor T 3 , and a gate of the third P-type transistor T 3 is electrically coupled to the first low frequency signal UD, and a source is electrically coupled to the driving output end ST(N+1) of the N+1th
  • the first P-type transistor T 1 and the second N-type transistor T 2 construct a forward transmission gate, and when the first low frequency signal UD is equivalent to a direct current high voltage level, and the second low frequency signal DU is equivalent to a direct current low voltage level as forward scan, the forward transmission gate functions to be employed to forward transmit a driving output signal ST(N ⁇ 1) of the N ⁇ 1th GOA unit to the information storage part 300 ; the third P-type transistor and the fourth N-type transistor construct a backward transmission gate, and when the first low frequency signal UD is equivalent to a direct current low voltage level, and the second low frequency signal DU is equivalent to a direct current high voltage level as backward scan, the backward transmission gate functions to be employed to backward transmit a driving output signal ST(N+1) of the N+1th GOA unit to the information storage part 300 .
  • the transmission control part 200 comprises: a fifth P-type transistor T 5 , and a gate of the fifth P-type transistor T 5 is electrically coupled to the driving output end ST(N ⁇ 1) of the N ⁇ 1th GOA unit which is the former stage of the Nth GOA unit, and the source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a sixth P-type transistor T 6 ; the sixth P-type transistor T 6 , and a gate of the sixth P-type transistor T 6 is electrically coupled to the driving output end ST(N+1) of the N ⁇ 1th GOA unit which is the latter stage of the Nth GOA unit, and a source is electrically coupled to the drain of the fifth P-type transistor T 5 , and a drain is electrically coupled to a source of a seventh N-type transistor T 7 ; the seventh N-type transistor T 7 , and a gate of the seventh N-type transistor T 7 is electrically coupled to the driving output end ST(N ⁇ 1) of the N ⁇ 1th G
  • the information storage part 300 comprises a thirteenth N-type transistor T 13 , and a gate of the thirteenth N-type transistor T 13 is electrically coupled to the source of the eleventh P-type transistor T 11 , and a source is electrically coupled to a drain of a fourteenth P-type transistor T 14 , and a drain is electrically coupled to the low voltage source L; the fourteenth P-type transistor T 14 , and a gate of the fourteenth P-type transistor T 14 is electrically coupled to the source of the eleventh P-type transistor T 11 , and a source is electrically coupled to the high voltage source H, and the drain is electrically coupled to the source of the thirteenth N-type transistor T 13 ; a fifteenth P-type transistor T 15 , and a gate of the fifteenth P-type transistor T 15 is electrically coupled to the source of the thirteenth N-type transistor T 13 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a sixteenth P-type transistor T
  • the fifteenth P-type transistor T 15 , the sixteenth P-type transistor T 16 , the seventeenth N-type transistor T 17 , the eighteenth N-type transistor T 18 construct a forward sequence inverter, and the forward sequence inverter is electrically coupled to the forward transmission gate in the transmission part 100 ;
  • the nineteenth P-type transistor, the twentieth P-type transistor, the twenty-first N-type transistor, the twenty-second N-type transistor construct a backward sequence inverter, and the backward sequence inverter is electrically coupled to the backward transmission gate in the transmission part 100 ;
  • the thirteenth N-type transistor T 13 , the fourteenth P-type transistor T 14 construct an inverter; as forward scan, the information storage part 300 is employed to save and transmit the signals from the driving output end ST(N ⁇ 1) of the N ⁇ 1th GOA unit and the M ⁇ 2th sequence signal CK(M ⁇ 2); as backward scan, the information storage part 300 is employed to save and transmit the signals from the driving output end ST(N+1) of the N
  • the data erase part 400 comprises a twenty-third P-type transistor T 23 , and a gate of the twenty-third P-type transistor T 23 is electrically coupled to the reset signal end Reset, and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to the drain of the sixteenth P-type transistor T 16 and the drain of the twentieth P-type transistor T 20 ; the data erase part 400 is employed to erase the voltage level of the driving output end ST(N) of the circuit in due time.
  • the reset signal end Reset receives a pulse reset signal to discharge the driving output end ST(N), and accordingly to erase the voltage level of the driving output end ST(N) at the start of the every frame.
  • the output control part 500 comprises a twenty-fourth P-type transistor T 24 , and a gate of the twenty-fourth P-type transistor T 24 is electrically coupled to the drain of the sixteenth P-type transistor T 16 and the drain of the twentieth P-type transistor T 20 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to the driving output end ST(N); a twenty-fifth N-type transistor T 25 , and a gate of the twenty-fifth N-type transistor T 25 is electrically coupled to the drain of the sixteenth P-type transistor T 16 and the drain of the twentieth P-type transistor T 20 , and a source is electrically coupled to the driving output end ST(N), and a drain is electrically coupled to the low voltage source L; a twenty-sixth P-type transistor T 26 , and a gate of the twenty-sixth P-type transistor T 26 is electrically coupled to the driving output end ST(N), and a source is electrically coupled to the high voltage source H,
  • the twenty-sixth P-type transistor T 26 , the twenty-seventh N-type transistor T 27 , the twenty-eighth P-type transistor T 28 and the twenty-ninth N-type T 29 construct a NAND gate logic unit; the twenty-fourth P-type transistor T 24 , twenty-fifth N-type transistor T 25 construct an inverter; the output control part 500 is employed to control a scan signal outputted by the output end G(N) to output the scan signal according with time sequence.
  • the output buffer part 600 comprises a thirtieth P-type transistor T 30 , and a gate of the thirtieth P-type transistor T 30 is electrically coupled to the source of the twenty-ninth N-type transistor T 29 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a thirty-first N-type transistor T 31 ; the thirty-first N-type transistor T 31 , and a gate of the thirty-first N-type transistor T 31 is electrically coupled to the source of the twenty-ninth N-type transistor T 29 , and the source is electrically coupled to the drain of the thirtieth P-type transistor T 30 , and a drain is electrically coupled to the low voltage source L; a thirty-second P-type transistor T 32 , and a gate of the thirty-second P-type transistor T 32 is electrically coupled to the drain of the thirtieth P-type transistor T 30 , and a source is electrically coupled to the high voltage source H, and a
  • the thirtieth P-type transistor T 30 and the thirty-first N-type transistor T 31 , the thirty-second P-type transistor T 32 and the thirty-third N-type transistor T 33 , the thirty-fourth P-type transistor T 34 and thirty-fifth N-type transistor T 35 respectively construct three inverters, employed to adjust the scan signal with a done sequence adjustment, and meanwhile, to strengthen a band loading capacity.
  • all the source of the first P-type transistor T 1 , the source of the second N-type transistor T 2 , the gate of the fifth P-type transistor T 5 , the gate of the seventh N-type transistor T 7 are electrically coupled to an activation signal end STV of the circuit; in the last stage connection, all the source of the third P-type transistor T 3 , the source of the fourth N-type transistor T 4 , the gate of the sixth P-type transistor T 6 , the gate of the eighth N-type transistor T 8 are electrically coupled to the activation signal end STV of the circuit.
  • FIGS. 5-6 respectively are waveform diagrams of the key nodes in the GOA circuit of LTPS semiconductor TFT as forward scan, backward scan according to the present invention.
  • the first low frequency signal UD and the second low frequency signal DU are low frequency signals which the voltage levels can be switched along with the forward-backward scan, and the first low frequency signal UD is equivalent to a direct current high voltage level, and the second low frequency signal DU is equivalent to a direct current low voltage level as forward scan, and the first low frequency signal UD is equivalent to a direct current low voltage level, and the second low frequency signal DU is equivalent to a direct current high voltage level as backward scan;
  • the order of the clock signal CK(M) has differences as forward-backward scan;
  • the high voltage source H and the low voltage source L are inputted constant voltage control signals;
  • the signal from the reset signal end Reset is a pulse signal which mainly discharges the key notes of the circuit at the start of the every frame;
  • STV signal is the
  • the first low frequency signal UD and the second low frequency signal DU are equivalent to direct current high and low voltage levels as forward scan;
  • the sequence signal CK(M) comprises four sets of sequence signals, which respectively are a first sequence signal CK( 1 ), a second sequence signal CK( 2 ), a third sequence signal CK( 3 ), a fourth sequence signal CK( 4 ), and the M ⁇ 2th sequence signal CK(M ⁇ 2) is the third sequence signal CK( 3 ) when the sequence signal CK(M) is the first sequence signal CK( 1 ), and the M ⁇ 2th sequence signal CK(M ⁇ 2) is the fourth sequence signal CK( 4 ) when the sequence signal CK(M) is the second sequence signal CK( 2 ), and the M+1th sequence signal CK(M+1) is the first sequence signal CK( 1 ) when the sequence signal CK(M) is the fourth sequence signal CK( 4 ).
  • the pulse signals of the sequence signal CK(M) arrive in sequence of CK( 1 )-CK( 4 ).
  • the third sequence signal CK( 3 ) corresponds to the output signal of the first stage output end G( 1 ).
  • the fourth sequence signal CK( 4 ) corresponds to the output signal of the second stage output end G( 2 ), and the first sequence signal CK( 1 ) corresponds to the output signal of the third stage output end G( 3 ), and the second sequence signal CK( 2 ) corresponds to the output signal of the fourth stage output end G( 4 ), and so on.
  • the waveforms of the respective key nodes satisfy the demands of design.
  • the first low frequency signal UD and the second low frequency signal DU are equivalent to direct current low and high voltage levels as backward scan, and the pulse signals of the sequence signal CK(M) arrive in sequence of CK( 4 )-CK( 1 ).
  • the second sequence signal CK( 2 ) corresponds to the output signal of the first stage output end G( 1 ).
  • the first sequence signal CK( 1 ) corresponds to the output signal of the second stage output end G( 2 ), and the fourth sequence signal CK( 4 ) corresponds to the output signal of the third stage output end G( 3 ), and the third sequence signal CK( 3 ) corresponds to the output signal of the fourth stage output end G( 4 ), and so on.
  • FIG. 4 is a circuit diagram of a GOA circuit of LTPS semiconductor TFT according to the second embodiment of the present invention.
  • the GOA circuit further comprises a second output control part 501 , a second output buffer part 601 .
  • the second output control part 501 is electrically coupled to the output control part 500 , the driving output end ST(N), an M+1th sequence signal CK(M+1), the high voltage source H and the low voltage source L;
  • the second output buffer part 601 is electrically coupled to the second output control part 501 , an output end G(N+1) of the N+1th GOA unit, the high voltage source H and the low voltage source L.
  • the second output control part 501 comprises a thirty-sixth P-type transistor T 36 , and a gate of the thirty-sixth P-type transistor T 36 is electrically coupled to the driving output end ST(N), and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a thirty-ninth N-type transistor T 39 ; a thirty-seventh N-type transistor T 37 , and a gate of the thirty-seventh N-type transistor T 37 is electrically coupled to the driving output end ST(N), and a source is electrically coupled to the drain of the thirty-ninth N-type transistor T 39 , and a drain is electrically coupled to the low voltage source L; a thirty-eighth P-type transistor T 38 , and a gate of the thirty-eighth P-type transistor T 38 is electrically coupled to an M+1th sequence signal CK(M+1), and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled
  • the second output buffer part 601 comprises a fortieth P-type transistor T 40 , and a gate of the fortieth P-type transistor T 40 is electrically coupled to the source of the thirty-ninth N-type transistor T 39 , and a source is electrically coupled to the high voltage source H, and a drain is electrically coupled to a source of a forty-first N-type transistor T 41 ; the forty-first N-type transistor T 41 , and a gate of the forty-first N-type transistor T 41 is electrically coupled to the source of the thirty-ninth N-type transistor T 39 , and the source is electrically coupled to the drain of the fortieth P-type transistor T 40 , and a drain is electrically coupled to the low voltage source L; a forty-second P-type transistor T 42 , and a gate of the forty-second P-type transistor T 42 is electrically coupled to the drain of the fortieth P-type transistor T 40 , and a source is electrically coupled to the high voltage
  • the second output control part 501 By adding the second output control part 501 , the second output buffer part 601 , the effect that the single stage GOA unit controls two stage circuits forward-backward bidirectional scan output can be realized. Meanwhile, the second output control part 501 and the second output buffer part 601 share one driving output end ST(N). The amount of the TFTs can be reduced and realize the ultra narrow frame or frameless designs by sharing the driving output end ST(N).
  • the GOA circuit of LTPS semiconductor TFT according to the present invention is employed for forward-backward bidirectional scan transmission.
  • the Nth GOA unit utilizes a plurality of N-type transistors and a plurality of P-type transistors, comprising a transmission part, a transmission control part, an information storage part, a data erase part, an output control part and an output buffer part.
  • the transmission part comprises the transmission gate; the transmission control part comprises the NOR gate logic unit, the inverter and the transmission gate; the information storage part comprises the sequence inverter, the inverter; the output control part comprises the NAND gate logic unit, the inverter; the output buffer part comprises the inverter; the transmission gate is employed to perform the former-latter level transferring signal, and the NOR gate logic unit and the NAND gate logic unit are employed to convert the signals, and the sequence inverter and the inverter are employed to save and transmit the signals to solve the issues that the stability of the circuit is poor, and the power consumption is larger as concerning the LTPS with single type TFT elements, and the problem of TFT leakage of the single type GOA circuit to optimize the performance of the circuit; by setting the second output control part and the second output buffer part to realize sharing the driving output end to make the single stage GOA unit control two stage circuits forward-backward bidirectional scan output, the amount of the TFTs can be reduced to realize the ultra narrow frame or frameless designs.

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10262613B2 (en) 2016-08-04 2019-04-16 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driver on array circuit and LCD panel
US10796656B1 (en) * 2018-05-30 2020-10-06 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104700799B (zh) * 2015-03-17 2017-09-12 深圳市华星光电技术有限公司 栅极驱动电路及显示装置
CN104766576B (zh) * 2015-04-07 2017-06-27 深圳市华星光电技术有限公司 基于p型薄膜晶体管的goa电路
CN105096853B (zh) * 2015-07-02 2017-04-19 武汉华星光电技术有限公司 一种扫描驱动电路
CN104992653B (zh) 2015-07-02 2017-09-26 武汉华星光电技术有限公司 一种扫描驱动电路
CN105047155B (zh) * 2015-08-17 2017-07-07 深圳市华星光电技术有限公司 液晶显示装置及其goa扫描电路
CN105118463B (zh) * 2015-09-22 2018-01-09 深圳市华星光电技术有限公司 一种goa电路及液晶显示器
CN105244003B (zh) * 2015-11-12 2018-01-09 深圳市华星光电技术有限公司 栅极驱动电路以及移位寄存电路
CN105336302B (zh) * 2015-12-07 2017-12-01 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN105469760B (zh) * 2015-12-17 2017-12-29 武汉华星光电技术有限公司 基于ltps半导体薄膜晶体管的goa电路
CN105575349B (zh) * 2015-12-23 2018-03-06 武汉华星光电技术有限公司 Goa电路及液晶显示装置
CN106097996B (zh) * 2016-06-13 2018-02-16 武汉华星光电技术有限公司 一种goa电路及液晶显示器
US10373578B2 (en) 2016-11-28 2019-08-06 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA driving circuit
CN107993620B (zh) * 2017-11-17 2020-01-10 武汉华星光电技术有限公司 一种goa电路
CN108320708B (zh) * 2018-05-10 2021-01-26 京东方科技集团股份有限公司 一种移位寄存器及其驱动方法、栅极驱动电路、显示装置
CN110728940B (zh) * 2019-09-17 2020-12-08 深圳市华星光电半导体显示技术有限公司 反相器、goa电路及显示面板
CN111754916B (zh) * 2020-07-09 2021-07-23 武汉华星光电技术有限公司 Goa电路及显示面板

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4565815B2 (ja) * 2003-06-27 2010-10-20 三洋電機株式会社 表示装置
KR101311358B1 (ko) 2006-11-20 2013-09-25 치 메이 엘 코퍼레이션 단일형 트랜지스터를 포함한 논리 회로 및 이를 이용한회로
JP4968681B2 (ja) * 2007-07-17 2012-07-04 Ｎｌｔテクノロジー株式会社 半導体回路とそれを用いた表示装置並びにその駆動方法
JP5224241B2 (ja) * 2007-11-06 2013-07-03 Ｎｌｔテクノロジー株式会社 双方向シフトレジスタ、それを用いた表示装置
CN101556831B (zh) * 2008-04-10 2011-04-13 北京京东方光电科技有限公司 移位寄存器
US7817771B2 (en) * 2008-12-15 2010-10-19 Au Optronics Corporation Shift register
JP2010243526A (ja) * 2009-04-01 2010-10-28 Sony Corp 電気光学装置
KR20100130523A (ko) * 2009-06-03 2010-12-13 엘지디스플레이 주식회사 폴리실리콘을 이용한 박막트랜지스터를 포함하는 어레이 기판 및 이의 제조방법
JP5473686B2 (ja) * 2010-03-11 2014-04-16 三菱電機株式会社 走査線駆動回路
JP5669453B2 (ja) * 2010-06-22 2015-02-12 株式会社ジャパンディスプレイ 双方向シフトレジスタ、及びこれを用いた画像表示装置
US8325127B2 (en) * 2010-06-25 2012-12-04 Au Optronics Corporation Shift register and architecture of same on a display panel
CN102650751B (zh) * 2011-09-22 2014-08-06 京东方科技集团股份有限公司 一种goa电路、阵列基板及液晶显示器件
CN102654968B (zh) * 2011-11-25 2014-12-10 京东方科技集团股份有限公司 移位寄存器、栅极驱动器及显示装置
TW201329797A (zh) * 2012-01-04 2013-07-16 Wintek Corp 觸控顯示面板
CN102629463B (zh) * 2012-03-29 2013-10-09 京东方科技集团股份有限公司 移位寄存器单元、移位寄存器电路、阵列基板及显示器件
CN103714792B (zh) * 2013-12-20 2015-11-11 京东方科技集团股份有限公司 一种移位寄存器单元、栅极驱动电路及显示装置
CN103714780B (zh) * 2013-12-24 2015-07-15 京东方科技集团股份有限公司 栅极驱动电路、方法、阵列基板行驱动电路和显示装置
CN103778896B (zh) * 2014-01-20 2016-05-04 深圳市华星光电技术有限公司 集成栅极驱动电路及具有集成栅极驱动电路的显示面板
CN203870945U (zh) * 2014-03-21 2014-10-08 京东方科技集团股份有限公司 驱动电路、goa单元、goa电路及显示装置
CN104064149B (zh) * 2014-07-07 2016-07-06 深圳市华星光电技术有限公司 像素电路、具备该像素电路的显示面板和显示器

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10262613B2 (en) 2016-08-04 2019-04-16 Wuhan China Star Optoelectronics Technology Co., Ltd. Gate driver on array circuit and LCD panel
US10796656B1 (en) * 2018-05-30 2020-10-06 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit

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US20160343323A1 (en) 2016-11-24
JP2017535811A (ja) 2017-11-30
WO2016070513A1 (zh) 2016-05-12
GB201703671D0 (en) 2017-04-19
KR101933327B1 (ko) 2018-12-27
CN104409054A (zh) 2015-03-11
GB2546648A (en) 2017-07-26
CN104409054B (zh) 2017-02-15
GB2546648B (en) 2020-10-28
JP6440225B2 (ja) 2018-12-19

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