US9722060B2 - Semiconductor device and semiconductor module - Google Patents

Semiconductor device and semiconductor module Download PDF

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Publication number
US9722060B2
US9722060B2 US14/926,475 US201514926475A US9722060B2 US 9722060 B2 US9722060 B2 US 9722060B2 US 201514926475 A US201514926475 A US 201514926475A US 9722060 B2 US9722060 B2 US 9722060B2
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semiconductor device
electrode
probe
semiconductor
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US20160240637A1 (en
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Hiroyuki Nakamura
Akira Okada
Eiji NOJIRI
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H01L29/7395—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H01L22/32—
    • H01L23/544—
    • H01L29/4232—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/273—Interconnections for measuring or testing, e.g. probe pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H01L2223/54426—
    • H01L2223/54453—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H10W72/07523—Active alignment, e.g. using optical alignment using marks or sensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/985—Alignment aids, e.g. alignment marks

Definitions

  • the present invention relates to a semiconductor device and a semiconductor module, and in particular, relates to a semiconductor device provided with a high withstand voltage semiconductor element and a semiconductor module provided with the semiconductor device.
  • the semiconductor device In evaluating the electrical characteristics of a semiconductor device (testing subject) mounted in a semiconductor wafer or a semiconductor chip, firstly, the semiconductor device is placed on the surface of a chuck stage of a semiconductor evaluation device. Next, the semiconductor device is fixed on the chuck stage through vacuum suction or the like. Thereafter, a contact probe is made into contact with a predetermined surface electrode of the semiconductor device, and the electrical characteristics are evaluated according to electrical inputs and outputs.
  • the surface of the chuck stage is used as the surface electrode.
  • the contact probe is deployed with a number of pins.
  • a gate electrode or an emitter electrode formed as the surface electrode is also reduced in size.
  • the footprint of the gate electrode regardless of the miniaturization of the semiconductor device, may be reduced when the element forming region (active region) is enlarged.
  • the gate electrode or the like is connected to a wire, and thus, reducing the footprint of the gate electrode or the like may cause problems in connecting it to a wire. The reason will be explained hereinafter.
  • a contact probe is made into contact with the surface of an electrode such as a gate electrode.
  • the tip end of the contact probe is formed into a sharp needle in shape.
  • the tip end of the contact probe may damage the surface of the electrode, roughening the surface of the electrode or causing irregularities to be formed on the surface of the electrode in correspondence to the contact points of the tip end of the contact probe.
  • the surface of the electrode to which a wire is connected is made rough or is caused to have irregularities thereon, the adhesion between the wire and the electrode is reduced. As a result, even a semiconductor device is evaluated as non-defective in the electrical characteristics, after it is assembled as a semiconductor module, the wire may disconnect from the electrode, making power supply impossible.
  • the present invention has been made in view of the above problems, and one object thereof is to provide a semiconductor device ensuring a liable connection of a wire to an electrode and another object thereof is to provide a semiconductor module provided with the semiconductor device.
  • the semiconductor device includes a semiconductor substrate, an element forming region, a termination region, and a first main surface electrode.
  • the semiconductor substrate has a first main surface and a second main surface facing each other.
  • the element forming region is defined on the first main surface of the semiconductor substrate.
  • the termination region is defined on the first main surface of the semiconductor substrate and is configured to surround the element forming region.
  • the first main surface electrode includes a first electrode formed in the element forming region and provided with a first region and a second region. The first region and the second region are separated by a separation member formed on the surface of the first electrode.
  • the first region is formed into a rectangular shape having a long side and a short side.
  • the second region is located closer to the long side of the first region.
  • the semiconductor module according to the present invention is such a semiconductor module that is provided with the semiconductor device described in the above, and in such semiconductor module, a wire is connected to the second region of the first electrode.
  • the first main surface electrode includes the first electrode which is provided with a first region to be contacted by a contact probe and a second region to be connected by a wire, it is possible to connect the wire to the first electrode reliably.
  • the semiconductor module according to the present invention it is possible to prevent the wire from getting disconnected from the second region, and thereby preventing power supply to the semiconductor module from being interrupted.
  • FIG. 1 is a planar view partially illustrating a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a enlarged planar view partially illustrating a gate electrode in FIG. 1 and a surrounding part thereof according to an embodiment of the present invention
  • FIG. 3 is a enlarged cross-sectional view partially illustrating a part taken along a section line III-III illustrated in FIG. 2 according to an embodiment of the present invention
  • FIG. 4 is a side view schematically illustrating the structure of a semiconductor evaluation device for performing an electrical evaluation for the semiconductor device according to an embodiment of the present invention
  • FIG. 5 is a side view schematically illustrating the structure of a probe body according to an embodiment of the present invention.
  • FIG. 6 is a side view illustrating a state in which a contact probe in the semiconductor evaluation device is brought into contact with the semiconductor device according to an embodiment of the present invention
  • FIG. 7 is a enlarged side view partially illustrating the state in which the contact probe is in contact with the semiconductor device according to an embodiment of the present invention.
  • FIG. 8 is a enlarged planar view partially illustrating a gate electrode and a surrounding part thereof after the evaluation of electrical characteristics according to an embodiment of the present invention
  • FIG. 9 is a enlarged cross-sectional view partially illustrating a part taken along a section line IX-IX illustrated in FIG. 8 according to an embodiment of the present invention.
  • FIG. 10 is a planar view partially illustrating an emitter electrode and a surrounding part thereof after the evaluation of electrical characteristics according to an embodiment of the present invention
  • FIG. 12 is a planar view partially illustrating a semiconductor device according to a second modification.
  • FIG. 13 is a planar view schematically illustrating a semiconductor module provided with the semiconductor device.
  • the semiconductor device refers to such a device that is used in a power converter or the like and provided with a high withstand voltage semiconductor element.
  • an element forming region 5 active region
  • a termination region 7 is defined on the same surface, surrounding element forming region 5 .
  • Termination region 7 is provided for offering voltage withstand, and may be configured into a guard-ring structure, a RESURF structure or a VLD (Variation of Lateral Doping) structure, for example.
  • an IGBT Insulated Gate Bipolar Transistor
  • element forming region 5 a gate electrode 9 and an emitter electrode 11 are disposed. Gate electrode 9 is disposed near termination region 7 , adjoining termination region 7 .
  • the back surface (second main surface) of semiconductor substrate 3 is formed with a collector electrode 25 (see FIG. 3 ).
  • gate electrode 9 is provided with a probe-contacting region 13 and a wiring region 15 .
  • Probe-contacting region 13 and wiring region 15 are separated by an insulator 17 formed on the surface of gate electrode 9 .
  • the surface of probe-contacting region 13 and the surface of wiring region 15 are located at the same height.
  • probe-contacting region 13 is configured to be contacted by a contact probe
  • wiring region 15 is configured to be connected by a wire.
  • a reference mark 19 is formed in wiring region 15 as a mark for connecting the wire.
  • the planar shape of probe-contacting region 13 is an oblong (a rectangle) with a long side and a short side.
  • Wiring region 15 is disposed closer to the long side of the rectangular shaped probe-contacting region 13 .
  • the area of wiring region 15 is set larger than the area of probe-contacting region 13 for the purpose of providing a longer stable electrical connection between the semiconductor device (gate electrode) and the wire after the semiconductor device is assembled into a product such as a semiconductor module.
  • Insulator 17 that separates probe-contacting region 13 and wiring region 15 , and reference mark 19 that is formed in wiring region 15 are formed simultaneously through patterning an insulating film which is formed for the purpose of covering probe-contacting region 13 , wiring region 15 and the like, and thus, insulator 17 and reference mark 19 have the same height.
  • insulator 17 is not limited to separating probe-contacting region 13 and wiring region 15 , it may be formed around gate electrode 9 so as to separate gate electrode 9 from the other regions.
  • An electrode member 21 for constituting gate electrode 9 is illustrated in FIG. 3 .
  • Electrode member 21 may be formed from aluminum (Al) for example but not limited thereto, any material superior in conductivity and suitable for manufacturing a semiconductor may be selected.
  • a semi-insulating silicon nitride film (SInSiN film) may be given as an example but not limited thereto.
  • the semi-insulating silicon nitride film is formed to cover termination region 7 , it is possible to stabilize the potential distribution in termination region 7 .
  • semiconductor device 1 in the above is described as an example of a vertical semiconductor device in which the electrical current flows between the front surface and the back surface of semiconductor substrate 3 but not limited thereto, semiconductor device 1 may be a lateral semiconductor device in which inputs and outputs are performed on one surface of the semiconductor substrate.
  • a semiconductor evaluation device 51 mainly includes a probe body 53 , a chuck stage 55 and an evaluation unit 57 .
  • probe body 53 includes a contact probe 69 , an insulating base 63 and a connection member 65 a.
  • semiconductor evaluation device 51 is electrically connected to the semiconductor device through a pair of electrodes.
  • one electrode is contact probe 69
  • the other electrode is the surface of chuck stage 55 .
  • contact probe 69 is brought into contact with the surface of an emitter electrode and the surface of a gate electrode, and the surface of chuck stage 55 is brought into contact with a collector electrode.
  • contact probe 69 is a cantilever-type contact probe.
  • the cantilever-type contact probe 69 is formed with a tip end 73 which is machined into a needle shape.
  • Tip end 73 is formed with a contact member 71 at a portion in contact with the surface electrode. It should be noted that although contact probe 69 is configured to have only tip end 73 inclined, it may have a multi-stage crank structure.
  • Contact probe 69 may be fabricated from metal material such as tungsten (W) or beryllium copper (BeCu) but not limited thereto.
  • tip end 73 or contact member 71 of contact probe 69 may be coated with gold (Au), palladium (Pd), tantalum (Ta) or platinum (Pt), for example.
  • contact probe 69 is formed with a flexible member 75 , and thus, as contact member 71 contacts the surface electrode, flexible member 75 deflects.
  • contact probe 69 is only illustrated as a pair of contact probes 69 facing each other, and it should be noted that in practice even more contact probes may be provided.
  • Contact probe 69 is provided with a mounting member 77 .
  • Mounting member 77 is mechanically fixed to insulating base 63 which constitutes the base of probe body 53 .
  • Contact probe 69 is electrically connected to evaluation unit 57 via connection member 65 a formed on insulating base 63 and via a signal lines 61 a .
  • the surface of chuck stage 55 is electrically connected to evaluation unit 57 via a connection member 65 b provided on chuck stage 55 and via a signal line 61 b.
  • connection member 65 a and connection 65 b are disposed in such a manner that the distance from connection member 65 a to connection member 65 b via contact probe 69 , semiconductor device 1 and chuck stage 55 is approximately the same in each contact probe.
  • connection member 65 a and connection member 65 b are arranged to face each other, sandwiching therebetween chuck stage 55 on which the semiconductor device is placed.
  • Each contact probe 69 and connection member 65 a are electrically connected via an electrical connection member 79 provided on insulating base 63 and via a signal line 61 .
  • Probe body 53 may be moved to an arbitrary position by a movable arm 67 . It should be noted that in the present embodiment, although probe body 53 is illustrated as being supported by a single movable arm 67 but not limited thereto, probe body 53 may be supported by a plurality of mobile arms for better stability. Instead of moving probe body 53 , it is possible to move chuck stage 55 alternatively.
  • Chuck stage 55 serves as a base for mounting semiconductor device 1 or a semiconductor wafer 59 and fixing the same thereon.
  • Semiconductor device 1 or the like is fixed on chuck stage 55 by vacuum suction.
  • the surface of chuck stage 55 is formed with a suction groove (not shown), and a part of the bottom surface of the suction groove is formed with suction holes.
  • the main part of semiconductor evaluation device 51 is configured as described above.
  • semiconductor device 1 or semiconductor wafer 59 with semiconductor device 1 integrated therein is mounted on chuck stage 55 by using a transport mechanism (not shown).
  • semiconductor device 1 or the like is fixed on chuck stage 55 by vacuum suction.
  • movable arm 67 is moved so as to bring each of the plurality of contact probes 69 into contact with a corresponding surface electrode formed on semiconductor device 1 or the like.
  • the evaluation on the desired electrical characteristics is performed after the plurality of contact probes 69 are brought into contact with the corresponding surface electrodes.
  • a single contact probe 69 is brought into contact with probe-contacting region 13 of gate electrode 9 of the IGBT provided in the semiconductor device, and a plurality of contact probes 69 are brought into contact with emitter electrode 11 .
  • a probe trail is formed on the surface of the surface electrode. The probe trail will be described later.
  • a plurality of contact probes 69 are arranged in such a manner that they are oriented from one end and the other end, respectively, toward the center of probe body 53 , which makes it possible to bring the plurality of contact probes 69 into contact with the surface electrode while maintaining the spacing between the opposing contact probes 69 . Maintaining the spacing between contact probes 69 is for the purpose of suppressing discharge.
  • contact probes 69 are released from the surface electrode.
  • semiconductor wafer 59 After the electrical evaluation is completed, contact probes 69 are released from the surface electrode.
  • semiconductor wafer 59 After the electrical evaluation is performed for all of semiconductor devices 1 integrated in semiconductor wafer 59 , semiconductor wafer 59 is moved away from chuck stage 55 , and another semiconductor device or another semiconductor wafer is mounted on the chuck stage for the evaluation of the electrical characteristics according to the same procedure.
  • the contact probe In performing the evaluation of the electrical characteristics by using the abovementioned contact probe, the contact probe (single contact probe) contacts probe-contacting region 13 of gate electrode 9 of semiconductor device 1 , and thereby, after the evaluation of the electrical characteristics, as illustrated in FIG. 8 , a probe trail 23 is left on probe-contacting region 13 of gate electrode 9 .
  • probe body 53 is made to approach semiconductor device 1 (semiconductor wafer 59 ) so that flexible member 75 of contact probe 69 is deflected.
  • semiconductor device 1 semiconductor wafer 59
  • contact member 71 at tip end 73 slides on the surface of probe-contacting region 13 , leaving probe trail 23 on the surface of probe-contacting region 13 .
  • the size of probe trail 23 is dependent on the displacing amount of contact member 71 and the size of contact member 71 itself.
  • probe trail 23 has a length LR, and the distance between the centers of contact members 71 is equal to a length LC.
  • wiring regions 15 is separated from probe-contacting region 13 , it is possible to reliably and closely connect a wire to the surface of a plain and no probe trail region (wiring region 15 ) of gate electrode 9 . As a result, even after the semiconductor device is assembled as a semiconductor module, the wire can be prevented from getting disconnected, and thus preventing the power supply from being interrupted reliably.
  • probe-contacting region 13 is described as being defined in gate electrode 9 , it is also possible to define the probe-contacting region in an emitter electrode. As illustrated in FIG. 10 , probe-contacting regions 13 may be disposed in emitter electrode 11 with intervals along X direction and with intervals along Y direction. By disposing wiring regions in an area other than probe-contacting region 13 , it is possible to prevent the wires from getting disconnected, and thereby preventing the power supply from being interrupted reliably. Accordingly, after the evaluation of the electrical characteristics for semiconductor device 1 is completed, the same number of probe trails as the number of the contact probes will be left on probe-contacting region 13 .
  • gate electrode 9 is arranged at a center position of one side (short side) of element forming region 5 and adjacent to termination region 7 .
  • modifications on the arrangement of the gate electrode in the element forming region will be described.
  • semiconductor device 1 according to the first modification is configured the same as semiconductor device 1 illustrated in FIG. 1 and the like except that gate electrode 9 is disposed at a corner of element forming region 5 adjacent to termination region 7 , and thus, the same members will be denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.
  • gate electrode 9 is disposed at a corner of element forming region 5 , and thereby, two of the four sides of the rectangular shaped gate electrode 9 adjoin to the boundary between gate electrode 9 and element forming region 5 in which emitter electrode 11 is provided.
  • semiconductor device 1 illustrated in FIG. 1 and the like is configured to have three sides of the four sides of the rectangular gate electrode 9 adjoining the boundary, it is possible to ensure a wider area for element forming regions 5 in the same region (area) of semiconductor substrate 3 .
  • semiconductor device 1 according to the second modification is configured the same as semiconductor device 1 illustrated in FIG. 1 and the like except that gate electrode 9 is disposed in the center of element forming region 5 spaced with a distance from termination region 7 , and thus, the same members will be denoted by the same reference numerals, and the description thereof will not be repeated unless necessary.
  • gate electrode 9 is disposed centrally in element forming region 5 .
  • a region where a channel is turned on will spread substantially uniformly from the center of element forming region 5 toward the periphery thereof, which makes it possible to further stabilize the electrical characteristics of semiconductor elements.
  • adopting such configuration can prevent the load from being concentrated on edges of element forming region 5 when connecting the wires.
  • probe-contacting region 13 and wiring region 15 are disposed in a surface electrode such as gate electrode 9 in the semiconductor device according to embodiments including the first modification and the second modification, and probe-contacting region 13 and wiring region 15 are separated by insulator 17 .
  • semiconductor device 1 is assembled as a semiconductor module and subjected to the evaluation of electrical characteristics, it is possible to prevent probe-contacting region 13 formed with irregularities from being wired, so that as illustrated in FIG. 13 , a wire 33 can be securely connected to wiring region 15 .
  • IGBT is given as an example of a semiconductor element formed in element forming region 5 .
  • the semiconductor element is not limited to IGBT, it may be any high withstand voltage semiconductor element used in power conversion or the like, for example, it may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a diode.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the structure of the semiconductor device described in the embodiment may be combined in various manner if necessary.
  • the present invention can be effectively applied to a semiconductor device provided with a high withstand voltage semiconductor element and a semiconductor module provided with the semiconductor device.

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Wire Bonding (AREA)
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JP2015028540A JP6476000B2 (ja) 2015-02-17 2015-02-17 半導体装置および半導体モジュール

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JP6476000B2 (ja) 2019-02-27
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