US9632794B2 - Subprocessor, integrated circuit device, and electronic apparatus - Google Patents

Subprocessor, integrated circuit device, and electronic apparatus Download PDF

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US9632794B2
US9632794B2 US13/258,717 US201013258717A US9632794B2 US 9632794 B2 US9632794 B2 US 9632794B2 US 201013258717 A US201013258717 A US 201013258717A US 9632794 B2 US9632794 B2 US 9632794B2
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subprocessor
command
processing
host processor
register
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US20120023312A1 (en
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Masakazu Isomura
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Crystal Leap Zrt
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Seiko Epson Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

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  • the invention relates to a subprocessor, an integrated circuit device, and an electronic apparatus or the like.
  • PTL 1 discloses a data processing device which includes a special-purpose data processing unit that performs operation processing and a general-purpose data processing unit that performs general-purpose processing.
  • a command fetch unit and a data interface are shared by these two units, there is a problem in that this method has a lot of restrictions on collaborative operations.
  • a subprocessor connected to a host processor through a bus controller, including: a command fetch unit that fetches a command from a subprocessor program; a register unit; a command decoding unit that decodes the fetched command; and an operation unit that performs command execution processing based on the decoding result, in which the host processor sets a program counter value indicating a storage destination of the subprocessor program and a processing start command for the processing of the subprocessor to the register unit through the bus controller, the command fetch unit fetches a command designated by the program counter value, the command decoding unit decodes the command, and the operation unit performs the command execution processing.
  • the subprocessor since the subprocessor includes the command fetch unit that fetches a command through the bus controller, the subprocessor can independently load a program without the intervention of the host processor and perform command execution processing.
  • the subprocessor may include a bus controller interface that performs interface processing between the bus controller and the subprocessor.
  • the subprocessor can independently fetch a command from the subprocessor program or independently perform reading or writing of data for execution of a command through the bus controller interface.
  • the bus controller interface may include a host interface that performs interface processing between the host processor and the subprocessor.
  • the host processor can access the register unit of the subprocessor through the host interface.
  • the bus controller interface may include a data interface for reading or writing data for execution of a command.
  • the subprocessor can independently read and write data without the intervention of the host processor.
  • the register unit may include a data register, and the operation unit may perform command execution processing based on data which is written to the data register through the bus controller interface and the command on the basis of the decoding RESULT.
  • the host processor can write necessary data to the data register before the subprocessor starts executing processing.
  • the register unit may include an address register that stores address information of data which is read or written through the bus controller interface, and the address information of the address register may be written by the host processor through the bus controller interface.
  • the host processor can write the address information before the subprocessor starts executing processing.
  • a processing complete signal may be output.
  • the register unit may include a control register that includes a Run bit indicating that the subprocessor is under processing, and the Run bit may be cleared when the processing complete signal is output.
  • the register unit may include an operation parameter register, and when an operation parameter is written to the operation parameter register by the host processor, the operation unit may perform operation processing in accordance with the content set by the operation parameter.
  • the register unit may include an operation parameter register, and when an operation parameter is written to the operation parameter register in accordance with an operation parameter setting command of the subprocessor program, the operation unit may perform operation processing in accordance with the content set by the operation parameter.
  • an integrated circuit device including: the subprocessor described above; and the bus controller connected to the subprocessor and the host processor, the bus controller performs bus control between a memory in which the host processor program and the subprocessor program are stored, the host processor, and the subprocessor.
  • the host processor can concurrently perform processing that is not directly dependent on the processing during the execution processing of the subprocessor. As a result, the data processing can be executed at a high speed.
  • the integrated circuit device may further include the host processor.
  • the integrated circuit device may further include a clock generation circuit, and the clock generation circuit may stop supplying clocks to the host processor after a processing start command is executed and resume the supply of clocks to the host processor after the processing of the subprocessor is complete.
  • the host processor since the host processor does not need to operate during the execution processing of the subprocessor, it is possible to halt the operation of the host processor to thereby decrease the power consumption of the data processing device (integrated circuit device).
  • an electronic apparatus having the integrated circuit device described above.
  • FIG. 1 shows a basic configuration example of a data processing device.
  • FIG. 2 shows a configuration example of a subprocessor.
  • FIG. 3 shows a flowchart of a basic operation of the subprocessor.
  • FIG. 4 is a diagram illustrating the operation of the subprocessor.
  • FIG. 5 is a diagram illustrating the operation of the subprocessor.
  • FIG. 6 is a diagram illustrating the operation of the subprocessor.
  • FIG. 7 shows an example of a command code.
  • FIGS. 8A and 8B show an example of a bit configuration of a resister.
  • FIG. 9 shows a modified example of a data processing device.
  • FIG. 10 shows an example of an electronic apparatus.
  • FIG. 1 shows a basic configuration example of a data processing device (integrated circuit device) of the present embodiment.
  • a data processing device (integrated circuit device) 200 shown in FIG. 1 is a system in which a host processor 210 and a subprocessor 100 perform data processing in collaboration with each other, and includes the subprocessor 100 , the host processor 210 , a bus controller 220 , and a memory 230 .
  • the data processing device 200 is not limited to the configuration of FIG. 1 , but may be modified in various ways such that a part of the constituent elements may be omitted, other constituent elements may be substituted, or other constituent elements may be added.
  • the host processor 210 may not be included in the data processing device 200 (integrated circuit device), but the host processor 210 may be an external integrated circuit device.
  • the subprocessor (coprocessor) 100 fetches a command from a subprocessor program 250 stored in the memory 230 , decodes the fetched command, and performs targeting data processing. A command for the targeting data processing is described in the subprocessor program 250 .
  • the bus controller 220 is connected to the subprocessor 100 and the host processor 210 so as to perform bus control between the memory 230 , the host processor 210 , and the subprocessor 100 .
  • the subprocessor 100 when the subprocessor 100 receives a processing start command from the host processor 210 , the subprocessor 100 can execute data processing independently without the intervention of the host processor 210 . That is, the subprocessor 100 fetches a command from the subprocessor program 250 through the bus controller 220 , decodes the fetched command, and performs targeting data processing. The subprocessor 100 can read data necessary for processing from the memory 230 through the bus controller 220 and write operation results to the memory 230 . The ability to execute processing independently is attributable to the fact that the subprocessor 100 includes a bus controller interface 150 as will be described later.
  • the subprocessor 100 can execute the targeting data processing independently.
  • the host processor 210 can concurrently perform processing that is not directly dependent on the processing.
  • the data processing can be executed at a high speed.
  • the processing of the host processor 210 becomes unnecessary during the execution of the subprocessor 100 , since the operation of the host processor 210 can be halted, it is possible to decrease the power consumption of the data processing device (integrated circuit device) 200 .
  • the memory 230 is included in the data processing device (integrated circuit device) 200 , it is not essential to provide the memory 230 at an inner side of the data processing device (integrated circuit device) 200 .
  • the memory 230 may be at the outer side of the data processing device (integrated circuit device) 200 .
  • FIG. 2 shows a configuration example of the subprocessor 100 of the present embodiment.
  • the subprocessor 100 shown in FIG. 2 includes the bus controller interface 150 , a register unit 130 , a command decoding unit 140 , and an operation unit 160 .
  • the bus controller interface 150 includes a host interface 110 , a command fetch unit 120 , and a data interface.
  • the data interface includes an X-bus read unit 170 , a Y-bus read unit 180 , and a Z-bus write unit 190 .
  • the operation unit 160 , the X-bus read unit 170 , the Y-bus read unit 180 , and the Z-bus write unit 190 form an operation pipeline unit.
  • the subprocessor 100 of the present embodiment is not limited to the configuration of FIG. 2 , but may be modified in various ways such that a part of the constituent elements may be omitted, other constituent elements may be substituted, or other constituent elements may be added.
  • the bus controller interface 150 is composed of the host interface 110 , the command fetch unit 120 , the X-bus read unit 170 , the Y-bus read unit 180 , and the Z-bus write unit 190 as shown in FIG. 2 .
  • the function of the host interface may be provided to any one of the other four constituent elements.
  • the bus controller interface 150 performs interface processing between the bus controller 220 and the subprocessor 100 . Specifically, the bus controller interface 150 performs interface processing for connecting the subprocessor 100 and the bus controller 220 .
  • the bus controller interface 150 includes the host interface 110 that performs the interface processing between the host processor 210 and the subprocessor. Specifically, the host interface 110 performs the interface processing for allowing the host processor 210 to write or read a register value to or from the register unit 130 .
  • the bus controller interface 150 includes the data interface for performing reading or writing of data for execution of commands. Specifically, the data interface includes the X-bus read unit 170 , the Y-bus read unit 180 , and the Z-bus write unit 190 . The X-bus read unit 170 and the Y-bus read unit 180 perform reading of data, and the Z-bus write unit 190 performs writing of data.
  • the command fetch unit (program interface) 120 fetches the command from the subprocessor program 250 , and the command decoding unit 140 decodes the fetched command.
  • the operation unit 160 executes the command based on the decoding results.
  • the register unit 130 includes a control register CTL, a program counter PC, address register A 0 to A 3 , data registers D 0 and D 1 , an accumulator register ACC, and an operation parameter register OPR.
  • the register configuration of the register unit 130 is not limited to this.
  • the control register CTL has bits related to the control of transmission or the like of the start, halt, and interrupt signals for execution of the subprocessor 100 .
  • the program counter PC stores an address (program counter value) in which the subprocessor program 250 is stored.
  • the address registers A 0 to A 3 store the address information of data read or written through the data interface. The data necessary for processing are written to the data registers D 0 and D 1 through the host interface 110 (in a broader sense, the bus controller interface 150 ).
  • the accumulator register ACC temporarily stores the intermediate results of the operation in the operation unit 160 .
  • the operation parameter register OPR stores operation parameters for controlling various options of operation processing.
  • FIG. 3 is a flowchart illustrating a basic operation of the subprocessor 100 .
  • FIGS. 4 to 6 are block diagrams illustrating the basic operation of the subprocessor 100 .
  • respective steps S 1 to S 7 of the operation of the subprocessor 100 will be described with reference to FIGS. 3 to 6 .
  • step S 1 the host processor 210 sets an address (program counter value) indicating a storage destination of the subprocessor program 250 to the program counter PC through the host interface 110 (in a broader sense, the bus controller interface 150 ). Specifically, the host processor 210 supplies a register address and a program counter value of the program counter PC to the host interface 110 together with a write control signal, and the host interface 110 sets the program counter value to the program counter PC.
  • step S 2 the host processor 210 sets necessary address information to the address registers A 0 to A 3 through the host interface 110 (in a broader sense, the bus controller interface 150 ).
  • the address information is the address indicating the location of input data and the storage destination of output data, which are processed by the subprocessor 100 .
  • the host processor 210 sets data necessary for the data processing performed by the subprocessor 100 to the data registers D 0 and D 1 as necessary.
  • step S 3 the host processor 210 issues a processing start command. Specifically, the host processor 210 writes “1” to the Run bit of the control register CTL through the host interface 110 (in a broader sense, the bus controller interface 150 ).
  • step S 4 the subprocessor 100 fetches the command from the subprocessor program 250 , decodes the fetched command, and starts executing processing.
  • the command fetch unit 120 outputs the program counter value to the bus controller 220 as a command address and receives and fetches a command code from the bus controller 220 .
  • the command fetch unit 120 updates the program counter value with the next command address.
  • the command decoding unit 140 decodes the command code to generate a necessary control signal and controls the operation unit 160 .
  • the operation pipeline unit performs the following operation processing, for example.
  • the X-bus read unit 170 and the Y-bus read unit 180 read data from addresses (addresses on the memory 230 ) indicated by the address registers A 0 to A 3 which are designated by the command code based on the control signal supplied from the command decoding unit 140 and supply the data to the operation unit 160 .
  • the operation unit 160 performs an operation based on the command code and outputs the operation results to the Z-bus write unit 190 .
  • the Z-bus write unit 190 writes the operation results to the addresses (the addresses on the memory 230 ) indicated by the address registers A 0 to A 3 which are designated by the command code.
  • a value “1” is set to the Run bit of the control register CTL during the period when the subprocessor 100 performs processing. That is, the value “1” set to the Run bit implies that the subprocessor 100 is executing processing.
  • step S 5 the subprocessor 100 fetches and decodes a processing end command.
  • the processing end command is an EXIT command, or the like, for example, and is a command described in the subprocessor program 250 as indicated by B 6 in FIG. 6 (for example, the command is described in a program processing end step of the subprocessor program 250 ).
  • this command is fetched, the subprocessor 100 ends the operation processing.
  • step S 6 the subprocessor 100 clears (namely, writes 0 to) a predetermined bit (the Run bit) of the control register CTL.
  • step S 7 the subprocessor 100 outputs a processing complete signal.
  • a value “1” is set to an IRQ bit (interrupt request bit) of the control register CTL.
  • the processing complete signal is output.
  • the subprocessor 100 can execute data processing independently.
  • the subprocessor is provided with the host interface 110 (in a broader sense, the bus controller interface 150 ) for performing interface processing between the host processor 210 and the subprocessor through the bus controller 220 or the like. That is, the subprocessor is provided with the host interface 110 which is generally not provided in a subprocessor of this type. Moreover, the program counter value indicating the storage destination of the subprocessor program and the processing start command of the subprocessor are written to the register unit 130 through the host interface 110 . Thus, after the host processor 210 issues a processing start command, the subprocessor 100 can independently load the subprocessor program 250 from the address (the program counter value) that is indicated by the program counter PC and execute targeting data processing. Moreover, the subprocessor 100 can independently read and write data from and to the address indicated by the address register that is designated by the command code.
  • the subprocessor 100 of the present embodiment can execute targeting data processing independently without the intervention of the host processor 210 .
  • the host processor 210 can perform processing that is not directly dependent on the processing.
  • the data processing can be executed at a high speed.
  • the processing of the host processor 210 becomes unnecessary during the execution of the subprocessor 100 , since the operation of the host processor 210 can be halted, it is possible to decrease the power consumption of the data processing device (integrated circuit device) 200 . That is, in the present embodiment, by providing the bus controller interface 150 to the subprocessor 100 , independent data processing by the subprocessor 100 , a reduction in power consumption, and the like are made possible.
  • FIG. 7 shows an example of the command code of the subprocessor 100 of the present embodiment.
  • the command code for operations such as, for example, addition, subtraction, or multiplication has a configuration shown in FIG. 7 .
  • An operation code OPC indicates the type of operation, and an operand indicates an input and output method of data. Furthermore, as shown in FIG. 7 , the operand is made up of fields XS, YS, and ZS for designating data input and output address registers and fields XDP, YDP, and ZDP for designating displacements for updating the address registers after accessing.
  • the fields XS and YS designate the address registers A 0 to A 3 storing the addresses on the memory when the X-bus read unit 170 and the Y-bus read unit 180 read data from the memory 230 .
  • the field ZS designates the address registers A 0 to A 3 storing the destination addresses on the memory to which the Z-bus write unit 190 writes the operation results.
  • the operand fields may designate immediate input data and designate the data registers D 0 and D 1 of the register unit 130 as well as inputting and outputting data to and from the memory 230 .
  • FIGS. 8(A) and 8(B) show an example of a bit configuration of the register of the subprocessor 100 of the present embodiment.
  • FIG. 8(A) shows the configuration of the control register CTL
  • FIG. 8(B) shows the configuration of the operation parameter register OPR.
  • the control register CTL includes a Run bit and an IRQ bit (interrupt request bit).
  • the execution of the subprocessor 100 starts when the host processor 210 writes “1” to the Run bit of the control register CTL through the host interface 110 .
  • the value “1” is set to the Run bit during execution of processing.
  • a value “1” is set to the IRQ bit (interrupt request bit).
  • a processing complete signal is output.
  • the operation parameter register OPR stores operation parameters for controlling various options of operation processing. For example, an arithmetic right shift control parameter controls an arithmetic right shift when writing operation results to a memory.
  • a clipping control parameter controls clipping when writing operation results to a memory.
  • a conditional memory writing control parameter controls memory writing which requires conditional determination.
  • operation parameters are written by the host processor 210 through the host interface 110 (in a broader sense, the bus controller interface 150 ), for example.
  • the operation parameters are written by an operation parameter setting command of the subprocessor program 250 . That is, the content of the operation parameter can be changed by the operation parameter setting command described in the subprocessor program 250 .
  • the subprocessor 100 of the present embodiment is provided with the host interface 110 , it is possible, for example, to set an initial value or the like of the operation parameter through the host interface 110 . Moreover, the content of the operation parameter can be changed as needed by the operation parameter setting command described in the subprocessor program 250 . In this way, flexible option control by the operation parameter can be realized.
  • FIG. 9 shows a modified example of the data processing device (integrated circuit device) of the present embodiment.
  • a data processing device (integrated circuit device) 200 of FIG. 9 includes a clock generation circuit 260 in addition to the constituent elements shown in FIG. 1 .
  • the subprocessor 100 of the present embodiment can execute targeting data processing independently without the intervention of the host processor 210 .
  • the host processor 210 can halt its operation in a period when the subprocessor 100 is executing the data processing.
  • the host processor 210 may resume its operation after the subprocessor 100 completes the processing.
  • the subprocessor 100 operates and executes data processing independently.
  • the host processor 210 issues a HALT command or the like to halt the supply of clocks from the clock generation circuit 260 , whereby the host processor 210 can halt its operation.
  • the host processor 210 is halted, and only the subprocessor 100 operates, it is possible to prevent a situation in which unnecessary power is consumed by the host processor 210 .
  • the host processor 210 is unable to receive a processing complete signal from the subprocessor 100 . Therefore, the subprocessor 100 outputs the processing complete signal to the clock generation circuit 260 rather than to the host processor 210 , and the clock generation circuit 260 having received this signal resumes the supply of clocks to the host processor 210 .
  • the host processor 210 in which the supply of clocks is resumed can restart its operation and execute operation processing or the like using the results of the data processing by the subprocessor 100 , for example.
  • FIG. 10 shows an example of an electronic apparatus including the data processing device (integrated circuit device) of the present embodiment.
  • An electronic apparatus 400 of FIG. 10 includes a sensor 310 , a detection circuit 320 , an A/D converter 330 , and a processing unit 340 .
  • the processing unit 340 is realized by the integrated circuit device 200 which is the data processing device of the present embodiment.
  • the detection circuit 320 and the A/D converter 330 may be integrated into the integrated circuit device 200 to form one chip.
  • the electronic apparatus 400 is a pulse meter, a pedometer, a digital camera, or the like, for example.
  • the sensor 310 is a gyro sensor, an acceleration sensor, a photo sensor, a pressure sensor, or the like, and a sensor corresponding to the purpose of the electronic apparatus 400 is used.
  • the detection circuit 320 amplifies the output signal (sensor signal) from the sensor 310 and removes noise using a filter.
  • the A/D converter 330 converts the amplified signal into a digital signal and outputs the digital signal to the processing unit 340 .
  • the processing unit 340 executes necessary digital signal processing on the digital signal from the A/D converter 330 . Moreover, gain control of the detection circuit 320 or the like may be performed. Here, the digital signal processing performed by the processing unit 340 may include Fourier transform or the like, for example.
  • the detection circuit 320 needs to perform an operation of detecting the desired signal under a low-noise environment. Moreover, in order to extract the desired signal from a very small amplitude sensor signal, data processing with high processing load such as, for example, fast Fourier transform is required.
  • data processing with high processing load for extracting a desired signal from a very small amplitude sensor signal can be executed by the subprocessor 100 having high operation processing capability at high speed.
  • the subprocessor 100 having high operation processing capability at high speed.
  • FIG. 9 by putting the host processor 210 into a halted state, it is possible to prevent noise from the host processor 210 from having an adverse effect on the detection circuit 320 .
  • the host processor 210 can be put into a halted state during the operation of the subprocessor 100 , or conversely, the subprocessor 100 can be put into a halted state during the operation of the host processor 210 .
  • the subprocessor 100 can be put into a halted state during the operation of the host processor 210 .

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