US9589921B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
US9589921B2
US9589921B2 US14/773,817 US201414773817A US9589921B2 US 9589921 B2 US9589921 B2 US 9589921B2 US 201414773817 A US201414773817 A US 201414773817A US 9589921 B2 US9589921 B2 US 9589921B2
Authority
US
United States
Prior art keywords
wiring
electrodes
semiconductor chip
pad electrodes
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/773,817
Other languages
English (en)
Other versions
US20160027754A1 (en
Inventor
Mitsuaki Katagiri
Yu Hasegawa
Satoshi Isa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Longitude Licensing Ltd
Original Assignee
PS4 Luxco SARL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PS4 Luxco SARL filed Critical PS4 Luxco SARL
Publication of US20160027754A1 publication Critical patent/US20160027754A1/en
Application granted granted Critical
Publication of US9589921B2 publication Critical patent/US9589921B2/en
Assigned to PS5 LUXCO S.A.R.L. reassignment PS5 LUXCO S.A.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PS4 LUXCO S.A.R.L.
Assigned to LONGITUDE SEMICONDUCTOR S.A.R.L. reassignment LONGITUDE SEMICONDUCTOR S.A.R.L. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: PS5 LUXCO S.A.R.L.
Assigned to LONGITUDE LICENSING LIMITED reassignment LONGITUDE LICENSING LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LONGITUDE SEMICONDUCTOR S.A.R.L.
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0235—Shape of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02375—Top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03912—Methods of manufacturing bonding areas involving a specific sequence of method steps the bump being used as a mask for patterning the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05014—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0501—Shape
    • H01L2224/05012—Shape in top view
    • H01L2224/05015—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0605—Shape
    • H01L2224/06051—Bonding areas having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/06102—Disposition the bonding areas being at different heights
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13007—Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13021—Disposition the bump connector being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13026—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body
    • H01L2224/13028—Disposition relative to the bonding area, e.g. bond pad, of the semiconductor or solid-state body the bump connector being disposed on at least two separate bonding areas, e.g. bond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1405—Shape
    • H01L2224/14051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/14177—Combinations of arrays with different layouts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1451—Function
    • H01L2224/14515—Bump connectors having different functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06596—Structural arrangements for testing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Definitions

  • the present invention relates to a semiconductor device, and more particularly relates to a semiconductor device provided with a semiconductor chip and a wiring structure provided on a main surface thereof.
  • WLP wafer level packages
  • Patent Document 1 Japanese Patent Application Laid-open No. 2012-33613.
  • DRAM Dynamic Random Access Memory
  • the ability of the power supply voltage within the semiconductor chip has become more important than before.
  • the method of increasing the number of external terminals for the power supply can be considered, but in many cases the number and arrangement of external terminals is determined in advance by standards and the like, so it is difficult to freely increase the number of external terminals for power supply. Also, an effect cannot be expected when stabilizing internal power supply voltage that is different from an external power supply voltage supplied from the outside, even if the number of external terminals for power supply is increased.
  • the semiconductor device includes: a semiconductor chip that includes a plurality of first pad electrodes and a plurality of second pad electrodes; and a wiring structure provided on the semiconductor chip, characterized in that the wiring structure includes a plurality of external terminals, a plurality of wiring patterns that electrically connect the plurality of external terminals and the plurality of first pad electrodes, and bridge wiring that is not electrically connected to any of the plurality of external terminals within the wiring structure, but that electrically connects in a shared fashion the plurality of second pad electrodes.
  • the bridge wiring provided in the wiring structure supplements the wiring within the semiconductor chip, so it is possible to reduce the impedance of specific wiring.
  • FIG. 1 is a schematic cross-sectional view for describing the structure of a semiconductor device 10 according to a first embodiment of the present invention
  • FIG. 2 is a schematic plan view for describing the layout of bump electrodes 110 provided in a semiconductor chip 100 ;
  • FIG. 3 is a schematic plan view showing pad electrodes 120 ;
  • FIG. 4 is a schematic cross-sectional view along the line A-N shown in FIG. 2 ;
  • FIG. 5 is a schematic cross-sectional view for describing the shape of bump electrodes 110 a to 110 c;
  • FIG. 6 is a schematic cross-sectional view along the line B-B′ shown in FIG. 5 ;
  • FIG. 7 is a schematic cross-sectional view showing the shape of the bump electrode 110 X;
  • FIG. 8 is a schematic cross-sectional view for describing the melted state of the solder layer 113 ;
  • FIG. 9 is a schematic cross-sectional view showing the shape of a modified example of the bump electrode 110 X;
  • FIG. 10 is a schematic cross-sectional view showing the shape of a another modified example of the bump electrode 110 X;
  • FIG. 11 is a schematic cross-sectional view for describing the conductor pattern formed on a first surface 210 a of the insulating substrate 210 ;
  • FIG. 12 shows an example of the layout of external terminals 260 provided on a second surface 210 b of the insulating substrate 210 ;
  • FIG. 13 is a schematic view for describing an example of the connection relationship between the semiconductor chip 100 and the wiring substrate 200 ;
  • FIG. 14 is a schematic view for describing another example of the connection relationship between the semiconductor chip 100 and the wiring substrate 200 ;
  • FIG. 15 is a process diagram for describing the process of manufacturing the bump electrode 110 ;
  • FIG. 16 is a process diagram for describing the process of manufacturing the bump electrode 110 ;
  • FIG. 17 is a process diagram for describing the process of flip chip mounting the semiconductor chip 100 on the wiring substrate 200 ;
  • FIG. 18 is a schematic cross-sectional view for describing the structure of the semiconductor chip 100 a used in a second embodiment
  • FIG. 19 is a schematic plan view for describing the shape of the bump electrodes 110 a to 110 c;
  • FIG. 20 is a schematic cross-sectional view along the line C-C′ shown in FIG. 19 ;
  • FIG. 21 is a schematic plan view for describing a first example of the relationship between the pad electrodes 120 b and the wiring layer of the uppermost layer;
  • FIG. 22 is a schematic plan view for describing a second example of the relationship between the pad electrodes 120 b and the wiring layer of the uppermost layer;
  • FIG. 23 is a schematic cross-sectional view for describing the structure of the semiconductor chip 100 b used in a third embodiment
  • FIG. 24 is a schematic cross-sectional view for describing the structure of a semiconductor device 20 ;
  • FIG. 25 is a schematic plan view for describing an example of the bumps 170 c on the reverse surface of the semiconductor chip 100 b short-circuited by the bridge wiring 290 a;
  • FIG. 26 is a schematic plan view showing the layout of the main surface of the semiconductor chip 100 c used in a fourth embodiment
  • FIG. 27 is a schematic plan view for describing the conductor pattern formed on the wiring substrate 200 b;
  • FIG. 28 is a schematic cross-sectional view for describing the structure of a semiconductor device 40 according to a fifth embodiment of the present invention.
  • FIG. 29 is a schematic plan view showing the layout of bridge wiring 290 c formed in the wiring layer 320 ;
  • FIG. 30 is a schematic view for describing the connection relationship between the semiconductor chip 100 e and the wiring substrate 200 d.
  • FIG. 1 is a schematic cross-sectional view for describing the structure of a semiconductor device 10 according to a first embodiment of the present invention.
  • the semiconductor device includes a semiconductor chip 100 , and a wiring substrate 200 on which the semiconductor chip 100 is flip chip mounted.
  • the semiconductor chip 100 is a single-chip device in which a plurality of elements such as transistors and the like are provided on a semiconductor substrate made from silicon (Si) or the like.
  • Si silicon
  • There is no particular limitation on the type of semiconductor chip 100 and it may be a memory device such as a Dynamic Random Access Memory (DRAM) or the like, or a logic type device such as a Central Processing Unit (CPU) or the like, or an analog type device such as a sensor or the like.
  • DRAM Dynamic Random Access Memory
  • CPU Central Processing Unit
  • the wiring substrate 200 is a circuit board that functions as a wiring structure, and includes for example an insulating substrate 210 made from glass epoxy 0.2 mm thick, connecting electrodes 220 formed on a first surface 210 a of the insulating substrate 210 , and a land pattern 230 formed on a second surface 210 b of the insulating substrate 210 .
  • the connecting electrodes 220 and the land pattern 230 are connected together via a wiring pattern 240 provided on the insulating substrate 210 .
  • the wiring pattern 240 may be formed on either the first or the second surface of the insulating substrate 210 , or may be formed in an internal layer of the insulating substrate 210 .
  • the parts where the connecting electrodes 220 and the land pattern 230 are not formed on the first and the second surfaces of the insulating substrate 210 are covered with a solder resist 250 .
  • the connecting electrodes 220 are electrodes to which bump electrodes 110 provided on the semiconductor chip 100 are joined.
  • external terminals 260 made from solder balls are connected to the land pattern 230 .
  • Underfill 270 is filled between the wiring substrate 200 and the semiconductor chip 100 , and sealing resin 280 is provided covering the semiconductor chip 100 .
  • the first type of bump electrode 110 a is provided in substantially the center region of the semiconductor chip 100 , electrically connected to the external terminals 260 via the wiring pattern 240 .
  • the second type of bump electrode 110 b is provided in the vicinity of the outer peripheral region of the semiconductor chip 100 , electrically connected to the external terminals 260 via the wiring pattern 240 .
  • the third type of bump electrode 110 c is provided in the vicinity of the outer peripheral region of the semiconductor chip 100 , but is not electrically connected to any of the external terminals 260 .
  • the fourth type of bump electrode 110 d is a dummy bump electrode provided in the vicinity of the outer peripheral region of the semiconductor chip 100 , and is not electrically connected to any of the external terminals 260 .
  • the pad electrodes 120 are provided at the base of the bump electrodes 110 a to 110 c , but pad electrodes are not provided corresponding to the dummy bump electrodes 110 d , which are formed on the top surface of a protective film 130 that covers the surface layer of the semiconductor chip 100 .
  • FIG. 2 is a schematic plan view for explaining the layout of the bump electrodes 110 provided on the semiconductor chip 100 .
  • FIG. 3 is a schematic plan view showing the pad electrodes 120 at the base of the bump electrodes 110 .
  • FIG. 4 is a schematic cross-sectional view along the line A-N in FIG. 2 .
  • the bump electrodes 110 a are arranged in two rows in the X direction in substantially the center in the Y direction of the semiconductor chip 100 .
  • the bump electrodes 110 a are used for input and output of signals and for supplying the external power supply voltage.
  • the pad electrodes 120 a corresponding to the bump electrodes 110 a have a slightly larger plan size than the bump electrodes 110 a.
  • the bump electrodes 110 b to 110 d are arranged in the vicinity of the outer peripheral region of the semiconductor chip 100 .
  • the bump electrodes 110 b are used for supplying the external power supply voltage
  • the bump electrodes 110 c are used for connecting to bridge wiring that is described later.
  • the pad electrodes 120 b , 120 c corresponding to the bump electrodes 110 b , 110 c have a slightly larger plan size than the corresponding bump electrodes 110 b , 110 c .
  • the bump electrodes 110 b , 110 c perform the role of increasing the connection strength between the semiconductor chip 100 and the wiring substrate 200 .
  • the semiconductor chip 100 made from silicon or the like and the wiring substrate 200 made from resin or the like have coefficients of thermal expansion that are greatly different from each other, so changes in temperature produce warping of the wiring substrate 200 , and there is a possibility that the semiconductor chip 100 will peel away from the wiring substrate 200 .
  • the bump electrodes 110 b , 110 c are arranged in the vicinity of the outer peripheral region of the semiconductor chip 100 where peeling can easily occur, to increase the connection strength between the two.
  • the dummy bump electrodes 110 d are used solely for the purpose of increasing the connection strength. Therefore, as shown in FIGS. 3 and 4 , pad electrodes corresponding to the dummy bump electrodes 110 d are not necessary.
  • FIG. 5 is a schematic cross-sectional view for explaining the shape of the bump electrodes 110 a to 110 c
  • FIG. 6 is a schematic cross-sectional view along the line B-B′ shown in FIG. 5 .
  • the plan shape of the bump electrodes 110 a is square, and in contrast the plan shape of the bump electrodes 110 b , 110 c is circular.
  • the plan shape of the dummy bump electrodes 110 d is also circular.
  • the length of one side of the bump electrode 110 a is designed to be almost equal to the diameter of the bump electrodes 110 b , 110 c . Therefore, the cross-sectional area in a direction parallel to the main surface of the semiconductor chip 100 is greater in the bump electrodes 110 a than the bump electrodes 110 b , 110 c .
  • the bump electrodes 110 a with a square shape and that are arranged at a predetermined interval (pitch) can be arranged more densely and with lower resistance than the bump electrodes 110 b , 110 c.
  • the plan shape of the pad electrodes 120 a corresponding to the bump electrodes 110 a is also square, and its size is larger than that of the bump electrodes 110 a . Therefore, the outer peripheral portion of the pad electrodes 120 a is not covered by the bump electrodes 110 a .
  • the plan shape of the pad electrodes 120 b , 120 c corresponding to the bump electrodes 110 b , 110 c is square, but its size is smaller than that of the bump electrodes 110 b , 110 c . Therefore, the pad electrodes 120 b , 120 c are covered by the bump electrodes 110 b , 110 c on all surfaces.
  • the contact resistance between the bump electrodes 110 a and the pad electrodes 120 a is lower than the contact resistance between the bump electrodes 110 b , 110 c and the pad electrodes 120 b , 120 c , so it is possible to send and receive signals and provide the power supply via the pad electrodes 120 a with low resistance.
  • the pad electrodes 120 a One reason for designing the area of the pad electrodes 120 a to be large is to enable contact by a tester probe carrying out tests in the wafer state. In contrast the pad electrodes 120 b , 120 c are not contacted by the probe during testing in the wafer state, so their area is designed to be smaller. Also, another reason is the pad electrodes 120 b , 120 c are arranged in the vicinity of the outer peripheral region of the semiconductor chip 100 where there is no pad area, as shown in FIG. 3 , so it would be difficult to provide pads with large area in the wiring layer.
  • the plan shape of the bump electrodes 110 a is square, and in contrast the plan shape of the bump electrodes 110 b to 110 d is circular.
  • the reason the plan shape of the bump electrodes 110 a is square is because when a plurality of the bump electrodes 110 a is arranged at a predetermined pitch, it is possible to maximize the cross-sectional area in a direction parallel to the main surface of the semiconductor chip 100 . In this way it is possible to send and receive signals and provide the power supply via the bump electrodes 110 a at low resistance.
  • the reason the plan shape of the bump electrodes 110 b to 110 d is circular is in order to increase the connection strength.
  • the plan shape of the bump electrodes 110 b to 110 d was square, when warping occurs on the wiring substrate 200 , stresses are concentrated on the corner portions of the bump electrodes, so peeling can easily occur from this location.
  • the plan shape of the bump electrodes 110 b to 110 d is circular, the stress is not concentrated in a particular location, so even if warping occurs in the wiring substrate 200 peeling does not easily occur.
  • the bump electrodes 110 a to 110 d are designed as described above.
  • the plan shape of the bump electrodes 110 b to 110 d is not limited to circular, but any shape in which stresses do not easily concentrate is desirable. For example, polygons such as a hexagonal shape or an octagonal shape in which the internal angles are each obtuse angles are desirable.
  • the bump electrodes 110 a to 110 c include an under barrier metal (UBM) layer 111 that contacts the pad electrodes 120 a to 120 c , a pillar portion 112 that stands on the UBM layer 111 , and a solder layer 113 provided on the top end surface 112 a of the pillar portion 112 .
  • the UBM layer 111 is made from, for example, a stacked film of Ti and Cu, and the pillar portion 112 is made from Cu for example.
  • the dummy bump electrodes 110 d do not have corresponding pad electrodes 120 , but otherwise have the same structure as the bump electrodes 110 a to 110 c shown in FIG. 6 .
  • the pillar portion 112 of the bump electrodes 110 a , 110 b , 110 c , and 110 d are produced by plating, they are formed simultaneously, so the position of the top end surface 112 a of the pillar portion 112 of the insulating film bump electrode 110 d is higher than the top end surface 112 a of the pillar portion 112 of the bump electrodes 110 a , 110 b , 110 c formed on the pad electrodes 120 a , 120 b , 120 c .
  • the pillar portion 112 of the bump electrode 110 d is formed with a smaller diameter than the pillar portion 112 of the other bump electrodes 110 a , 110 b , 110 c .
  • the diameter of the pillar portion 112 of the bump electrode 110 d By forming the diameter of the pillar portion 112 of the bump electrode 110 d smaller, the area of the top end surface 112 a of the pillar portion 112 is smaller than the area of the top end surface 112 a of the pillar portion 112 of the other bump electrodes 110 a , 110 b , 110 c , so the height after reflow of the solder bump formed thereupon is lower, and the height of the pillar portion 112 can be absorbed. In this way, the heights of the bump electrodes 110 a , 110 b , 110 c , 110 d including the solder layer 113 after reflow are substantially the same.
  • FIG. 7 is a schematic cross-sectional view showing the shape of an improved bump electrode 110 X.
  • the cross-section of the bump electrode 110 X shown in FIG. 7 is an inverted trapezium, and therefore the angle formed between the top end surface 112 a and the side surface 112 b of the pillar portion 112 is an acute angle. If a bump electrode 110 X having such a shape is used, it is difficult for the solder layer 113 that has melted due to reflow to wrap around the side surface 112 b of the pillar portion 112 when flip chip connecting the semiconductor chip 100 to the wiring substrate 200 . The melted solder layer 113 deforms into a hemispherical shape as shown in FIG.
  • solder layer 113 due to surface tension, but if the solder layer 113 is thick, the melted solder layer 113 spills from the top end surface 112 a of the pillar portion 112 , and wraps around the side surface 112 b . However, if the angle formed between the top end surface 112 a and the side surface 112 b is an acute angle, it is difficult for the solder layer 113 to wrap around in this way, so defective connections or short circuits due to spilling of the solder layer 113 can be prevented.
  • the side surface 112 b be completely slanted, but the top portion only of the side surface 112 b where it contacts the top end surface 112 a may be slanted, and the remainder may be vertical, as shown in FIG. 9 .
  • the upper portion of the side surface 112 b that contacts the top end surface 112 a may be formed slanting so that the diameter increases in the upward direction
  • the lower portion of the side surface 112 b that contacts the UBM layer 111 may be formed slanting so that the diameter increases in the downward direction so that the side surface 112 b has a spindle shape.
  • the angle formed between the top end surface 112 a of the pillar portion 112 and the portion of the side surface 112 b in contact with the top end surface 112 a is an acute angle.
  • FIG. 11 is a schematic plan view for explaining the conductor pattern formed on the first surface 210 a of the insulating substrate 210 .
  • the broken line 100 X shown in FIG. 11 is the area where the semiconductor chip 100 is mounted.
  • a plurality of connecting electrodes 220 , a plurality of wiring patterns 240 , and two bridge wirings 290 are provided on the first surface 210 a of the insulating substrate 210 .
  • the connecting electrodes 220 a connected to the bump electrodes 110 a are connected to through hole conductors 221 via the wiring pattern 240 .
  • the through hole conductors 221 are conductors provided passing through the insulating substrate 210 , and are connected to a land pattern 230 and external terminals 260 provided on the second surface 210 b of the insulating substrate 210 .
  • FIG. 12 shows an example of the layout of the external terminals 260 provided on the second surface 210 b of the insulating substrate 210 .
  • a wiring pattern 240 that connects the through hole conductors 221 and the land pattern 230 (external terminals 260 ) is provided on the second surface 210 b of the insulating substrate 210 .
  • the connecting electrodes 220 c connected to the bump electrodes 110 c are connected together via the bridge wiring 290 .
  • the bridge wiring 290 is not connected to the other wiring pattern 240 , and therefore is not connected to any of the external terminals 260 .
  • the plurality of bump electrodes 110 c are electrically short-circuited together by the bridge wiring 290 .
  • the bump electrodes 110 b and the dummy bump electrodes 110 d are directly connected to a large area power supply pattern 241 provided on the first surface 210 a of the insulating substrate 210 .
  • FIG. 13 is a schematic view for explaining the connection relationship between the semiconductor chip 100 and the wiring substrate 200 .
  • the semiconductor chip 100 includes an internal voltage generation circuit 140 that generates an internal power supply voltage VINT.
  • the internal voltage generation circuit 140 receives external power supply voltages VDD, VSS supplied via the external terminals 260 , and generates the internal power supply voltage VINT based on these.
  • the internal power supply voltage VINT is a voltage generated within the semiconductor chip 100 and is not supplied from the outside, so the capacity of the internal voltage generation circuit 140 is designed based on the load of the circuits using the internal power supply voltage VINT.
  • the voltage reduction of the internal power supply voltage VINT might be large. This voltage reduction is designed to be reduced as much as possible by configuring the power supply wiring network within the semiconductor chip 100 in a mesh form, but in advanced semiconductor chips 100 with high speed and high function it may not be possible to sufficiently reduce this voltage reduction.
  • the wiring that supplies this internal power supply voltage VINT is bypassed by the bridge wiring 290 .
  • the bridge wiring 290 is wiring provided on the wiring substrate 200 side, so its film thickness is extremely small compared with the wiring provided within the semiconductor chip 100 . Therefore, the bridge wiring 290 has extremely low resistance, and by bypassing the wiring that supplies the internal power supply voltage VINT using the bridge wiring 290 , the voltage reduction of the internal power supply voltage VINT can be greatly reduced.
  • the wiring that is bypassed using the bridge wiring 290 in the present invention is not limited to wiring that supplies the internal power supply voltage VINT.
  • the wiring that supplies the external power supply voltage VSS within the semiconductor chip 100 may be connected to the bump electrodes 110 c , and in this way the wiring can be bypassed using the bridge wiring 290 .
  • circuits 150 A that are easily affected by power supply noise arranged in a dispersed manner
  • circuit 150 B that is a source of generation of power supply noise
  • the power supply wiring in the vicinity of each of the circuits 150 A is connected to the bump electrodes 110 c , and in this way the power supply wiring is bypassed between the plurality of circuits 150 A, the effect of the noise can be reduced.
  • FIGS. 15A to 15D and FIGS. 16A to 16C are process diagrams for describing a process of manufacturing the bump electrodes 110 a , 110 c.
  • the pad electrodes 120 a , 120 c are formed by patterning the wiring layer of the uppermost layer included in the semiconductor chip 100 .
  • Preferably aluminum is used as the material of the pad electrodes 120 a , 120 c .
  • these are covered with a protective film 130 configured from a passivation film or a polyimide film, so that a portion of the pad electrodes 120 a , 120 c is exposed.
  • the reason that the sizes of the pad electrode 120 a and the pad electrode 120 c are different is because of the difference in the necessity for contact by the tester probe, as described previously.
  • the test using the probe is carried out in the state as shown in FIG. 15A .
  • the UBM film 111 is formed over the whole surface. Forming the UBM film 111 can be carried out by sputtering Ti and Cu in this order.
  • a resist film 160 is formed on the surface of the UBM film 111 . There is no particular limitation on the thickness of the resist film 160 , but it can be for example about 20 ⁇ m.
  • a mask M in which openings having a predetermined pattern are formed is disposed on the semiconductor chip 100 , and by carrying out exposure to light and developing, openings 160 a , 160 c are formed in the resist film 160 .
  • a positive resist is shown on the drawings, but a negative resist may also be used.
  • the openings 160 a , 160 c are provided at the positions where the bump electrodes 110 a , 110 c are to be formed.
  • the internal walls of the openings 160 a , 160 c are substantially vertical, but the internal walls of the openings 160 a , 160 c can be slanted by adjusting the focus position during light exposure or the like.
  • the pillar portions 112 and the solder layer 113 are formed on the UBM layer 111 exposed by the openings 160 a , 160 c by electroplating. Then, after the resist film 160 is removed as shown in FIG. 16B , the portion of the UBM film 111 that is not covered with the pillar portions 112 is removed, and the bump electrodes 110 a , 110 c are completed. Note that if the internal walls of the openings 160 a , 160 c are slanted by adjusting the focus position or the like, the cross-sectional shape of the bump electrodes 110 a , 110 c will reflect this shape, and bump electrodes 110 X as shown in FIGS. 7 to 10 can be manufactured.
  • the bump electrodes 110 a , 110 c were formed simultaneously, but the other bump electrodes 110 b , 110 d can also be formed at the same time.
  • there are no pad electrodes 120 corresponding to the dummy bump electrodes 110 d so they are formed on the protective film 130 .
  • reflow of the semiconductor chip 100 is carried out at a predetermined temperature, for example about 240° C. and the solder layer 113 is melted, and the solder layer 113 takes a hemispherical shape due to surface tension.
  • each individual semiconductor chip 100 may be carried out on each individual semiconductor chip 100 , but normally it will be carried out in one operation on a plurality of semiconductor chips 100 in the wafer state. Also, after the process as described above has been completed, the individual semiconductor chips 100 are obtained by dicing the wafer. The individual semiconductor chips 100 are flip chip mounted on the wiring substrate 200 as described next.
  • FIGS. 17A to 17E are process diagrams for describing the process of flip chip mounting the semiconductor chip 100 onto the wiring substrate 200 .
  • a large area insulating substrate 210 X capable of mounting a plurality of semiconductor chips 100 is prepared, and the connecting electrodes 220 , the land pattern 230 , the solder resist 250 , and so on are formed on both sides thereof.
  • the broken line D shown in FIG. 17A is the dicing line where cutting is carried out in the next process.
  • the semiconductor chips 100 are connected by flip chip bonding to the mounting regions defined on the surface of the insulating substrate 210 .
  • the flip chip bonding is carried out in a positioned state so that the bump electrodes 110 provided on the semiconductor chip 100 and the connecting electrodes 220 provided on the insulating substrate 210 are joined.
  • the reverse surface of the semiconductor chip 100 is held by suction using a bonding tool that is not shown on the drawings, and the bump electrodes 110 and the connecting electrodes 220 are joined at a temperature of about 240° C. while a load is applied. Then, the gap between the wiring substrate 200 and the semiconductor chip 100 is filled with underfill 270 .
  • the supplied underfill material fills the gap between the wiring substrate 200 and the semiconductor chip 100 by capillary action.
  • underfill 270 After filling with underfill 270 , curing is carried out at a predetermined temperature of, for example, about 150° C., the underfill 270 hardens, and a fillet is formed as shown in FIG. 17B .
  • a predetermined temperature for example, about 150° C.
  • NCP non conductive paste
  • the whole surface of the wiring substrate 200 is covered with sealing resin 280 so that the semiconductor chip 100 is embedded, then as shown in FIG. 17D the external terminals 260 made from solder balls are mounted on the land pattern 230 . Then as shown in FIG. 17E , the wiring substrate 200 is cut along the dicing line D, and a plurality of the semiconductor devices 10 can be obtained.
  • the semiconductor device 10 is provided with bridge wiring 290 in the wiring substrate 200 , so the plurality of pad electrodes 120 c provided in the semiconductor chip 100 is bypassed by the bridge wiring 290 .
  • the impedance of the wiring connected to the pad electrodes 120 c for example the wiring that supplies the internal power supply voltage, can be greatly reduced.
  • FIG. 18 is a schematic cross-sectional view for explaining the structure of a semiconductor chip 100 a used in the second embodiment.
  • the semiconductor chip 100 a used in the present embodiment two very small pad electrodes 120 b , 120 c are provided at the base of the bump electrodes 110 b , 110 c respectively.
  • the semiconductor chip 100 is the same as the semiconductor chip 100 used in the first embodiment, so the same elements are given the same reference symbols, and duplicated descriptions are omitted.
  • the wiring substrate 200 used in the present embodiment is the same as that of the first embodiment.
  • FIG. 19 is a schematic plan view for describing the shape of the bump electrodes 110 a to 110 c
  • FIG. 20 is a schematic cross-sectional view along the line C-C′ shown in FIG. 19 .
  • the plan shapes of the bump electrodes 110 a , 110 b , 110 c are the same as in the first embodiment. However, there is one pad electrode 120 a corresponding to each bump electrode 110 a , and in contrast there are two pad electrodes 120 b , 120 c corresponding to the bump electrodes 110 b , 110 c . These two pad electrodes 120 b , 120 c are covered by the corresponding bump electrodes 110 b , 110 c.
  • FIG. 21 is a schematic plan view for describing a first example of the relationship between the pad electrodes 120 b and the wiring layer of the uppermost layer.
  • power supply wiring 411 to 413 is provided extending in the X direction on the wiring layer of the uppermost layer.
  • the power supply wiring 411 , 413 is wiring to which the power supply voltage VDD is applied
  • the power supply wiring 412 is wiring to which the ground voltage VSS is applied.
  • the wiring to which the power supply voltage VDD is applied and the wiring to which the ground voltage VSS is applied are frequently arranged alternately in this way.
  • a portion of the power supply wiring 412 is used as pad electrodes 120 b at two locations. These two pad electrodes 120 b are arranged in the X direction along the power supply wiring 412 .
  • the width of the power supply wiring 412 is not particularly widened at the locations corresponding to the pad electrodes 120 b , and therefore the pad electrodes 120 b do not encroach on the other power supply wiring 411 , 413 .
  • two pad electrodes 120 b are allocated for one bump electrode 110 b , so even though the plan size of the pad electrodes 120 b is very small, the contact resistance can be reduced.
  • FIG. 22 is a schematic plan view for describing a second example of the relationship between the pad electrodes 120 b and the wiring layer of the uppermost layer.
  • power supply wiring 421 to 423 is provided extending in the X direction in the wiring layer of the uppermost layer.
  • power supply wiring 421 , 423 is wiring to which the power supply voltage VDD is applied
  • power supply wiring 422 is wiring to which the ground voltage VSS is applied.
  • the wiring to which the power supply voltage VDD is applied and the wiring to which the ground voltage VS S is applied are arranged alternately.
  • a portion of the power supply wiring 421 and a portion of the power supply wiring 423 are used as pad electrodes 120 b . These two pad electrodes 120 b are arranged in the Y direction straddling the power supply wiring 422 .
  • the width of the power supply wiring 421 , 423 is not particularly widened at the positions corresponding to the pad electrodes 120 b , and therefore the pad electrodes 120 b do not encroach on the power supply wiring 422 .
  • one bump electrode 110 b can be allocated to two different power supply wiring 421 , 423 .
  • the two different power supply wiring 421 , 423 is wiring to which the same voltage is applied, they are wiring formed separated from each other on the wiring layer of the uppermost layer. Therefore, these are short-circuited in another wiring layer located in a lower layer.
  • two pad electrodes 120 b are allocated to one bump electrode 110 b , so even though the plan size of the pad electrodes 120 b is very small the contact resistance can be reduced. Also, as in the example shown in FIG. 22 , a single bump electrode 110 b can be allocated to two different wirings.
  • two pad electrodes 120 b , 120 c are allocated to the bump electrodes 110 b , 110 c , but three or more pad electrodes 120 b , 120 c may be allocated. Also, it is not essential that a plurality of pad electrodes 120 b , 120 c is allocated to all the bump electrodes 110 b , 110 c , and a plurality of pad electrodes 120 b , 120 c may be allocated to only some of the bump electrodes 110 b , 110 c.
  • FIG. 23 is a schematic cross-sectional view for describing the structure of a semiconductor chip 100 b according to the third embodiment.
  • FIG. 24 is a schematic cross-sectional view for describing the structure of a semiconductor device 20 in which a plurality of the semiconductor chips 100 b is stacked on the wiring substrate 200 .
  • the semiconductor chip 100 b used in the present embodiment differs from the semiconductor chip 100 used in the first embodiment in that a penetrating electrode 120 X is provided corresponding to pad electrodes 120 a .
  • the penetrating electrode 120 X is provided penetrating a semiconductor substrate S made from silicon or the like, and is electrically connected to a reverse surface bump 170 a provided on a reverse surface of the semiconductor substrate S.
  • Penetrating electrodes 120 X are not provided corresponding to the other pad electrodes 120 b , 120 c , but dummy reverse surface bumps 170 b to 170 d are provided on the reverse surface of the semiconductor substrate S in positions that overlap with the bump electrodes 110 b to 110 d in plan view.
  • a plurality of the semiconductor chips 100 b having this structure can be mounted stacked on the wiring substrate 200 as shown in FIG. 24 .
  • FIG. 24 an example is shown in which two semiconductor chips 100 b are stacked, but three or more semiconductor chips 100 b can be stacked.
  • the reverse surface bumps 170 a to 170 d of the semiconductor chip 100 b located on the bottom layer are connected to the bump electrodes 110 a to 110 d located on the top layer.
  • the impedance of the wiring supplying the internal power supply voltage VINT can be reduced by the bridge wiring 290 , the same as for the first embodiment as described above.
  • the semiconductor chip 100 b on the upper layer the above effect cannot be obtained because it is not directly mounted on the wiring substrate 200 , but if the reverse surface bumps 170 c of each semiconductor chip 100 b are short-circuited by the bridge wiring 290 a as shown in FIG. 25 , the same effect as for the first embodiment can also be obtained for the semiconductor chip 100 b of the upper layer.
  • the bridge wiring 290 a formed on the reverse surface of the semiconductor chip 100 b may be formed at the same time in the process of forming the reverse surface bumps 170 a to 170 d .
  • the plan shape of the bump electrodes 110 a and the reverse surface bumps 170 a is circular. This is because the plan shape of the penetrating electrode 120 X is circular.
  • FIG. 26 is a schematic plan view showing the layout of the main surface of a semiconductor chip 100 c used in the fourth embodiment.
  • FIG. 27 is a schematic plan view for explaining the conductor pattern formed on a wiring substrate 200 b used in the fourth embodiment.
  • the broken line 100 X shown in FIG. 27 is the area for mounting the semiconductor chip 100 c.
  • the semiconductor chip 100 c used in the present embodiment has bump electrodes 110 a arranged along the outer periphery thereof. Also, the plurality of the bump electrodes 110 c is arranged so as to surround the bump electrodes 110 a .
  • the bump electrodes 110 a are arranged along the outer periphery of the semiconductor chip 100 c , so peeling of the semiconductor chip 100 c due to temperature changes does not easily occur. Therefore, the dummy bump electrodes 110 d are not provided, unlike in the first embodiment, but dummy bump electrodes 110 d may be provided.
  • Connecting electrodes 220 a , 220 c are provided on the wiring substrate 200 b in positions corresponding to the bump electrodes 110 a , 110 c as shown in FIG. 27 . Also, the connecting electrodes 220 c connected to the bump electrodes 110 c are connected via bridge wiring 290 b in a shared fashion.
  • the bridge wiring 290 b is not connected to the other wiring pattern 240 , the same as for the first embodiment, and therefore is not connected to any of the external terminals 260 . As a result in the present embodiment the same effect can be obtained as for the first embodiment as described above.
  • FIG. 28 is a schematic cross-sectional view for describing the structure of a semiconductor device 40 according to the fifth embodiment of the present invention.
  • the semiconductor device 40 according to the present embodiment is configured from a semiconductor chip 100 d and a wiring structure 300 formed on a main surface thereof.
  • the semiconductor device 40 according to the present embodiment has a structure referred to as a wafer level package (WLP), and does not use a rigid insulating substrate as in the first to fourth embodiments.
  • WLP wafer level package
  • the wiring structure 300 includes a first insulating film 310 that covers the main surface of the semiconductor chip 100 d , a wiring layer 320 formed on the surface of the first insulating film 310 , a second insulating film 330 that covers the wiring layer 320 , and external terminals 340 formed on the surface of the second insulating film 330 .
  • a plurality of through holes that expose the pad electrodes 120 is provided in the first insulating film 310 , and the pad electrodes 120 and the wiring layer 320 are electrically connected via these through holes.
  • a plurality of through holes that expose the wiring layer 320 is provided in the second insulating film 330 , and the wiring layer 320 and the external terminals 340 are electrically connected via the through holes.
  • the wiring layer 320 has the role of converting the electrode pitch of the pad electrodes 120 into the electrode pitch of the external terminals 340 .
  • FIG. 29 is a schematic plan view showing the layout of bridge wiring 290 c formed on the wiring layer 320 .
  • the broken lines indicate the pad electrodes 120 a to 120 c.
  • the bridge wiring 290 c formed on the wiring layer 320 is provided so as to short-circuit the plurality of pad electrodes 120 c .
  • the impedance of the wiring supplying the internal power supply voltage VINT can be reduced by the bridge wiring 290 c , the same as for the first to fourth embodiments.
  • the bridge wiring 290 c is not connected to any of the external terminals 340 .
  • the semiconductor device according to the present invention is not limited to a structure in which the semiconductor chip is flip chip connected to a rigid wiring substrate, but it can also be applied to a semiconductor device having a so-called wafer level package structure, as described in the fifth embodiment.
  • the present invention is not limited to this, and as shown in FIG. 30 by connecting specific pad electrodes 120 e to connecting electrodes 220 e , and by bringing out the wiring 290 e on to the wiring substrate 200 d , the probing can also be carried out after flip chip connecting.
  • the probing may be directly carried out on the wiring 290 e , or it may be carried out on a test pad TP provided on the end of the wiring 290 e.
  • a test circuit 190 provided on the semiconductor chip 100 e is connected to the pad electrodes 120 e , and in this way the test circuit 190 is operated after flip chip connecting, or, a signal or voltage level generated by the test circuit 190 can be monitored.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US14/773,817 2013-03-13 2014-03-10 Semiconductor device Active US9589921B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013-050404 2013-03-13
JP2013050404 2013-03-13
PCT/JP2014/056185 WO2014142075A1 (ja) 2013-03-13 2014-03-10 半導体装置

Publications (2)

Publication Number Publication Date
US20160027754A1 US20160027754A1 (en) 2016-01-28
US9589921B2 true US9589921B2 (en) 2017-03-07

Family

ID=51536731

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/773,817 Active US9589921B2 (en) 2013-03-13 2014-03-10 Semiconductor device

Country Status (5)

Country Link
US (1) US9589921B2 (de)
KR (1) KR20150128919A (de)
DE (1) DE112014001274T5 (de)
TW (1) TW201503303A (de)
WO (1) WO2014142075A1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102214512B1 (ko) * 2014-07-04 2021-02-09 삼성전자 주식회사 인쇄회로기판 및 이를 이용한 반도체 패키지
EP3175481B1 (de) * 2014-07-28 2021-07-21 Intel Corporation Multichipmodul-halbleiterchipverkapselung mit dichter verkapselungsverdrahtung
KR102287754B1 (ko) * 2014-08-22 2021-08-09 삼성전자주식회사 칩 적층 반도체 패키지
KR102327142B1 (ko) * 2015-06-11 2021-11-16 삼성전자주식회사 웨이퍼 레벨 패키지
JP6610144B2 (ja) * 2015-10-07 2019-11-27 富士通株式会社 電子部品及び電子装置の製造方法
US10014268B2 (en) * 2016-03-01 2018-07-03 Advanced Semiconductor Engineering, Inc. Semiconductor chip, semiconductor device and manufacturing process for manufacturing the same
US9922920B1 (en) 2016-09-19 2018-03-20 Nanya Technology Corporation Semiconductor package and method for fabricating the same
JP2018063578A (ja) * 2016-10-13 2018-04-19 日本航空電子工業株式会社 印刷配線の製造方法
JPWO2018092318A1 (ja) * 2016-11-21 2019-01-24 オリンパス株式会社 内視鏡用撮像モジュール、および内視鏡
JP6680705B2 (ja) * 2017-02-10 2020-04-15 キオクシア株式会社 半導体装置及びその製造方法
US11233025B2 (en) * 2017-05-31 2022-01-25 Futurewei Technologies, Inc. Merged power pad for improving integrated circuit power delivery
TWI736859B (zh) * 2019-03-18 2021-08-21 矽品精密工業股份有限公司 電子封裝件及其製法
KR20210065263A (ko) * 2019-11-26 2021-06-04 삼성전자주식회사 반도체 테스트 장치 및 그 테스트 방법
US11315855B2 (en) * 2020-04-01 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure with photonic die and method
US11404404B2 (en) * 2020-05-27 2022-08-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having photonic die and electronic die

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03173434A (ja) 1989-12-01 1991-07-26 Seiko Epson Corp 半導体集積回路装置
JPH03173435A (ja) 1989-12-01 1991-07-26 Seiko Epson Corp 半導体集積回路装置
JPH1070158A (ja) 1996-08-27 1998-03-10 Toshiba Corp Ｔａｂ実装半導体装置
US20040150118A1 (en) * 2003-02-03 2004-08-05 Nec Electronics Corporation Warp-suppressed semiconductor device
US7078792B2 (en) * 2004-04-30 2006-07-18 Atmel Corporation Universal interconnect die

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03173434A (ja) 1989-12-01 1991-07-26 Seiko Epson Corp 半導体集積回路装置
JPH03173435A (ja) 1989-12-01 1991-07-26 Seiko Epson Corp 半導体集積回路装置
JPH1070158A (ja) 1996-08-27 1998-03-10 Toshiba Corp Ｔａｂ実装半導体装置
US20040150118A1 (en) * 2003-02-03 2004-08-05 Nec Electronics Corporation Warp-suppressed semiconductor device
US7078792B2 (en) * 2004-04-30 2006-07-18 Atmel Corporation Universal interconnect die

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Application No. PCT/JP2014/056185, International Search Report, Jun. 10, 2014.

Also Published As

Publication number Publication date
WO2014142075A1 (ja) 2014-09-18
US20160027754A1 (en) 2016-01-28
DE112014001274T5 (de) 2015-12-17
KR20150128919A (ko) 2015-11-18
TW201503303A (zh) 2015-01-16

Similar Documents

Publication Publication Date Title
US9589921B2 (en) Semiconductor device
US10510734B2 (en) Semiconductor packages having dummy connectors and methods of forming same
KR102570582B1 (ko) 반도체 패키지 및 그 제조 방법
US8575493B1 (en) Integrated circuit device having extended under ball metallization
TWI654723B (zh) 封裝結構之製法
KR20130098685A (ko) 반도체 패키지
US9935038B2 (en) Semiconductor device packages and methods
US10916519B2 (en) Method for manufacturing semiconductor package with connection structures including via groups
TWI579984B (zh) 電子封裝件及其製法
US7595268B2 (en) Semiconductor package having re-distribution lines for supplying power and a method for manufacturing the same
US20110309358A1 (en) Semiconductor chip with fine pitch leads for normal testing of same
JP2014179364A (ja) 半導体チップ及びこれを備える半導体装置
JP2008091795A (ja) 半導体装置および半導体装置の製造方法
TWI395280B (zh) 用於晶圓級半導體測試之測試座及測試板
TWI467723B (zh) 半導體封裝件及其製法
JP2014179363A (ja) 半導体チップ及びこれを備える半導体装置
JP2010093106A (ja) 半導体装置およびその製造方法
JP2014179362A (ja) 半導体装置
US20160027758A1 (en) Semiconductor device
TWI612632B (zh) 封裝結構、晶片結構及其製法
TWI807827B (zh) 電子封裝件及其製法
JP5331934B2 (ja) 半導体装置
TWI790916B (zh) 電子封裝件及其製法
TWI790945B (zh) 電子封裝件及其製法
JP2013219385A (ja) 半導体装置

Legal Events

Date Code Title Description
STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: PS5 LUXCO S.A.R.L., LUXEMBOURG

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:042586/0772

Effective date: 20130829

Owner name: LONGITUDE SEMICONDUCTOR S.A.R.L., LUXEMBOURG

Free format text: CHANGE OF NAME;ASSIGNOR:PS5 LUXCO S.A.R.L.;REEL/FRAME:042589/0346

Effective date: 20131112

AS Assignment

Owner name: LONGITUDE LICENSING LIMITED, IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LONGITUDE SEMICONDUCTOR S.A.R.L.;REEL/FRAME:046863/0001

Effective date: 20180731

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4