US9461036B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US9461036B2
US9461036B2 US14/679,051 US201514679051A US9461036B2 US 9461036 B2 US9461036 B2 US 9461036B2 US 201514679051 A US201514679051 A US 201514679051A US 9461036 B2 US9461036 B2 US 9461036B2
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conductivity type
semiconductor layer
semiconductor device
type region
semiconductor
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US20150303189A1 (en
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Hisamitsu Suzuki
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs
    • H01L27/0623—
    • H01L29/0657—
    • H01L29/0804—
    • H01L29/66272—
    • H01L29/732—
    • H01L29/7851—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6211—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
    • H01L21/8249—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to semiconductor devices and more particularly to technology for a semiconductor device having a bipolar transistor.
  • a bipolar transistor may be provided in the semiconductor substrate.
  • a bipolar transistor is formed by stacking an impurity layer to become an emitter, an impurity layer to become a base, and an impurity layer to become a collector in the thickness direction of the semiconductor substrate.
  • a fin-type semiconductor layer is used in the FET forming process (for example, see Japanese Unexamined Patent Application Publications No. 2007-165780 and Japanese Translation of PCT International Application Publication No. JP-T-2013-511852).
  • a semiconductor device which includes a substrate, a first first-conductivity type region, a second-conductivity type region, a first semiconductor layer, a second first-conductivity type region, a first contact, a second contact, and a third contact.
  • the substrate is a semiconductor substrate.
  • the first first-conductivity type region is a first-conductivity type impurity region which is formed in the substrate.
  • the second-conductivity type region is a second-conductivity type impurity region which is formed in the surface layer of the first first-conductivity type region.
  • the first semiconductor layer is a fin-type semiconductor layer which is located over the second-conductivity type region.
  • the second first-conductivity type region is formed in the first semiconductor layer with its bottom coupled to the second-conductivity type region.
  • the first contact is coupled to the first first-conductivity type region
  • the second contact is coupled to the second-conductivity type region
  • the third contact is coupled to the second first-conductivity type region.
  • a semiconductor device in which a first semiconductor layer over a substrate includes a first first-conductivity type region, a second first-conductivity type region, and a second-conductivity type region.
  • the second first-conductivity type region is spaced from the first first-conductivity type region.
  • the second-conductivity type region couples the first first-conductivity type region and the second first-conductivity type region.
  • a bipolar transistor can be formed using a fin-type semiconductor layer.
  • FIG. 1 is a perspective view showing the structure of a semiconductor device according to a first embodiment of the invention
  • FIG. 2 is a plan view of the semiconductor device
  • FIG. 3 is a sectional view taken along the line A-A′ of FIG. 2 ;
  • FIGS. 4A and 4B are views for explaining a semiconductor device manufacturing method, in which FIG. 4A is a perspective view and FIG. 4B is a sectional view;
  • FIGS. 5A and 5B are views for explaining the semiconductor device manufacturing method, in which FIG. 5A is a perspective view and FIG. 5B is a sectional view;
  • FIGS. 6A and 6B are views for explaining the semiconductor device manufacturing method, in which FIG. 6A is a perspective view and FIG. 6B is a sectional view;
  • FIGS. 7A and 7B are views for explaining the semiconductor device manufacturing method, in which FIG. 7A is a perspective view and FIG. 7B is a sectional view;
  • FIGS. 8A and 8B are views for explaining the semiconductor device manufacturing method, in which FIG. 8A is a perspective view and FIG. 8B is a sectional view;
  • FIGS. 9A and 9B are views showing variations of the semiconductor device, in which FIG. 9A shows the first variation and FIG. 9B shows the second variation;
  • FIG. 10 is a plan view of a semiconductor device according to a second embodiment of the invention.
  • FIG. 11 is a sectional view taken along the line A-A′ of FIG. 10 ;
  • FIG. 12 is a perspective view showing the structure of a semiconductor device according to a third embodiment of the invention.
  • FIG. 13 is a plan view of the semiconductor device according to the third embodiment.
  • FIG. 14 is a sectional view taken along the line B-B′ of FIG. 13 ;
  • FIGS. 15A and 15B are views for explaining a semiconductor device manufacturing method according to the third embodiment, in which FIG. 15A is a perspective view and FIG. 15B is a sectional view;
  • FIGS. 16A and 16B are views showing variations of the semiconductor device according to the third embodiment, in which FIG. 16A shows the first variation and FIG. 16B shows the second variation;
  • FIG. 17 is a plan view of a semiconductor device according to a fourth embodiment of the invention.
  • FIG. 18 is a sectional view taken along the line B-B′ of FIG. 17 ;
  • FIG. 19 is a perspective view showing the structure of a semiconductor device according to a fifth embodiment of the invention.
  • FIG. 20 is a plan view of the semiconductor device according to the fifth embodiment.
  • FIG. 21 is a sectional view taken along the line B-B′ of FIG. 20 ;
  • FIGS. 22A and 22B are sectional views showing variations of the semiconductor device according to the fifth embodiment, in which FIG. 22A shows the first variation and FIG. 22B shows the second variation;
  • FIG. 23 is a sectional view showing the structure of a semiconductor device according to a sixth embodiment of the invention.
  • FIG. 24 is a plan view of a semiconductor device according to a seventh embodiment of the invention.
  • FIG. 25 is a sectional view taken along the line B-B′ of FIG. 24 .
  • FIG. 1 is a perspective view showing the structure of a semiconductor device SD according to the first embodiment.
  • FIG. 2 is a plan view of the semiconductor device SD and
  • FIG. 3 is a sectional view taken along the line A-A′ of FIG. 2 .
  • the layers above an insulating film INSL 2 and contacts are omitted in FIG. 3 .
  • a substrate SUB including a bipolar transistor BPT and a substrate SUB including a field effect transistor FET are separately shown for illustrative convenience, but these are one and the same substrate SUB.
  • the semiconductor substrate SD includes a substrate SUB, collector (first first-conductivity type region), base BSE (second-conductivity type region), first semiconductor layer SCL 1 , emitter EMI (second first-conductivity type region), first contact CON 1 , second contact CON 2 , and third contact CON 3 .
  • the substrate SUB is a semiconductor substrate.
  • the collector COR is a first-conductivity type impurity region which is formed in the substrate SUB.
  • the base BSE is a second-conductivity type impurity region which is formed in the surface layer of the collector COR.
  • the first semiconductor layer SCL 1 is a fin-type semiconductor layer which lies over the base BSE.
  • the emitter EMI is formed in the first semiconductor layer SCL 1 with its bottom coupled to the base BSE.
  • the first contact CON 1 is coupled to the collector COR, the second contact CON 2 is coupled to the base BSE, and the third contact CON 3 is coupled to the emitter EMI.
  • the substrate SUB is a silicon substrate.
  • a bipolar transistor BPT and a field effect transistor FET are formed on the same substrate SUB.
  • the substrate SUB is a second-conductivity type substrate, for example, a p-type second-conductivity type substrate.
  • the emitter EMI and collector COR of the bipolar transistor BPT are of the n-type.
  • the substrate SUB is an n-type semiconductor substrate, the emitter EMI and collector COR of the bipolar transistor BPT are of the p-type.
  • the bipolar transistor BPT is a vertical bipolar transistor which includes the emitter EM 1 , base BSE, and collector COR as mentioned above.
  • the emitter EMI of the bipolar transistor BPT is formed using the fin-type first semiconductor layer SCL 1 .
  • the first semiconductor layer SCL 1 is a first-conductivity type semiconductor layer and the whole first semiconductor layer SCL 1 configures the emitter EMI.
  • the base BSE and collector COR are formed by implanting impurity ions into the substrate SUB.
  • the emitter EMI is formed by implanting impurity ions into the first semiconductor layer SCL 1 after the formation of the first semiconductor layer SCL 1 .
  • the field effect transistor FET is formed using a fin-type second semiconductor layer SCL 2 .
  • an insulating film INSL 1 (for example, a silicon oxide film) is formed over the substrate SUB.
  • the insulating film INSL 1 is an element isolation film which has a smaller depth than the second semiconductor layer SCL 2 . Therefore, the second semiconductor layer SCL 2 protrudes from the insulating film INSL 1 .
  • the gate electrode GE of the field effect transistor FET lies over the insulating film INSL 1 , striding across part of the second semiconductor layer SCL 2 . It is preferable that the first semiconductor layer SCL 1 and second semiconductor layer SCL 2 extend in the same direction.
  • the insulating film INSL 1 also lies in the region of the substrate SUB in which the bipolar transistor BPT is formed.
  • a gate insulating film GINS lies between the second semiconductor layer SCL 2 and gate electrode GE.
  • the gate insulating film GINS is formed, for example, by thermally oxidizing the second semiconductor layer SCL 2 .
  • the region of the second semiconductor layer SCL 2 which is not covered by the gate electrode GE is doped with impurities. Consequently, a first impurity region to become a source SOU and a second impurity region to become a drain DRN are formed in the second semiconductor layer SCL 2 .
  • the gate insulating film GINS and gate electrode GE lie between the first impurity region and second impurity region of the second semiconductor layer SCL 2 .
  • An insulating film INSL 2 as an interlayer insulating film is formed over the insulating film INSL 1 .
  • Contacts CON 4 , CON 5 , and CON 6 as well as the first contact CON 1 , second contact CON 2 and third contact CON 3 are buried in the insulating film INSL 1 and insulating film INSL 2 .
  • the first contact CON 1 , second contact CON 2 , and third contact CON 3 are coupled to the collector COR, base BSE, and emitter EMI, respectively.
  • the contact CON 4 , contact CON 5 , and contact CON 6 are coupled to the gate electrode GE, drain DRN, and source SOU, respectively.
  • the arrangement of the contacts is not limited to the example shown in FIGS. 2 and 3 .
  • a first interconnect INC 1 , second interconnect INC 2 , and third interconnect INC 3 are formed over the insulating film INSL 2 .
  • the first interconnect INC 1 , second interconnect INC 2 , and third interconnect INC 3 are coupled to the first contact CON 1 , second contact CON 2 , and third contact CON 3 , respectively.
  • the first interconnect INC 1 , second interconnect INC 2 , and third interconnect INC 3 are formed, for example, by making a conductive film (for example, a metal film such as a tungsten film) over the insulating film INSL 2 and removing the conductive film selectively.
  • the first interconnect INC 1 , second interconnect INC 2 , and third interconnect INC 3 may be formed by a damascene process.
  • a plurality of interconnects to be coupled to the contacts CON 4 , CON 5 , and CON 6 are also formed over the insulating film INSL 2 . These interconnects are formed in the same process in which the first interconnect INC 1 is formed.
  • FIGS. 4A, 5A, 6A, 7A, and 8A are perspective views and FIGS. 4B, 5B, 6B, 7B, and 8B are sectional views corresponding to FIG. 3 .
  • a second-conductivity type substrate SUB is provided as shown in FIGS. 4A and 4B .
  • a resist pattern (not shown) is made over the substrate SUB and using the resist pattern as a mask, first-conductivity type impurities (for example, P) are implanted into the substrate SUB. Consequently, a collector COR is formed.
  • the dosage of impurities in this step is, for example, not less than 1 ⁇ 10 13 cm 2 and not more than 1 ⁇ 10 14 cm 2 . After that, the resist pattern is removed.
  • a resist pattern (not shown) is made over the substrate SUB and using the resist patter as a mask, second-conductivity type impurities (for example, B) are implanted into the substrate SUB. Consequently, a base BSE is formed.
  • the dosage of impurities in this step is, for example, not less than 1 ⁇ 10 12 cm 2 and not more than 1 ⁇ 10 14 cm 2 . After that, the resist pattern is removed.
  • a mask pattern MSK 1 for example, a hard mask pattern of silicon nitride film is formed over the substrate SUB as shown in FIGS. 5A and 5B .
  • the mask pattern MSK 1 covers the region of the substrate SUB in which the first semiconductor layer SCL 1 is to be formed, and the region of the substrate SUB in which the second semiconductor layer SCL 2 is to be formed.
  • the substrate SUB is dry-etched using the mask pattern MSK 1 as a mask as shown in FIGS. 6A and 6B . Consequently, a first semiconductor layer SCL 1 and a second semiconductor layer SCL 2 are formed in the substrate SUB.
  • an insulating film INSL 1 is formed over the substrate SUB as shown in FIGS. 7A and 7B .
  • the insulating film INSL 1 is made by a deposition process such as CVD.
  • the insulating film INSL 1 is made so that it is thicker than the first semiconductor layer SCL 1 and the second semiconductor layer SCL 2 .
  • the insulating film INSL 1 is planarized by a CMP process and then the insulating film INSL 1 is thinned by etching so that the upper portions of the first semiconductor layer SCL 1 and second semiconductor layer SCL 2 are exposed from the insulating film INSL 1 .
  • the mask pattern MSK 1 is removed.
  • a gate insulating film GINS is made on the second semiconductor layer SCL 2 as shown in FIGS. 8A and 8B .
  • the gate insulating film GINS is formed, for example, by a thermal oxidation process.
  • a thermally oxidized film (not shown) is also made on the surface layer of the first semiconductor layer SCL 1 .
  • a conductive film for example, polysilicon film
  • a gate electrode GE is made over the substrate SUB and the polysilicon film is selectively removed. Consequently, a gate electrode GE is formed.
  • impurities are implanted into the second semiconductor layer SCL 2 using the gate electrode GE as a mask. Consequently, a source SOU and a drain DRN are formed in the second semiconductor layer SCL 2 .
  • first-conductivity type impurities are also implanted into the first semiconductor layer SCL 1 in the step of forming the source SOU and drain DRN. Consequently, an emitter EMI is formed in the first semiconductor layer SCL 1 .
  • an emitter EMI is formed in an impurity implanting step other than the step of forming the source SOU and drain DRN.
  • the first semiconductor layer SCL 1 is covered by the resist pattern in the step of forming the source SOU and drain DRN.
  • the second semiconductor layer SCL 2 is covered by the resist pattern in the step of forming the emitter EMI.
  • the emitter EMI is formed in the same step in which the sources SOU and drains DRN of the first-conductivity type field effect transistors FET are formed.
  • the second semiconductor layer SCL 2 which is used for the second-conductivity type field effect transistors FET is covered by the resist pattern in the step of forming the sources SOU and drains DRN of the first-conductivity type field effect transistors FET.
  • the second semiconductor layer SCL 2 and first semiconductor layer SCL 1 which are used for the first-conductivity type field effect transistors FET are covered by the resist pattern in the step of forming the sources SOU and drains DRN of the second-conductivity type field effect transistors FET.
  • the dosage of impurities for the formation of an emitter EMI is, for example, not less than 1 ⁇ 10 14 cm 2 and not more than 1 ⁇ 10 16 cm 2 .
  • the emitter EMI occupies the entire first semiconductor layer SCL 1 in the thickness direction and does not occupy any part of the substrate SUB other than the first semiconductor layer SCL 1 .
  • the emitter EMI may partially occupy the first semiconductor layer CL 1 in the thickness direction or as shown in FIG. 9B , it may occupy the first semiconductor layer SCL 1 and extend to a portion of the substrate SUB which is joined to the first semiconductor layer SCL 1 .
  • the area occupied by the emitter EMI can be changed, for example, by adjusting the energy for ion implantation.
  • a bipolar transistor BPT can be formed using a fin-type first semiconductor layer SCL 1 .
  • the bipolar transistor BPT can be miniaturized.
  • a second semiconductor layer SCL 2 is formed in the same step in which the first semiconductor layer SCL 1 is formed, and a fin-type field effect transistor FET is formed using the second semiconductor layer SCL 2 . Therefore, a fin-type bipolar transistor BPT and a fin-type field effect transistor FET can be formed over a substrate SUB in a fewer steps.
  • FIG. 10 is a plan view of a semiconductor device SD according to the second embodiment and FIG. 11 is a sectional view taken along the line A-A′ of FIG. 10 .
  • FIG. 10 corresponds to FIG. 2 for the first embodiment and
  • FIG. 11 corresponds to FIG. 3 for the first embodiment.
  • the semiconductor device SD according to this embodiment is structurally the same as the semiconductor device SD according to the first embodiment except the following points.
  • the first point is that the substrate SUB is of the first-conductivity type, or of the same conductivity type as the collector COR.
  • the substrate SUB includes a separation region SEP to separate the collector COR from the substrate SUB electrically.
  • the separation region SEP is a second-conductivity type impurity region which covers the side and bottom faces of the collector COR. In other words, the collector COR is formed in part of the separation region SEP.
  • the method for manufacturing the semiconductor device SD according to this embodiment is the same as the method for manufacturing the semiconductor device SD according to the first embodiment except that the separation region SEP is formed before (or after) the formation of the collector COR.
  • the separation region SEP is formed, for example, by making a resist pattern on the substrate SUB and implanting impurities into the substrate SUB using the resist pattern as a mask.
  • the dosage of impurities is, for example, not less than 1 ⁇ 10 12 cm 2 and not more than 1 ⁇ 10 13 cm 2 .
  • the second embodiment also brings about the same advantageous effects as the first embodiment.
  • the bipolar transistor BPT in the first embodiment and the bipolar transistor BPT in the second embodiment may be formed on the same substrate SUB.
  • FIG. 12 is a perspective view showing the structure of a semiconductor device SD according to the third embodiment.
  • FIG. 13 is a plan view of the semiconductor device SD and
  • FIG. 14 is a sectional view taken along the line B-B′ of FIG. 13 .
  • FIGS. 12 to 14 correspond to FIGS. 1 to 3 for the first embodiment. In these figures, contacts are omitted.
  • the semiconductor device SD according to the third embodiment is structurally the same as the semiconductor device SD according to the first embodiment except that the bipolar transistor BPT has a lateral structure.
  • the base BSE, emitter EMI, and collector COR of the bipolar transistor BPT are all formed in the first semiconductor layer SCL 1 .
  • the emitter EMI and the collector COR are spaced apart from each other.
  • the base BSE is formed between the emitter EMI and the collector COR in the first semiconductor layer SCL 1 . In other words, the base BSE interconnects the emitter EMI and collector COR.
  • a portion of the base BSE lies in an area of the substrate SUB under the first semiconductor layer SCL 1 , but unlike the first embodiment, the collector COR does not lie there.
  • FIG. 15A is a perspective view for explaining the method for manufacturing the semiconductor device SD according to the third embodiment and FIG. 15B is a sectional view of the bipolar transistor part shown in FIG. 15A .
  • the cross section shown in FIG. 15B corresponds to the cross section shown in FIG. 14 .
  • the method for manufacturing the semiconductor device SD according to this embodiment is the same as the method for manufacturing the semiconductor device SD according to the first embodiment except the following points.
  • the first point is that the collector COR is not formed before the first semiconductor layer SCL 1 and second semiconductor layer SCL 2 are formed ( FIG. 4 for the first embodiment).
  • the base BSE is formed in the same way as in the first embodiment.
  • the first semiconductor layer SCL 1 is of the second-conductivity type.
  • the region of the first semiconductor layer SCL 1 to become the base BSE is covered by a mask pattern MSK 2 , for example, a resist pattern. Then, first-conductivity type impurities are implanted into the first semiconductor layer SCL 1 using the mask pattern MSK 2 as a mask. Consequently, a collector COR and an emitter EMI are formed in the first semiconductor layer SCL 1 .
  • a mask pattern MSK 2 and implant impurities into the first semiconductor layer SCL 1 is the same as when to form the emitter EMI in the first semiconductor layer SCL 1 in the first embodiment.
  • the collector COR and emitter EMI partially occupy the first semiconductor layer SCL 1 in the thickness direction.
  • the collector COR and emitter EMI may be formed so as to extend throughout the first semiconductor layer SCL 1 in the thickness direction and not occupy any region other than the first semiconductor layer SCL 1 .
  • the collector COR and emitter EMI may occupy the first semiconductor layer SCL 1 and extend to a portion of the substrate SUB which is joined to the first semiconductor layer SCL 1 .
  • the area occupied by the collector COR and emitter EMI can be changed, for example, by adjusting the energy for ion implantation.
  • a lateral bipolar transistor BPT can be formed using a fin-type first semiconductor layer SCL 1 .
  • FIG. 17 is a plan view of a semiconductor device SD according to the fourth embodiment and FIG. 18 is a sectional view taken along the line B-B′ of FIG. 17 .
  • FIG. 17 corresponds to FIG. 13 for the third embodiment and FIG. 18 corresponds to FIG. 14 for the third embodiment.
  • the semiconductor device SD according to this embodiment is structurally the same as the semiconductor device SD according to the third embodiment except the following points.
  • the first point is that the substrate SUB is of the first-conductivity type, or of the same conductivity type as the collector COR.
  • the substrate SUB includes a separation region SEP to separate the collector COR from the substrate SUB electrically.
  • the separation region SEP is a second-conductivity type impurity region which covers the side and bottom faces of the collector COR.
  • the collector COR is formed in part of the surface layer of the separation region SEP.
  • the method for manufacturing the semiconductor device SD according to this embodiment is the same as the method for manufacturing the semiconductor device SD according to the first embodiment except that the separation region SEP is formed before (or after) the formation of the base BSE.
  • the separation region SEP is formed in the same way as in the second embodiment.
  • the fourth embodiment also brings about the same advantageous effects as the third embodiment.
  • the bipolar transistor BPT in the third embodiment and the bipolar transistor BPT in the fourth embodiment may be formed on the same substrate SUB.
  • FIG. 19 is a perspective view showing the structure of a semiconductor device SD according to the fifth embodiment.
  • FIG. 20 is a plan view of the semiconductor device SD and
  • FIG. 21 is a sectional view taken along the line B-B′ of FIG. 20 .
  • FIGS. 19 to 21 correspond to FIGS. 12 to 14 for the first embodiment.
  • the semiconductor device SD according to the fifth embodiment is structurally the same as the semiconductor device SD according to the third or fourth embodiment except that a mask pattern MSK 3 is made on the bipolar transistor BPT.
  • FIGS. 19 to 21 show a case that the semiconductor device is structurally the same as in the third embodiment.
  • the mask pattern MSK 3 is used in place of the mask pattern MSK 2 in the third and fourth embodiments. It functions as a mask in the step in which first-conductivity type impurities are implanted into the second-conductivity type first semiconductor layer SCL 1 to form the collector COR and emitter EMI. Since the mask pattern MSK 3 is made in the same step in which the gate electrode GE of the field effect transistor FET is formed, it is made of the same material as the gate electrode GE. An insulating film INSL 3 which is the same as the gate insulating film GINS is made on the top and side faces of the first semiconductor layer SCL 1 .
  • the collector COR and emitter EMI partially occupy the first semiconductor layer SCL 1 in the thickness direction.
  • the collector COR and emitter EMI may be formed so as to extend throughout the first semiconductor layer SCL 1 in the thickness direction and not occupy any region other than the first semiconductor layer SCL 1 .
  • the collector COR and emitter EMI may occupy the first semiconductor layer SCL 1 and extend to a portion of the substrate SUB which is joined to the first semiconductor layer SCL 1 .
  • the area occupied by the collector COR and emitter EMI can be changed, for example, by adjusting the energy for ion implantation.
  • the fifth embodiment also brings about the same advantageous effects as the third or fourth embodiment. Since the mask pattern MSK 3 is made in the same step in which the gate electrode GE is formed, the number of steps for manufacturing the semiconductor device SD is decreased. In addition, since the width of the mask pattern MSK 3 is almost equal to that of the gate electrode GE, the width of the mask pattern MSK 3 can be decreased to decrease the width of the base BSE.
  • FIG. 23 is a sectional view showing the structure of a semiconductor device SD according to the sixth embodiment, which corresponds to FIG. 21 for the fifth embodiment.
  • the semiconductor device SD according to this embodiment is structurally the same as the semiconductor device SD according to the fifth embodiment except the following points.
  • the first point is that a sidewall SW 1 is made on the side face of the mask pattern MSK 3 and a sidewall SW 2 is made on the side face of the first semiconductor layer SCL 1 . Also, a sidewall SW 1 is made on the side face of the gate electrode GE and a sidewall SW 2 is made on the side face of the second semiconductor layer SCL 2 , though not shown in the figure.
  • An insulating film INSL 3 is made only in the area of the first semiconductor layer SCL 1 which is covered by the mask pattern MSK 3 , namely only over the base BSE.
  • the method for manufacturing the semiconductor device SD according to this embodiment is the same as the method for manufacturing the semiconductor device SD according to the fifth embodiment except that the step of making sidewalls SW 1 and SW 2 is taken after the steps of manufacturing the semiconductor device SD according to the fifth embodiment.
  • the step of making sidewalls SW 1 and SW 2 includes the step of making an insulating film for sidewalls SW 1 and SW 2 and the step of etching back the insulating film to make sidewalls SW 1 and SW 2 .
  • the sixth embodiment also brings about the same advantageous effects as the fifth embodiment.
  • FIG. 24 is a plan view of a semiconductor device SD according to the seventh embodiment and FIG. 25 is a sectional view taken along the line B-B′ of FIG. 24 .
  • FIG. 24 corresponds to FIG. 20 for the fifth embodiment and
  • FIG. 25 corresponds to FIG. 21 for the fifth embodiment.
  • the semiconductor device SD according to this embodiment is structurally the same as the semiconductor device SD according to the fifth embodiment except the following points.
  • the first point is that the substrate SUB is of the first-conductivity type, or of the same conductivity type as the collector COR.
  • the substrate SUB includes a separation region SEP to separate the collector COR from the substrate SUB electrically.
  • the separation region SEP is a second-conductivity type impurity region which covers the side and bottom faces of the collector COR.
  • the collector COR is formed in part of the surface layer of the separation region SEP.
  • the method for manufacturing the semiconductor device SD according to this embodiment is the same as the method for manufacturing the semiconductor device SD according to the fifth embodiment except that the separation region SEP is formed before (or after) the formation of the base BSE.
  • the separation region SEP is formed in the same way as in the second embodiment.
  • the seventh embodiment also brings about the same advantageous effects as the fifth embodiment.
  • the bipolar transistor BPT in the fifth embodiment and the bipolar transistor BPT in the seventh embodiment may be formed on the same substrate SUB.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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FR3087048B1 (fr) 2018-10-08 2021-11-12 St Microelectronics Sa Transistor bipolaire
FR3087047B1 (fr) 2018-10-08 2021-10-22 St Microelectronics Sa Transistor bipolaire
FR3113539B1 (fr) 2020-08-24 2022-09-23 St Microelectronics Crolles 2 Sas Transistor bipolaire

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