US9271436B2 - Electronic packaged device and manufacturing method thereof - Google Patents

Electronic packaged device and manufacturing method thereof Download PDF

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Publication number
US9271436B2
US9271436B2 US14/286,965 US201414286965A US9271436B2 US 9271436 B2 US9271436 B2 US 9271436B2 US 201414286965 A US201414286965 A US 201414286965A US 9271436 B2 US9271436 B2 US 9271436B2
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trenches
grounding
encapsulating member
forming
conductive material
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US20150173258A1 (en
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Jen-Chun Chen
Pai-Sheng Shih
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Universal Scientific Industrial Shanghai Co Ltd
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Universal Scientific Industrial Shanghai Co Ltd
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/046—Surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0022—Casings with localised screening of components mounted on printed circuit boards [PCB]
    • H05K9/0037—Housings with compartments containing a PCB, e.g. partitioning walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0007—Casings
    • H05K9/002—Casings with localised screening
    • H05K9/0039—Galvanic coupling of ground layer on printed circuit board [PCB] to conductive casing
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0064—Earth or grounding circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09036—Recesses or grooves in insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10371—Shields or metal cases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Definitions

  • the instant disclosure relates to an electronic packaged device and the manufacturing method thereof.
  • an electromagnetic interference (EMI) layer is designed in the electronic packaging to isolate different electronic components.
  • an external metal cover (Metal lid) is installed on the electronic packaging.
  • An embodiment of the instant disclosure provide an electronic packaging device which includes a shielding structure for prevent electromagnetic interferences between electronic components.
  • the electronic packaged device includes a circuit layer, a plurality of electronic components, an encapsulating member, a shielding structure, at least one grounding structure, and an electromagnetic shielding layer.
  • the circuit layer includes at least one grounding pad.
  • the electronic components and the circuit layer are electrically connected.
  • the encapsulating member covers at least one electronic component.
  • a trench is formed on the encapsulating member to partition into at least two encapsulating compartments.
  • the shielding structure is interposed between different encapsulating compartments, and the shielding structure is electrically connected to the grounding pad.
  • the electromagnetic shielding layer is formed on the external surface of encapsulating member and electrically connected to the grounding pad.
  • An embodiment of the instant disclosure provides an electronic package device manufacturing method including disposing a plurality of electronic components on a surface of a substrate carrier. Disposing an encapsulating member on the surface of the substrate carrier to cover the electronic components. Separating the substrate carrier from the encapsulating member. Forming a plurality of first trenches and a plurality of first grounding trenches on a first surface of the encapsulating member. Disposing conductive material on the first surface of the encapsulating member, in the first trenches and in the first grounding trenches to form a conductive layer and a plurality of grounding structures. Patterning the conductive layer on the first surface of the encapsulating member to form a circuit layer.
  • the circuit layer including at least one grounding pad, which electrically connected to the grounding structures.
  • Another embodiment of the instant disclosure provides a manufacturing method of electronic package device, including configuring a plurality of electronic components on a surface of a substrate carrier. Disposing an encapsulating member on the surface of the substrate carrier to cover the electronic components. Separating the substrate carrier from the encapsulating member. Forming a plurality of first trenches and a plurality of first grounding trenches on a first surface of the encapsulating member. Disposing conductive material on the first surface of the encapsulating member, in the first trenches and in the first grounding trenches to form a conductive layer. Patterning the conductive layer on the first surface of the encapsulating member to form a circuit layer.
  • the circuit layer including at least one grounding pad, which electrically connected to the grounding structures.
  • the instant disclosure provides a manufacturing method of package device, in which electronic components are fixed onto a substrate carrier, and an encapsulating member is disposed on the surface of the substrate carrier to cover the electronic components.
  • the substrate carrier is then separated from the encapsulating member.
  • First trench is then formed on a first surface of the encapsulating member.
  • Conductive material is disposed on the first surface of the encapsulating member and the outer surface of the first trench to form a conductive layer.
  • the conductive layer is patterned to form a circuit layer, so that the circuit layer is formed directly on the encapsulating member instead of a circuit board to reduce the volume of the packaging.
  • second trench is formed on the second surface of the encapsulating member.
  • the second trench and the first trench are interconnected.
  • a shielding structure is then formed in the first and the second trenches to reduce the electromagnetic and radio frequency interferences between encapsulating compartments.
  • An electromagnetic shielding layer is then formed and is electrically connected to grounding pads.
  • the electronic packaged device of the instant disclosure includes an encapsulating member and a shielding structure.
  • the shielding structure is interposed between different encapsulating compartments to reduce the electromagnetic and radio frequency interferences between encapsulating compartments.
  • the shielding structure can transmit electromagnetic interfering signals to the surrounding via grounding pads, and enhance the effects of electromagnetic shielding for the electronic packaged device.
  • FIGS. 1A to 1K are cross-sectional views illustrating steps of an electronic packaged device manufacturing method in accordance with a first embodiment of the instant disclosure
  • FIGS. 2A to 2C are cross-sectional views illustrating steps of the electronic packaged device manufacturing method in accordance with a second embodiment of the instant disclosure
  • FIGS. 3A to 3D are cross-sectional views illustrating steps of the electronic packaged device manufacturing method in accordance with a third embodiment of the instant disclosure.
  • FIG. 4 is a schematic diagram of an electronic packaged device in accordance with the first embodiment of the instant disclosure
  • FIGS. 1A to 1K are schematic diagrams illustrating steps of an electronic packaged device manufacturing method in accordance with a first embodiment of the instant disclosure.
  • a plurality of electronic components 120 is configured on a surface of a substrate carrier B 1 .
  • Adhesives A 1 are applied onto the surface of the substrate carrier B 1 to fix the electronic components 120 on the substrate carrier B 1 .
  • the electronic components 120 can be chips, transistors, diodes, capacitors, inductors, or the like.
  • the adhesives A 1 can be glue, double sided tape, adhesive inks or the like.
  • the coupling between the electronic components 120 and the substrate carrier B 1 is not limited to the examples provided herein.
  • An encapsulating member 130 is disposed on the surface of the substrate carrier to cover the electronic components 120 .
  • the encapsulating member 130 can be molding sealant or prepreg adhesives.
  • the encapsulating member 130 is at least partially adhered to the substrate carrier's B 1 surface and covers the electronic components 120 .
  • the encapsulating member 130 has a first surface S 1 and a second surface S 2 opposite the first surface S 1 .
  • the first surface S 1 is the bottom surface of the encapsulating member 130 and the second surface S 2 is the top surface of the encapsulating member 130 .
  • the first surface S 1 can be the top surface of the encapsulating member 130 and the second surface S 2 is the bottom surface of the encapsulating member 130 in another embodiment, and is not limited to the examples provided herein.
  • the adhesives A 1 are removed to separate the substrate carrier B 1 from the encapsulating member 130 .
  • the adhesives can be mechanically removed by scraping or sanding as well as thermally treating the adhesives to remove the adhesiveness.
  • solvents can be used to remove adhesives, but the removal of adhesives is not limited to the examples provided herein.
  • the manufacturing method of the electronic packaged device can further include forming a protective layer P 1 covering over the encapsulating member 130 .
  • the protective layer P 1 is formed on the surface of the encapsulating member 130 covering thereof at desired positions where the trenches are to be formed, in which minimizes contamination to post-processing procedures or structures by particles or powder generated during the formation of the trenches.
  • the protective layer P 1 can be insulating ink coating or photoresist, but not limited to the examples provided herein.
  • the protective layer P 1 is formed on the first surface S 1 .
  • a plurality of first trenches T 1 and a plurality of first grounding trenches G 1 are formed in the encapsulating member 130 .
  • the first trenches T 1 and first grounding trenches G 1 are formed by laser L 1 ablation through the surface of the protective layer P 1 to portions of the encapsulating member 130 .
  • a packaged unit U 1 is defined as a pre-determined region where a single packaged unit is obtained from the post process of singularization, and the single packaged unit is the electronic packaged device.
  • the first trenches T 1 are arranged at the regions between electronic components 120
  • the first grounding trenches G 1 are arranged between the packaged units U 1 .
  • the first trenches T 1 and first grounding trenches G 1 are not formed through the second surface S 2 of the encapsulating member 130 .
  • the first trenches T 1 can be of various shapes and bends to divide into three or more encapsulating compartments 130 a in an embodiment but is not limited to the example provided herein.
  • the protective layer P 1 is removed.
  • powder or particles are generated when portions of the encapsulating member 130 are being removed to form the first trenches T 1 and the first grounding trenches G 1 .
  • Majority of those particles tends to stick onto the surface of the protective layer P 1 .
  • solvent can be used to remove the protective layer P 1 as well as the particles.
  • Conductive material is disposed onto the first surface S 1 of the encapsulating member 130 and filled into the first trenches T 1 as well as the first grounding trenches G 1 .
  • the conductive material is disposed by spray coating, printing, electroplating or injection onto the first surface S 1 of the encapsulating member 130 , the first trenches T 1 , and the first grounding trenches G 1 to at least cover the surface of the first trenches T 1 and the first grounding trenches G 1 .
  • the conductive material covers the first surface S 1 to form a conductive layer 110 ′.
  • the conductive material is also filled into the first trenches T 1 and the first grounding trenches G 1 to form a plurality of grounding structures 160 . Successively, the conductive material is cured for solidification.
  • the conductive layer 110 ′ on the first surface S 1 is patterned to form a circuit layer 110 .
  • the circuit layer 110 includes at least one grounding pad 112 electrically connected to the grounding structure 160 .
  • the circuit layer 110 also includes the ground connections to active components and passive components.
  • the circuit layer 110 is a re-distribution layer.
  • the circuit layer 110 is arranged on the bottom surface of the packaged unit U 1 , whereas the grounding pad 112 is re-layout on the surrounding of the bottom surface of the packaged unit U 1 in the instant embodiment.
  • the grounding pad 112 can be arranged elsewhere due to various designs of the grounding circuits, and the arrangement of the grounding pad 112 is not limited to the examples provided herein.
  • a plurality of second trenches T 2 corresponding to the first trenches T 1 is formed on the second surface S 2 of the encapsulating member 130 .
  • a protective layer P 1 can be formed to cover the surface of the circuit layer 110 .
  • the protective layer P 1 can be first formed to cover the circuit layer 110 in order to prevent short circuiting due to contamination of the circuit layer 110 .
  • the depths of the first trenches T 1 and the second trenches T 2 vary, where the depth of the first trenches T 1 is about 70% of the depth of the encapsulating member 130 .
  • the first and the second trenches are interconnected to divide the encapsulating member 130 into at least two encapsulating compartments 130 a.
  • FIG. 1I Forming at least one shielding structure 140 in the first trenches T 1 as well as the second trenches T 2 .
  • conductive material 151 is spray coated or sputtered onto the second surface S 2 and onto outer surface of the second trenches T 2 .
  • the conductive material on the surface of the second trench T 2 and the conductive material in the first trench T 1 are electrically connected to form the shielding structure 140 .
  • the shielding structure 140 and the grounding pas 113 can be electrically connected according to the various grounding circuit designs.
  • the encapsulating member 130 is cut at the second surface S 2 corresponding to the grounding structures 160 to divide into the plurality of packaged units U 1 .
  • the electromagnetic shielding layer 150 is formed to cover the encapsulating member 130 . Since the plurality of packaged units U 1 are formed by cutting the encapsulating member 130 at the second surface S 2 corresponding to the grounding structures 160 , the grounding structures 160 are exposed at the sides of the packaged units U 1 . The exposed sides and top outer surfaces, also denoted as the external sides, of the packaged units U 1 are spray coated or sputter with conductive material thereon to form a continuous layer of electromagnetic shielding layer 150 across the exposed sides and top outer surfaces, or the external sides, of the packaged units U 1 .
  • the formation of the electromagnetic shielding layer 150 is not limited to example provided herein. Notably, the electromagnetic shielding layer 150 , the grounding structure 160 and the grounding pads 112 are electrically connected.
  • the protective layer P 1 is then removed with solvents to simultaneously remove powder or particles on the protective layer P 1 .
  • the electronic packaged device 100 is substantially provided.
  • the electronic packaged device manufacturing method can be applied to wafer level chip scale package (WLCSP) to package chips without the need of a substrate carrier or PCB, which improves upon the need to have electrically connection with the substrate carrier as in the conventional flip chip or wire bonding technology and also reduces the overall packaging volume.
  • WLCSP wafer level chip scale package
  • the electromagnetic shielding layer 150 and the grounding pads 112 of the instant disclosure are electrically connected to reduce the effects of electromagnetic and radio frequency interferences.
  • FIGS. 2A to 2C are schematic diagrams illustrating steps of the electronic packaged device manufacturing method in accordance with a second embodiment of the instant disclosure. The differences between the electronic packaged device method of the first and the second embodiments are further discloses as follows.
  • FIG. 1G in conjunction with FIG. 2A as a continuation of the manufacturing method for the second embodiment.
  • a plurality of second trenches T 2 and a plurality of second grounding trenches G 2 are formed on the second surface S 2 of the encapsulating member 130 .
  • laser L 1 ablation is applied to removed portions of the encapsulating member 130 to form the second trenches T 2 and second grounding trenches G 2 in the second embodiment.
  • the second trenches T 2 correspond to and are interconnected to the first trenches T 1
  • the second grounding trenches G 2 corresponding to the first grounding trenches G 1 are electrically and physically connected to the first grounding trenches G 1 to divide into at least two encapsulating compartments 130 a.
  • Conductive material 151 is formed on the second surface S 2 , and in the second trenches T 2 as well as second grounding trenches G 2 of the encapsulating member 130 .
  • conductive material 151 is spray coated or sputter or injection or printing on the second surface S 2 , and in the second trenches T 2 as well as second grounding trenches G 2 of the encapsulating member 130 .
  • the conductive material 151 formed on the second surface S 2 of the encapsulating member 130 is an electromagnetic shielding layer 150 , whereas the conductive material 151 formed in the second trenches T 2 and the conductive material 151 formed in the first trenches T 1 are interconnected to form at least one shielding structure 240 , meanwhile, the conductive material 151 formed in the second grounding trenches G 2 and the conductive material 151 formed in the first grounding trenches G 1 are electrically connected to form a plurality of grounding structures 260 . Successively, the grounding structures 260 of the encapsulating member 130 are cut through from the second surface S 2 to divide into a plurality of packaged units U 1 .
  • the electromagnetic shielding layer 150 covering the second surface S 2 are physically connected to the shielding structures 240 and the grounding structures 260 disposed on sides of the electronic packaged devices 200 , whereas the electromagnetic shielding layer 150 , the shielding structures 240 , and the grounding structures 260 are electrically connected to each other.
  • the electromagnetic shielding layer 150 on the surface of the packaged units U 1 provides electromagnetic shielding via the grounding structures 260 .
  • the electromagnetic shielding layer 150 covers the encapsulating member 130 and is electrically connected to the grounding pads 112 .
  • FIGS. 3A to 3D are schematic diagrams illustrating steps of the electronic packaged device manufacturing method in accordance with a third embodiment of the instant disclosure. The differences between the electronic packaged device method of the third and the second embodiments are further discloses as follows. Please refer to FIGS. 3A to 3D .
  • a plurality of through holes V 1 is formed on the first trenches T 1 via laser L 1 ablation.
  • the through holes V 1 have small diameters and formed from the first trenches T 1 through the encapsulating member 130 and to the second surface S 2 .
  • the diameters of the through holes V 1 range from about 20 to 40 microns ( ⁇ m).
  • Conductive material is disposed on the first surface S 1 and into the first trenches T 1 as well as in to the first grounding trenches G 1 .
  • conductivies materials are spray coated, printed, sputter, or injected on the first surface S 1 of the encapsulating member 130 as well as filling in the first trenches T 1 and the first grounding trenches G 1 to form the conductive layer 110 ′.
  • Suction is then provided from the second surface S 2 of the encapsulating member 130 via the through holes V 1 , such that the conductive material can smoothly flow into the first trenches T 1 .
  • the conductive material covers the first trenches T 1 , the surface of the first grounding trenches G 1 , as well as filling in the first trenches T 1 and the first grounding trenches G 1 to form the plurality of grounding structures 160 . Successively, the conductive material is cured for solidification.
  • the conductive layer 110 ′ of the first surface S 1 of the encapsulating member 130 is patterned to form a circuit layer 110 .
  • the circuit layer 110 includes at least one grounding pad 112 electrically connected to the grounding structure 160 .
  • the circuit layer 110 is a re-distribution layer in the instant embodiment.
  • Second trenches T 2 are formed on the second surface S 2 of the encapsulating member 130 .
  • the second trenches T 2 are formed by removing portions of the encapsulating member 130 from the position proximate to the through holes V 1 .
  • the second trenches T 2 and the first trenches T 1 are electrically connected.
  • the width of the first and the second trenches T 1 , T 2 are identical.
  • the width of the first and second trenches T 1 , T 2 can be different and are not limited to the examples provides herein.
  • FIGS. 1I to IK Please refer to FIGS. 1I to IK as a continuation of the manufacturing method in FIG. 3D for the instant embodiment.
  • the electronic packaged device 100 includes a circuit layer 110 , a plurality of electronic components 120 , an encapsulating member 130 , a shielding structure 140 , at least one grounding structure 160 , and a electromagnetic shielding layer 150 .
  • the electronic components 120 and the circuit layer 110 are electrically connected.
  • the encapsulating member 130 covers at least one electronic component 120 and includes at least two encapsulating compartments 130 a .
  • the shielding structure 140 is interposed between different encapsulating compartments 130 a , and the electromagnetic shielding layer 150 is formed on the encapsulating member 130 .
  • the circuit layer 110 includes grounding pads 112 and electric circuits.
  • the circuit layer 110 is a redistribution layer so the grounding pads 112 are re-layout proximate to the surrounding of the bottom surface of the packaged units U 1 .
  • the grounding pads 112 and the electric circuits can be configured according to the arrangement of the electronic components.
  • Electronic components 120 can be of various kinds and are not necessarily identical. Examples of electronic components 120 can be chips, transistors, diodes, capacitors, inductors or the like. As shown in FIG. 4 , the electronic components 120 can be various sizes and shapes or types, and are not limited to the examples provides herein.
  • the encapsulating member 130 includes a first surface S 1 and an oppositely arranged second surface S 2 .
  • the first surface S 1 is the bottom surface of the encapsulating member 130 and is in contact with the circuit layer 110
  • the second surface S 2 is the top surface of the encapsulating member 130 .
  • the first trenches T 1 and the second trenches T 2 are respectively formed on the first surface S 1 and the second surface S 2 of the encapsulating member 130 .
  • the first trenches T 1 and the second trenches T 2 inwardly extend in the encapsulating member 130 , such that the first and the second trenches T 1 , T 2 are interconnected.
  • the first and the second trenches T 1 , T 2 cooperatively defines a region therebetween as a trench F 1 .
  • the trench F 1 extend through the top surface (second surface S 2 ) of the encapsulating member 130 to the bottom surface (first surface S 1 ) of the encapsulating member 130 to divide into at least two encapsulating compartments 130 a.
  • the encapsulating member 130 includes two encapsulating compartments 130 a each covering at least one electronic component 120 .
  • the encapsulating member 130 can include three or more encapsulating compartments 130 a that can cover the electronic components 120 , but the number of components is not limited to the examples provided herein.
  • the encapsulating member 130 can be molding sealant to prevent unnecessary electrical connectivity, short circuiting, or the like.
  • the encapsulating member 130 can be pre-impregnated material (prepreg) such as glass fiber prepreg, carbon fiber prepreg, epoxy resin, or the like.
  • the shielding structure 140 is disposed in the trench F 1 between the encapsulating compartments 130 a .
  • the shielding structure 140 is disposed in the encapsulating member 130 and extends from the top surface to the bottom surface of the encapsulating member 130 , such that various encapsulating compartments 130 a can be divided.
  • the shielding structure 140 includes a first portion 140 a and a second portion 140 b .
  • Conductive material 151 is spray coated, printed, sputter, or injected into the first trench T 1 to form the first portion 140 a
  • conductive material 151 is spray coated or sputter on the outer surface of the second trench T 2 to form the second portion 104 b .
  • the conductive material on the outer surface of the second trench T 2 is electrically connected to the conductive material in the first trench T 1
  • the first portion 140 a and the second portion 140 b are electrically connected to form the shielding structure 140 .
  • the shielding structure 140 reduces electromagnetic and radio frequency interferences between the encapsulating compartments 130 a .
  • the shielding structure 140 provides further electromagnetic shielding of the electronic packaged device by transmitting electromagnetic interferences to the ground via the grounding pads 112 , and further enhances the effects of electromagnetic shielding between electronic components 120 covered in the encapsulating compartments 130 a.
  • the shielding structure 140 is made of metal such as copper, aluminum, silver, nickel or the like.
  • the shielding structure 140 can also be conductive polymers such as polyaniline (PAn), polypyrrole (PYy), polythiophene (PTh) or the like, and is not limited to the examples provided herein.
  • the electromagnetic shielding layer 150 is formed on the second surface S 2 and the exposed sides of the encapsulating member 130 .
  • the electromagnetic shielding layer 150 is electrically connected to the second portion 140 b of the shielding structure 140 .
  • the electromagnetic shielding layer 150 reduces surrounding electromagnetic interferences from the electronic components 120 .
  • the grounding structure 160 is exposed at the cut sides of the encapsulating member 130 and is electrically connected to the grounding pads 112 .
  • the electromagnetic shielding layer 150 covers the top outer surface and exposed sides (the top outer surface and the exposed sides are denoted as the external sides) of the encapsulating member 130 .
  • the electromagnetic shielding layer 150 covers exposed sides of the grounding pads 112 and electrically connected to the grounding structure 160 and the grounding pads 112 , such that the electromagnetic shielding layer 150 can transmit electromagnetic interfering signals to the grounding pads 112 of the circuit layer 110 , and enhance electromagnetic shielding effects for the electronic packaged device.
  • the electromagnetic shielding layer 150 can also cover only the top surface and the exposed sides of the encapsulating member 30 while not extended to the grounding pads 112 . As a result, the electromagnetic shielding layer 150 can transmit electromagnetic interfering signals to the ground via the grounding structure 160 .
  • the structure of the electronic packaged device in accordance with the instant disclosure can be applied to wafer level chip scale package (WLCSP) to package chips without the need of a substrate carrier or PCB, which improves upon the need to have electrically connection with the substrate carrier as in the conventional flip chip or wire bonding technology and also reduces the overall packaging volume.
  • WLCSP wafer level chip scale package
  • the electromagnetic shielding layer 150 and the grounding pads 112 of the instant disclosure are electrically connected to reduce the effects of electromagnetic and radio frequency interferences.
  • FIG. 2C schematic diagrams illustrating the structure of the electronic packaged device in accordance with the second embodiment of the instant disclosure.
  • the electronic packaged device 200 and the electronic packaged device 100 are similar, so the differences will be disclosed as follow.
  • the shielding structure 240 is formed by spray coating, sputtering, printing, injection or the like to fill the trench F 1 with conductive material.
  • the shielding structure 240 extends from the first surface S 1 (bottom surface) to the second surface S 2 (top surface) of the encapsulating member 130 and is electrically connected to the electromagnetic shielding layer 150 .
  • the electromagnetic shielding layer 150 covers the second surface S 2 of the encapsulating member 130 to electrically connect to the shielding structure 240 , and the electromagnetic shielding layer 150 is physically and electrically connected to the grounding structure 260 at the sides of the electronic packaged device 200 .
  • the sides of the electronic packaged device 200 are electromagnetic shielded by the grounding structure 260 .
  • the electromagnetic shielding layer 150 covers the encapsulating member 130 and is electrically connected to the grounding pads 112 .
  • the instant disclosure provides a package device manufacturing method.
  • Electronic components are fixed onto a substrate carrier by adhesives, and an encapsulating member is disposed on the surface of the substrate carrier to cover the electronic components.
  • the substrate carrier is then separated from the encapsulating member.
  • First trench is then formed on a first surface of the encapsulating member.
  • Conductive material is disposed on the first surface and the outer surface of the first trench to form a conductive layer.
  • the conductive layer is patterned to form a circuit layer, so that the circuit layer is formed directly on the encapsulating member instead of a circuit board to reduce the volume of the packaging.
  • second trench is formed on the second surface of the encapsulating member.
  • the second trench and the first trench are interconnected.
  • a shielding structure is then formed in the first and the second trenches to reduce the electromagnetic and radio frequency interferences between encapsulating compartments.
  • An electromagnetic shielding layer is then formed and is electrically connected to grounding pads.
  • the electronic packaged device of the instant disclosure includes an encapsulating member and a shielding structure.
  • the shielding structure is interposed between different encapsulating compartments to reduce the electromagnetic and radio frequency interferences between encapsulating compartments.
  • the shielding structure can transmit electromagnetic interfering signals to the surrounding via grounding pads, and enhance electromagnetic shielding for the electronic packaged device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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US20160081235A1 (en) 2016-03-17
US20150173258A1 (en) 2015-06-18
US9674991B2 (en) 2017-06-06
TWI509767B (zh) 2015-11-21

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