CN102364683A - 封装结构、方法、及电子设备 - Google Patents
封装结构、方法、及电子设备 Download PDFInfo
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Abstract
本发明实施例公开了一种封装结构、方法、及电子设备,其中,该封装结构包括:基板(21),基板(21)上布设有接地端(27)和至少两个电路模块;屏蔽隔筋(24),连接在基板(21)上,以分隔所述至少两个电路模块;封装绝缘体(25),敷设于基板(21)上以包覆所述至少两个电路模块,封装绝缘体(25)低于屏蔽隔筋(24);导电涂层(26),与接地端(27)连接,敷设于封装绝缘体(25)上,以包覆封装绝缘体(25)和屏蔽隔筋(24)。应用本发明实施例可以在封装结构内部形成多个屏蔽区,减少了封装结构内部模块之间的电磁干扰,同时,增加了封装结构内部电路的功能发挥。
Description
技术领域
本发明实施例涉及电子技术,尤其涉及一种封装结构、方法、及电子设备。
背景技术
电磁干扰是大多数电子设备和电路系统面临的一个严峻的问题,由于电磁干扰常中断、阻碍、降低电子设备或电路系统的性能,因此需要有效的电磁干扰屏蔽,确保电子设备或电路系统的效率和安全操作。
现有的封装技术大多采用膜技术或者微细连接技术,如半导体封装结构,将半导体芯片和基板中的导体部分连接以便引出接线引脚,并通过可塑性绝缘介质灌封固定,之后,使用导电涂层把封装体包覆住,并通过同封装体的外露“地”连接,形成接地,构成一个封装体,该封装体不仅具有屏蔽的效果,还具有电路连接,物理支撑和保护等作用。
在实现本发明的过程中,发明人发现现有技术中至少存在如下问题:现有的封装结构及封装方法只能形成一个全覆盖的屏蔽,限制了封装体内部电路的功能。
发明内容
本发明实施例提供一种封装结构、方法、及电子设备,用以解决现有的封装结构及封装方法只能形成一个全覆盖的屏蔽,限制了封装体内部电路的功能发挥的技术问题。
一方面,本发明实施例提供了一种封装结构,包括:
基板21,所述基板21上布设有接地端27和至少两个电路模块;
屏蔽隔筋24,连接在所述基板21上,以分隔所述至少两个电路模块;
封装绝缘体25,敷设于所述基板21上以包覆所述至少两个电路模块,所述封装绝缘体25低于所述屏蔽隔筋24;
导电涂层26,与所述接地端27连接,敷设于所述封装绝缘体25上,以包覆所述封装绝缘体25和所述屏蔽隔筋24。
另一方面,本发明实施例还提供了一种封装方法,包括:
将屏蔽隔筋连接在包括至少两个电路模块的基板上,以分隔所述至少两个电路模块;
将封装绝缘体敷设在所述基板上以包覆所述至少两个电路模块;
将导电涂层敷设在所述绝缘封装体上,以包覆所述绝缘封装体和所述屏蔽隔筋,且将所述导电涂层与所述基板的接地端连接。
另一方面,本发明实施例还提供了一种电子设备,包括上述封装结构。
由于采用了连接在基板上的屏蔽隔筋,将至少两个电路模块分隔开,再敷设封装绝缘体和导电涂层,并通过导电涂层将屏蔽隔筋接地的技术手段,在封装结构内部形成多个隔离的屏蔽部分,从而形成多个屏蔽区,减少了封装结构内部电路模块之间的电磁干扰,同时,增加了封装结构内部电路的功能发挥。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术的一种半导体电路封装结构的正视截面示意图;
图2a为本发明实施例一提供的封装结构的俯视截面示意图;
图2b为本发明实施例一提供的封装结构的正视截面示意图;
图3a为本发明实施例二提供的封装结构的俯视截面示意图;
图3b为本发明实施例二提供的封装结构的正视截面示意图;
图3c为本发明实施例二提供的封装结构的侧视截面示意图;
图4为本发明实施例三提供的封装方法的流程示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
图1为现有技术的一种半导体电路封装结构的正视截面示意图,如图1所示,该封装结构包括:
基板11,该基板11布设有接地端15、半导体电路12和半导体电路16;
封装绝缘体13,敷设于基板11上,用以包覆半导体电路12和半导体电路16;
导电涂层14,敷设于封装绝缘体13和基板11上、用于包覆封装绝缘体13和该封装绝缘体13外侧周围未覆盖的的基板11表面,该导电涂层14与基板11的接地端15连接,用以构成该半导体电路基板封装结构的电磁屏蔽接地电路。具体地,接地端15位于封装绝缘体13外侧未包覆的基板11上的一侧部分,被导电涂层14覆盖。
由此可见,现有技术的封装结构只能形成一个全覆盖的屏蔽,也就是说,现有技术的封装结构能够使该封装结构内部电路屏蔽外界的电磁干扰;但是,正因为现有技术的封装结构只能形成一个全覆盖的屏蔽,而不能分别形成几个屏蔽区,若该封装结构内部有若干个电路模块,该若干个电路模块之间也容易产生电磁干扰,同时也会影响封装结构内部的若干个电路模块的功能。
实施例一
针对现有技术存在的上述问题,本发明实施例通过在基板上连接(优选为焊接)屏蔽隔筋将至少两个电路模块分隔开,再敷设封装绝缘体和导电涂层,并通过导电涂层将屏蔽隔筋接地,可以在封装结构内部形成多个隔离的屏蔽部分,从而形成多个屏蔽区,减少了封装结构内部电路模块之间的电磁干扰。
图2a为本发明实施例一提供的封装结构的俯视截面示意图,图2b为本发明实施例一提供的封装结构的正视截面示意图,如图2a和图2b所示,该封装结构包括:
基板21,基板21上布设有接地端27和至少两个电路模块,即电路模块22和电路模块23;
屏蔽隔筋24,连接在基板21上,以分隔所述至少两个电路模块;
封装绝缘体25,敷设于基板21上以包覆所述至少两个电路模块,其中,封装绝缘体25低于屏蔽隔筋24;
导电涂层26,与基板21的接地端27连接,敷设于封装绝缘体25上,以包覆封装绝缘体25和屏蔽隔筋24。
其中,基板21可以是树脂基板或玻璃基板或半导体基板或金属基板。电路模块可以为半导体电路或模块电路或系统级封装模块(System inpackage,简称SIP模块)或晶片电路或芯片电路。
特别的,基板21上布设至少两个电路模块具体为:利用具有固定功能的黏着剂,将电路模块22和电路模块23固定在基板21的上表面,并进行一打线结合制成或者覆晶结合制成,用导线或锡球将电路模块22和电路模块23的表面焊接垫分别与基板21表面的各相对焊接垫进行电性连接。基板21上布设有接地端27具体为:将接地端27通过基板21内部电路电性连接至接地点。
屏蔽隔筋24,可以是金属隔筋、硅橡胶隔筋等,用以分隔电路模块22和电路模块23;本实施例的屏蔽隔筋24优选为焊接在基板21上,且将屏蔽隔筋24通过导电涂层26接地,使得屏蔽隔筋24外侧的正电荷流入大地,以使外侧不会有电场存在,即带正电导体的电场被屏蔽在屏蔽隔筋24内。
封装绝缘体25,可以是环氧树脂、硅树脂等,用以保护电路模块免受外力、湿气或其他物质的破坏和腐蚀。
导电涂层26,可以是包含金属材质的导电粒子与环氧树脂、聚氨酯等黏着剂,利用涂布、喷涂或印刷等方式敷设于封装绝缘体25表面上,用以包覆封装绝缘体25和屏蔽隔筋24。本实施例的导电涂层26可直接覆盖于基板21的接地端27上方,或者通过焊线电性连接至所述接地端27,使得导电涂层26电性连接至零电位的接地点,用以构成该封装结构的电磁屏蔽接地电路。
该实施例的封装结构采用了连接在基板上的屏蔽隔筋,将至少两个电路模块分隔开,再敷设封装绝缘体和导电涂层,并通过导电涂层将屏蔽隔筋接地的技术手段,在封装结构内部形成多个屏蔽区,减少了封装结构内部电路模块之间的电磁干扰,同时,增加了封装结构内部电路的功能发挥。
实施例二
图3a为本发明实施例二提供的封装结构的俯视截面示意图,图3b为本发明实施例二提供的封装结构的正视截面示意图,图3c为本发明实施例二提供的封装结构的侧视截面示意图,实施例二是在图2a,2b所示的实施例一的基础上,以半导体电路为例,对实施例一进行扩展而形成,具体为:本发明实施例的屏蔽隔筋优选为金属隔筋,具有低电阻、导电性好的优点,其中,金属隔筋的上表面包括多个突起部分,该突起部分优选为锯齿,但并不限定于锯齿,该锯齿的纵截面具体包括三角形或圆弧形,但并不限于三角形或圆弧形。如图3a、图3b和图3c所示,本实施例的封装结构包括:
基板31,表面设置有接地端37,基板31布设有半导体电路32、半导体电路33、半导体电路38、半导体电路39;其中,本实施例的基板31的接地端37可通过基板31内部电路电性连接至接地点;举例来说,本实施例的基板31为半导体基板,半导体电路32为可读存储器,半导体电路33为模拟电路,半导体电路38为放大器,半导体电路39为振荡器,本发明实施例中的半导体电路并不限定具体的举例,半导体电路可以根据具体电路而定;本实施例,利用具有固定功能的黏着剂,将半导体电路32固定在基板31的上表面,并进行一打线结合制成或者覆晶结合制成,用导线或锡球将半导体电路32表面的焊接垫与基板31表面的各相对焊接垫进行电性连接;同理,将半导体电路33、半导体电路38、半导体电路39电性连接在基板31上。
金属隔筋34,连接优选为焊接在基板31上,金属隔筋34的上表面包括多个突起部分,该突起部分优选为锯齿,金属隔筋34呈十字交叉将半导体电路32、半导体电路33、半导体电路38和半导体电路39分隔开,本实施例的金属隔筋34并不限于十字交叉状,只要能将封装结构内部电路模块分隔开的任一形状都属于本发明实施例保护的范围。
封装绝缘体35,敷设在基板31上,用于包覆半导体电路32、半导体电路33、半导体电路38、半导体电路39;
导电涂层36,敷设在封装绝缘体35上,用于包覆金属隔筋34和封装绝缘体35的上表面、侧壁与封装绝缘体35周围的基板31表面。本实施例的导电涂层36与金属隔筋34的锯齿连接,使得金属隔筋34与导电涂层36相连;本实施例的导电涂层36可直接覆盖于基板31的接地端37上方,或者通过焊线电性连接至所述接地端37,使得导电涂层36电性连接至零电位的接地点,用以构成该半导体电路封装结构的电磁屏蔽接地电路。
该实施例采用在半导体电路之间的基板上焊接金属隔筋,将半导体电路分隔开,通过金属隔筋的锯齿使得金属隔筋与导电涂层接地连接,在半导体电路之间形成相互隔离的多个屏蔽部分,最终在半导体电路封装结构内部形成多个隔离的屏蔽部分,有效降低半导体电路内部电路模块之间的电磁辐射干扰,增加了封装结构内部电路的功能发挥,同时本实施例的金属隔筋上表面采用锯齿可以简化封装结构的制作工艺流程,并降低了封装结构的制作成本。
虽然本发明实施例二中的电路模块以半导体电路为例进行了描述,本领域技术人员可以根据本发明实施例二和公知常识很容易地将电路模块替换为芯片电路、晶片电路、SIP模块,得到芯片电路封装结构、晶片电路封装结构、SIP模块封装结构。
实施例三
本实施例通过在基板上连接屏蔽隔筋将至少两个电路模块分隔开,再敷设封装绝缘体和导电涂层,并通过导电涂层将屏蔽隔筋接地,可以在封装结构内部形成多个屏蔽区,减少了封装结构内部电路模块之间的电磁干扰。
图4为本发明实施例三提供的封装方法的流程示意图。如图4所示,该方法包括:
步骤401、将屏蔽隔筋连接在包括至少两个电路模块的基板上,以分隔所述至少两个电路模块;
步骤402、将封装绝缘体敷设在所述基板上以包覆所述至少两个电路模块,所述绝缘封装体低于所述屏蔽隔筋;
步骤403、将导电涂层敷设在所述绝缘封装体上,以包覆所述绝缘封装体和所述屏蔽隔筋,且将所述导电涂层与所述基板的接地端连接。
本发明实施例三提供的封装方法可以实现本发明实施例一提供的封装结构,该封装结构的实现原理和技术效果不再赘述。
其中,当屏蔽隔筋优选为金属隔筋,且金属隔筋的上表面包括多个锯齿时,本实施例的封装方法还包括:将金属隔筋焊接在基板上,用于分隔基板上的电路模块,金属隔筋的上表面设计成“锯齿”形状,在封装绝缘体时,金属隔筋被绝缘体覆盖后,在后续的喷沙工序中,将绝缘体表面稍微减薄,以使露出金属隔筋锯齿即可,然后进行导电涂层的涂覆,通过锯齿将金属隔筋和导电涂层接地,最终在封装结构内部形成多个隔离的屏蔽部分。
本实施例采用将金属隔筋的上表面设计成锯齿形状,因此当金属隔筋被封装绝缘体覆盖后,在后续喷沙工序中,很容易将封装绝缘体表面减薄,就可以露出金属隔筋的锯齿上表面,因此简化了现有的封装方法的工艺流程,并降低了制作成本。
本发明实施例的至少一个封装结构可以应用到电子芯片、半导体集成电路、数据卡等多种电子设备中,本领域技术人员可以理解,只要是存在至少两个电路模块的场合,为了防止干扰均可以采用本发明实施例中的封装结构。
最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。
Claims (12)
1.一种封装结构,其特征在于,包括:
基板(21),所述基板(21)上布设有接地端(27)和至少两个电路模块;
屏蔽隔筋(24),连接在所述基板(21)上,以分隔所述至少两个电路模块;
封装绝缘体(25),敷设于所述基板(21)上以包覆所述至少两个电路模块,所述封装绝缘体(25)低于所述屏蔽隔筋(24);
导电涂层(26),与所述接地端(27)连接,敷设于所述封装绝缘体(25)上,以包覆所述封装绝缘体(25)和所述屏蔽隔筋(24)。
2.根据权利要求1所述的封装结构,其特征在于,所述屏蔽隔筋(24)的上表面包括多个突起部分。
3.根据权利要求2所述的封装结构,其特征在于,所述突起部分优选为锯齿。
4.根据权利要求3所述的封装结构,其特征在于,所述锯齿的纵截面为三角形或圆弧形。
5.根据权利要求1~4中任一项所述的封装结构,其特征在于,所述导电涂层(26)敷设在所述接地端(27)上。
6.根据权利要求1~4中任一项所述的封装结构,其特征在于,所述导电涂层(26)通过焊线电性连接至所述接地端(27)。
7.根据权利要求1~6中任一项所述的封装结构,其特征在于,所述至少两个电路模块包括:芯片电路或晶片电路或半导体电路。
8.一种封装方法,其特征在于,包括:
将屏蔽隔筋连接在包括至少两个电路模块的基板上,以分隔所述至少两个电路模块;
将封装绝缘体敷设在所述基板上以包覆所述至少两个电路模块;
将导电涂层敷设在所述绝缘封装体上,以包覆所述绝缘封装体和所述屏蔽隔筋,且将所述导电涂层与所述基板的接地端连接。
9.根据权利要求8所述的方法,其特征在于,所述将所述导电涂层与所述基板的接地端连接具体包括:将所述导电涂层敷设在接地端上。
10.根据权利要求8所述的方法,其特征在于,所述将所述导电涂层与所述基板的接地端连接具体包括:将所述导电涂层通过焊线电性连接至所述接地端。
11.一种电子设备,其特征在于,包括如权利要求1~7中任一项所述的封装结构。
12.根据权利要求11所述的电子设备,其特征在于,所述电子设备包括数据卡。
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Also Published As
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EP2584605A2 (en) | 2013-04-24 |
US20130119523A1 (en) | 2013-05-16 |
WO2013056629A1 (zh) | 2013-04-25 |
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