US9136204B2 - Semiconductor device having penetrating electrodes each penetrating through substrate - Google Patents

Semiconductor device having penetrating electrodes each penetrating through substrate Download PDF

Info

Publication number
US9136204B2
US9136204B2 US13/780,979 US201313780979A US9136204B2 US 9136204 B2 US9136204 B2 US 9136204B2 US 201313780979 A US201313780979 A US 201313780979A US 9136204 B2 US9136204 B2 US 9136204B2
Authority
US
United States
Prior art keywords
penetrating
penetrating electrode
electrodes
electrode
penetrating electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US13/780,979
Other languages
English (en)
Other versions
US20130228898A1 (en
Inventor
Akira Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Longitude Licensing Ltd
Original Assignee
PS4 Luxco SARL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PS4 Luxco SARL filed Critical PS4 Luxco SARL
Assigned to ELPIDA MEMORY, INC. reassignment ELPIDA MEMORY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IDE, AKIRA
Assigned to ELPIDA MEMORY INC. reassignment ELPIDA MEMORY INC. SECURITY AGREEMENT Assignors: PS4 LUXCO S.A.R.L.
Publication of US20130228898A1 publication Critical patent/US20130228898A1/en
Assigned to PS4 LUXCO S.A.R.L. reassignment PS4 LUXCO S.A.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ELPIDA MEMORY, INC.
Application granted granted Critical
Publication of US9136204B2 publication Critical patent/US9136204B2/en
Assigned to LONGITUDE SEMICONDUCTOR S.A.R.L. reassignment LONGITUDE SEMICONDUCTOR S.A.R.L. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: PS5 LUXCO S.A.R.L.
Assigned to PS5 LUXCO S.A.R.L. reassignment PS5 LUXCO S.A.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PS4 LUXCO S.A.R.L.
Assigned to LONGITUDE LICENSING LIMITED reassignment LONGITUDE LICENSING LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LONGITUDE SEMICONDUCTOR S.A.R.L.
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Definitions

  • the present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with a penetrating electrode which is so provided as to pass through a substrate.
  • a semiconductor device that includes a first semiconductor chip including a first internal circuit formed in a first semiconductor substrate, and a plurality of penetrating electrodes each penetrating through the first semiconductor substrate.
  • the plurality of penetrating electrodes includes first, second, third and fourth penetrating electrodes arranged along a first line.
  • the first and second penetrating electrodes are in a floating state without electrically being connected to the first internal circuit.
  • the third penetrating electrode is electrically connected to a first power supply line that conveys a first power supply potential to the first internal circuit.
  • the fourth penetrating electrode is electrically connected to a second power supply line that conveys a second power supply potential to the first internal circuit.
  • the third and fourth penetrating electrodes are arranged between the first penetrating electrode and the second penetrating electrode.
  • semiconductor device in another embodiment, includes a semiconductor chip including an internal circuit and a semiconductor substrate, and a plurality of penetrating electrodes each penetrating through the semiconductor substrate.
  • the plurality of penetrating electrodes include a first penetrating electrode group arranged along a first line.
  • the first penetrating electrode group includes a first penetrating electrode arranged closest to a first side of the semiconductor chip among the first penetrating electrode group.
  • the first penetrating electrode is in a floating state without being electrically connected to the internal circuit.
  • a semiconductor device that includes: an interposer having a first surface on which a plurality of substrate electrodes are provided; a first semiconductor chip mounted on the first surface of the interposer, the first semiconductor chip includes a first penetrating electrode group including a plurality of penetrating electrodes each penetrating through a first semiconductor substrate and arranged along a first line; and a second semiconductor chip mounted over the first semiconductor chip, the second semiconductor chip includes a second penetrating electrode group having a plurality of penetrating electrodes each penetrating through a second semiconductor substrate.
  • the first penetrating electrode group includes a first penetrating electrode arranged closest to a first side of the first semiconductor chip, and a second penetrating electrode arranged far from the first side compared with the first penetrating electrode.
  • the second penetrating electrode group includes third and fourth penetrating electrodes vertically aligned with the first and second penetrating electrodes, respectively.
  • the first semiconductor chip includes a second surface that faces the first surface of the interposer, a third surface positioned opposite to the second surface, first and second bump electrodes provided on the second surface and vertically aligned with the first and second penetrating electrodes, respectively, and third and fourth bump electrodes provided on the third surface and vertically aligned with the first and second penetrating electrodes, respectively.
  • the second semiconductor chip includes a fourth surface that faces the third surface of the first semiconductor chip, a fifth surface positioned opposite to the fourth surface, fifth and sixth bump electrodes provided on the fourth surface and vertically aligned with the third and fourth penetrating electrodes, respectively, and seventh and eighth bump electrodes provided on the fifth surface and vertically aligned with the third and fourth penetrating electrodes, respectively.
  • the third bump electrode and the fifth bump electrode are bonded to each other, and the fourth bump electrode and the sixth bump electrode are bonded to each other.
  • the plurality of substrate electrodes include a first substrate electrode vertically aligned with and bonded to the second bump electrode, whereas the plurality of substrate electrodes include no substrate electrode vertically aligned with and bonded to the first bump electrode.
  • bonding strength between stacked semiconductor chips can be increased. Therefore, it is possible to increase reliability of a stacked semiconductor device.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device an embodiment of the present invention
  • FIG. 2 is a cross-sectional view of a penetrating electrode TSV 1 ;
  • FIG. 3 is a cross-sectional view of a penetrating electrode TSV 2 ;
  • FIG. 4 is a cross-sectional view of a penetrating electrode TSV 3 ;
  • FIG. 5 is a cross-sectional view of a top-surface bump shown in FIG. 1 ;
  • FIG. 6 is a schematic top view of a layout of core chips CC 1 to CC 3 shown in FIG. 1 ;
  • FIG. 7 is a schematic top view of a layout of an interface chip IF
  • FIG. 8 is a layout chart of penetrating electrodes TSV and top-surface bumps FB disposed in regions A shown in FIG. 7 according to a first embodiment of the present invention
  • FIG. 9 is a cross-sectional view of FIG. 8 taken along line a-a (line C 1 ) shown in FIG. 8 ;
  • FIG. 10 is a cross-sectional view of FIG. 8 taken along line b-b (line C 2 ) shown in FIG. 8 ;
  • FIG. 11 is a diagram for explaining problems that could arise when displacement of substrate electrodes 91 occurs on an interposer IP in the case of the layout shown in FIG. 8 ;
  • FIG. 12 is a layout chart of the penetrating electrodes TSV and top-surface bumps FB disposed in the region A shown in FIG. 7 according to a second embodiment of the present invention.
  • FIG. 13 is a layout chart of the penetrating electrodes TSV and top-surface bumps FB disposed in the region A shown in FIG. 7 according to a third embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of FIG. 13 taken along line c-c (line C 1 ) shown in FIG. 13 ;
  • FIG. 15 is a cross-sectional view of FIG. 13 taken along line d-d (line C 2 ) shown in FIG. 13 ;
  • FIG. 16 is a layout chart of the penetrating electrodes TSV and top-surface bumps FB disposed in the region A shown in FIG. 7 according to a fourth embodiment of the present invention.
  • FIG. 17 is a layout chart indicative of an embodiment of the penetrating electrodes TSV that are arranged along curved lines.
  • FIG. 18 is a schematic diagram indicative of an embodiment of the connection relationship between power-supply penetrating electrodes TSVv 1 and TSVv 2 , signal penetrating electrodes TSVs, and internal circuits 20 .
  • the semiconductor device 10 of the embodiment has a structure in which the following components are stacked: four core chips CC 0 to CC 3 , which have the some functions and are produced with the use of the same production mask; one interface chip IF, which is produced with the use of a different production mask from that of the core chips CC 0 to CC 3 ; and one interposer IP.
  • the core chips CC 0 to CC 3 and the interface chip IF are semiconductor chips for which a silicon substrate is used, and are stacked by a face-clown method on the interposer IP.
  • the face-down method means a method of mounting semiconductor chips in such a way that principal surfaces on which electronic circuits such as transistors are formed face downward, or that the principal surfaces face the interposer IP's side.
  • the semiconductor device of the present invention is not limited to the above structure.
  • the semiconductor chips each may be stacked by a face-up method.
  • the face-up method means a method of mounting semiconductor chips in such a way that principal surfaces on which electronic circuits such as transistors are formed face upward, or that the principal surfaces face a side opposite to the interposer IP's side.
  • the semiconductor chips stacked by the face-down method, and the semiconductor chips stacked by the face-up method may exist together.
  • the core chips CCI to CC 3 and the interface chip IF other than the core chip CC 0 placed on the top layer are provided with large numbers of penetrating electrodes (through-substrate vias) TSV that pass through a substrate.
  • TSV may be called penetration electrodes, penetration vias, through electrode, or through-vias.
  • top-surface bumps FB are provided on the principal-surface sides of the chips
  • back-surface bumps BB are provided on the back-surface sides of the chips.
  • the reason why no penetrating electrode TSV is provided on the top-layer core chip CC 0 is because there is no need to form a bump electrode on the back-surface side of the core chip CC 0 as the chips are stacked by the face-down method. If no penetrating electrode TSV is provided on the top-layer core chip CC 0 as described above, the top-layer core chip CC 0 can be made thicker than the other core chips CC 1 to CC 3 to increase the mechanical strength of the core chip CC 0 .
  • a penetrating electrode TSV may be provided on the top-layer core chip CC 0 . In this case, all core chips CC 0 to CC 3 can be produced by the same process.
  • the core chips CC 0 to CC 3 are semiconductor chips made by removing the so-called front-end section, which serves as an interface with the outside, from circuit blocks contained in atypical SDRAM (Synchronous Dynamic Random Access Memory) that operates alone.
  • the core chips CC 0 to CC 3 are memory chips on which only circuit blocks belonging to the back-end section are integrated.
  • a parallel-to-serial conversion circuit which performs parallel-to-serial conversion of input/output data between a memory cell array and a data input/output terminal
  • a DLL (Delay Locked Loop) circuit which controls an input/output timing of data, and the like are provided.
  • the interface chip IF is a semiconductor chip on which only circuit blocks of the front-end section are integrated, among circuit blocks contained in a typical SDRAM that operates alone.
  • the interface chip IF functions as a common front-end section for the four core chips CC 0 to CC 3 . All accesses from the outside are conducted through the interface chip IF, and inputting and outputting of data are performed through the interface chip IF.
  • the interposer IP is a circuit board made of resin. On aback surface IPb thereof, a plurality of external terminals (solder balls) SB are formed.
  • the interposer IP ensures the mechanical strength of the semiconductor device 10 and functions as a redistribution substrate (or a rewiring substrate) to expand an electrode pitch. That is, substrate electrodes 91 that are formed on a top surface IPa of the interposer IP are led out to the back surface IPb via through-hole electrodes 92 ; rewiring layers 93 that are provided on the back surface IPb are designed to expand the pitch of the external terminals SB.
  • the areas of the top surface IPa of the interposer IP where no substrate electrode 91 is formed are covered with resist 90 a .
  • FIG. 1 shows only five external terminals SB. However, a large number of external terminals is actually provided.
  • the layout of the external terminals SB is the same as that of a SDRAM determined by the standard. Accordingly, an external controller can handle the external terminals SB as those of one SDRAM.
  • the gaps between the core chips CC 0 to CC 3 and interface chip IF stacked are filled with underfill 94 . In this manner, the mechanical strength is ensured.
  • the gap between the interposer IP and the interface chip IF is filled with NCP (Non-Conductive Paste) 95 .
  • the entire package is covered with mold resin 96 . In this manner, each chip is physically protected.
  • the penetrating electrodes TSV provided in the core chips CC 1 to CC 3 and interface chip IF are arranged at a minimum pitch P 0 that can be processed, or at a slightly wider pitch P 0 than the minimum pitch, in order to curb an increase in the chip size.
  • the value of the pitch P 0 is for example about 40 to 50 ⁇ m.
  • the substrate electrodes 91 provided on the interposer IP are arranged at a minimum pitch P 1 (>P 0 ) that is allowed according to a layout rule of the interposer IP, or at a slightly wider pitch P 1 (>P 0 ) than the minimum pitch.
  • the value of the pitch P 1 is for example about 75 to 150 ⁇ m.
  • FIG. 1 shows eight penetrating electrodes TSV, which are arranged in lines T 1 to T 8 in the core chips CC 1 to CC 3 and interface chip IF, as well as top-surface bumps FB, which are arranged in lines T 1 and T 8 to T 12 in the interface chip IF.
  • greater numbers of penetrating electrodes TSV and top-surface bumps FB are actually provided.
  • the top-surface bumps FB provided on the interface chip IF are bonded to the substrate electrodes 91 on the interposer IP.
  • some of the top-surface bumps FB provided on the interface chip IF are not bonded to the substrate electrodes 91 on the interposer IP.
  • the penetrating electrodes TSV provided on the core chips CC 1 to CC 3 are connected to the top-surface bumps FB and back-surface bumps BB that are provided at the same locations in planar view.
  • the penetrating electrodes of such a kind are represented by TSV 1 .
  • the penetrating electrodes TSV 1 of such a kind are shown in lines T 1 to T 8 .
  • the penetrating electrode TSV 1 is so provided as to pass through a silicon substrate 80 , an interlayer insulation film 81 , which is provided on a top surface of the silicon substrate 80 , and a passivation film 83 , which is provided on a back surface of the silicon substrate 80 .
  • the penetrating electrode TSV 1 is made of Cu (copper).
  • the top surface of the silicon substrate 80 serves as a device formation surface en which devices such as transistors are formed.
  • insulation rings 82 are provided to insulate the penetrating electrode TSV 1 from a transistor region.
  • two insulation rings 82 are provided to reduce capacitance between the penetrating electrode TSV 1 and the silicon substrate 80 .
  • one insulation ring 82 instead of two, may be provided.
  • a back-surface bump BB An end portion of the penetrating electrode TSV 1 that is closer to the back surface of the silicon substrate 80 is covered with a back-surface bump BB.
  • the back-surface bumps BB are in contact with the top-surface bumps FB provided on upper-layer core chips CC 0 to CC 2 , respectively.
  • the back-surface bumps BB are in contact with the top-surface bumps FB provided on the core chip CC 3 .
  • the back-surface bumps BB are made of SnAg solder, which covers the surfaces of the penetrating electrodes TSV 1 made of Cu (copper).
  • the top-surface bump FB is connected to an end portion of the penetrating electrode TSV 1 via pads M 1 to M 4 , which are provided in wiring layers L 1 to L 4 , and a plurality of through-hole electrodes TH 1 to TH 3 , which connect the pads.
  • the op-surface bumps FB are in contact with the back-surface bumps BB provided on the lower-layer core chips CC 2 and CC 3 and the interface chips IF, respectively.
  • the top-surface bumps FB are in contact with the substrate electrodes 91 on the interposer IP.
  • the top-surface bumps FB include a pillar portion 86 that is made of Cu (copper).
  • a surface of the pillar portion 86 includes a structure in which layers of Ni (nickel) and Au (gold) are stacked.
  • the diameter of the top-surface bumps FB and back-surface bumps BB is about 20 ⁇ m.
  • the top-surface bumps FB and back-surface bumps BB that are provided at the same locations in planar view are being short-circuited via the penetrating electrodes TSV 1 .
  • the pillar portion 86 of a top-surface bump FB is so provided as to pass through a passivation film 84 .
  • a top surface of the passivation film 84 except a region where the top-surface bump FB is formed is covered with a polyimide film 85 .
  • the connection to internal circuits not shown in the diagram is realized via internal wires (not shown), which are led out from the pads M 1 to M 3 provided in the wiring layers L 1 to L 3 .
  • the penetrating electrodes TSV 1 are connected to the top-surface bumps FB and back-surface bumps BB that are provided at the same locations in planar view. Accordingly, input signals (command signals, address signals, and other signals) that are supplied from the interface chip IF via the penetrating electrodes TSV 1 are input into the core chips CC 0 to CC 3 in common. Output signals (such as data) that are supplied from the core chips CCC to CC 3 via the penetrating electrodes TSV 1 are subjected to a Wired-OR operation before being input into the interface chip IF.
  • FIG. 1 shows the penetrating electrodes TSV 1 provided in lines T 1 and T 8 of the interface chip IF.
  • the penetrating electrodes TSV 1 provided on the interface chip IF are used mainly for supplying power supply potential VDD or VSS.
  • the penetrating electrodes TSV provided on the interface chip IF are connected to the back-surface bumps BB that are provided at the same locations in planar view, but not connected to the top-surface bumps FB that are provided at the same locations in planar view.
  • the penetrating electrodes of such a kind are represented by TSV 2 .
  • the penetrating electrodes TSV 2 provided on the interface chip IF are shown in lines T 2 to T 7 .
  • the penetrating electrode TSV 2 is different from the penetrating electrode TSV 1 shown in FIG. 2 in that a through-hole electrode TH 2 , which is designed to connect the pads M 2 and M 3 placed at the same plane position, has been removed. Therefore, the top-surface bump FB and back-surface bump BB that are placed at the same plane position are not short-circuited.
  • the penetrating electrodes TSV 2 provided on the interface chip IF are used mainly for transmitting or receiving signals. That is, signals output from the internal circuits (not shown) in the interface chip IF are supplied to the pad M 1 or M 2 , and are supplied to the core chips CC 0 to CC 3 via the back-surface bumps BB.
  • Signals output from the core chips CC 0 to CC 3 are supplied to the pad M 1 or M 2 via the back-surface bumps BB, and are input into the internal circuits (not shown) in the interface chip IF.
  • the penetrating electrodes TSV 2 are electrodes that are bonded to the top-surface bumps FB provided on the core chip CC 3 . Therefore, the array pitch thereof is so designed as to be P 0 .
  • the top-surface bumps FB of the penetrating electrodes TSV 2 shown in lines T 2 to T 7 are not bonded to the substrate electrodes 91 on the interposer IP. In such a case, there is no need to provide the top-surface bumps FB; as in the case of a penetrating electrode TSV 3 shown in FIG. 4 , the top-surface bumps FB may be removed.
  • penetrating electrodes TSV 2 are used in the core chips CC 1 to CC 3 .
  • the penetrating electrodes TSV 2 provided on the core chips CC 1 to CC 3 are used to sequentially transfer predetermined information to the internal circuits (not shown) provided on each of the core chips CC 0 to CC 3 , and to input unique information.
  • the information includes chip address information, defective chip information, and the like.
  • top-surface bumps FBa on which penetrating electrodes TSV are not provided at the same plane positions are provided, too.
  • the top-surface bumps FBa provided on the interface chip IF are shown in Lines T 9 to T 12 .
  • top-surface bump FBa provided on the interface chip IF is connected to the pads M 4 and M 3 .
  • the pads M 2 and M 1 , the penetrating electrodes TSV, and the back-surface bump BB are not provided.
  • the pads M 4 and M 3 are connected to logic circuits and other circuits in the interface chip IF, which are not shown in the diagram.
  • the top surface bump FBa is an electrode bonded to a substrate electrode 91 on the interposer IP. Therefore, the array pitch thereof is so designed as to be P 1 .
  • the core chip CC 0 is placed on a stage of a flip chip bonder in a face-up manner. The position thereof is recognized with the help of an alignment mark put on the surface of the chip. Then, a flip chip bonding tool is used to pick up the principal surface of the core chip CC 1 , or the surface on which the top-surface bumps FB are formed. The position of the core chip CC 1 that is picked up is recognized with the help of an alignment mark put on the back surface thereof.
  • the core chip CC 1 is stacked on the core chip CC 0 in a face-up manner in such a way that the top-surface bumps FB of the core chip CC 0 are accurately placed on the back-surface bumps BB of the core chip CC 1 .
  • the position of the core chip CC 1 is recognized with the help of an alignment mark put on the surface of the chip.
  • a flip chip bonding tool is used to pick up the core chip CC 2 .
  • the same procedure is used to stack the core chip CC 2 on the core chip CC 1 in a face-up manner.
  • the core chip CC 3 and the interface chip IF are stacked in that order.
  • the underfill 94 is injected from the sides. Then, pressurization baking or the like is performed to cure the underfill 94 .
  • the substrate electrodes 91 are formed on the top surface IPa of the interposer IP.
  • stud bump made of gold (Au) be used as the substrate electrodes 91 .
  • the interposer IP is placed, and the NCP (Non-Conductive Paste) 95 is applied to the top surface IPa on which the substrate electrodes 91 are formed.
  • NCP Non-Conductive Paste
  • a process of stacking the core chips CC 0 to 003 and the interface chip IF is performed in the state that the temperature of the flip chip bonding tool is set to 300 degrees Celsius, for example.
  • the temperature is a temperature necessary to bond the top-surface bumps FB to the back-surface bumps BB.
  • a decrease in the temperature leads to a decline in bonding strength.
  • it is desirable that the semiconductor chip that is picked up be evenly heated at about 300 degrees Celsius.
  • the periphery of the chip actually tends to decrease in temperature.
  • the formation density of high thermal-conductivity penetrating electrodes TSV is low at the periphery of the chip.
  • the semiconductor device 10 of the present embodiment is able to prevent the occurrence of such a bonding failure in an effective manner. While the details will be described later, the reason is that dummy penetrating electrodes are disposed in an area where the formation density of the penetrating electrodes TSV is low, thereby increasing the bonding strength.
  • the planar configuration of the core chips CC 0 to CC 3 and the interface chip IF will be described in more detail.
  • the core chips CC 1 to CC 3 each have eight memory banks BANK 0 to BANK 7 .
  • the even-numbered memory banks BANK 0 , 2 , 4 , and 6 are disposed in an X-direction along one side L 11 in a Y-direction of each of the core chips CC 1 to CC 3 .
  • the odd-numbered memory banks BANK 1 , 3 , 5 , and 7 are disposed in the X-direction along the other side L 12 in the Y-direction of each of the core chips CC 1 to CC 3 .
  • row decoders XDEC are disposed to perform row access.
  • column decoders YDEC are disposed to perform column access.
  • peripheral circuits PEC In a central portion of the chip in the Y-direction, called peripheral circuits PEC are disposed.
  • peripheral circuits PEC a logic circuit, a power supply circuit, an input/output circuit, and the like are provided.
  • regions S 1 between the peripheral circuits PEC and the column decoders YDEC a large number of penetrating electrodes TSV are disposed.
  • the penetrating electrodes disposed in the regions S 1 are mainly made up of penetrating electrodes TSVv for power supply, and penetrating electrodes TSVs for signals.
  • penetrating electrodes TSV 1 having the configuration shown in FIG. 2 are used.
  • penetrating electrodes TSV 1 having the configuration shown in FIG. 2 or penetrating electrodes TSV 2 having the configuration shown in FIG. 3 are used. While the details will be described later, dummy penetrating electrodes TSVd, too, are provided in the area according to the present embodiment. The dummy penetrating electrodes TSVd are disposed near the sides L 13 and L 14 in the X-direction of the chip.
  • penetrating electrodes TSVp for support, and alignment marks FCM are provided.
  • the support penetrating electrodes TSVp are provided to prevent the gaps between the chips from becoming narrower due to warping of the chips.
  • penetrating electrodes TSV 1 having the configuration shown in FIG. 2 are used.
  • the alignment marks FCM are made up of pads M 4 which are provided on the top-layer wiring layers L 4 for the principal surfaces' sides of the chips, and the alignment marks FCM are made up of the back-surface bumps BB for the back surfaces' sides of the chips.
  • the back-surface bumps BB that constitute the alignment marks FCM are formed integrally with the penetrating electrodes TSV 3 shown in FIG. 4 .
  • the top-layer core chip CC 0 basically has the same configuration as the core chips CC 1 to CC 3 shown in FIG. 6 .
  • no penetrating electrode TSV is provided on the core chip CC 0 . Therefore, no back-surface bump BB is provided on the core chip CC 0 .
  • the layout of the top-surface bumps FB is the same as the layout shown in FIG. 6 .
  • peripheral circuits PEIF in a central portion in the Y-direction of the interface chip IF, so-called peripheral circuits PEIF are disposed.
  • peripheral circuits PEIF a logic circuit, a power supply circuit, a DLL circuit, and the like are provided.
  • regions S 3 on both sides in the Y-direction of the peripheral circuits PEIF a plurality of penetrating electrodes TSV are so disposed that the peripheral circuits PEIF are sandwiched therebetween.
  • the layout of the penetrating electrodes TSV disposed in the regions S 3 is the same as the layout of the penetrating electrodes TSV disposed in the regions S 1 of the core chips CC 1 to CC 3 .
  • the penetrating electrodes TSV disposed in the regions S 3 are mainly made up of penetrating electrodes TSVv for power supply, and penetrating electrodes TSVs for signals.
  • penetrating electrodes TSVv penetrating electrodes TSV 1 having the configuration shown in FIG. 2 are used.
  • penetrating electrodes TSV 2 having the configuration shown in FIG. 3 are used. While the details will be described later, dummy penetrating electrodes TSVd, too, are provided in the area according to the present embodiment.
  • the dummy penetrating electrodes TSVd are disposed near the sides L 23 and L 24 in the X-direction of the chip.
  • top-surface bumps FBa are so provided as to be connected to the interposer IP.
  • the top-surface bumps FBa provided in the regions S 4 have the configuration shown in FIG. 5 .
  • the pitch of the top-surface bumps FBa provided in the regions S 4 is pitch P 1 that is allowed according to the wiring rule of the interposer IP, and is larger than the array pitch P 0 of the penetrating electrodes TSV.
  • test circuits BIST along the sides L 21 and L 22 of the chip, test circuits BIST, anti-fuse elements AF, power supply circuits GEN, and other circuits are disposed.
  • alignment marks FCM are provided in diagonal regions of the chip.
  • the Y-direction size of the interface chip IF is smaller than the Y-direction size of the core chips CC 0 to CC 3 .
  • the interface chip IF is unlikely to be warped. Therefore, unlike the core chips CC 1 to CC 3 , the support penetrating electrodes TSV are not provided along the sides L 21 and L 22 of the chip.
  • the region S 3 contains penetrating electrodes TSVv 1 and TSVv 2 for power supply, penetrating electrodes TSVs for signals, dummy penetrating electrodes TSVd, and penetrating electrodes TSVv 1 a and TSVv 2 a for power supply assistance.
  • FIG. 8 is a top view seen from the principal surface's side of the interface chip IF. Therefore, the top-surface bumps FB are actually confirmed in the region S 3 . However, for ease of explanation, the top-surface bumps FB are regarded as penetrating electrodes in the following description. Turning to FIG.
  • the internal circuit 20 is powered by power supply potential VDD, which is supplied via a power supply line V 1 , and power supply potential VSS, which is supplied via a power supply line V 2 , to operate and a signal is input and output via a signal line S.
  • VDD power supply potential
  • VSS power supply potential
  • the penetrating electrodes TSVv 1 and TSVv 2 are connected to the power supply lines V 1 and V 2 , respectively, and the penetrating electrode TSVs is connected to the signal line S.
  • the upper-layer core chips CC 1 and CC 2 is connected to the signal line S.
  • the top-surface bumps FBa formed in the region S 4 have the configuration shown in FIG. 5 .
  • no penetrating electrode TSV is provided.
  • the distance LF between the regions S 3 and S 4 in the Y-direction is determined based on the size and precision of a flip chip bonding tool used for flip-chip stacking. The reason is that, at the time of flip-chip stacking, the flip chip bonding tool needs to stick fast to an area where no top-surface bump FB is provided. In one example, the distance LF is about 200 to 500 ⁇ m.
  • the distance between lines a-a and b-b in the Y-direction is so designed as to be ⁇ times as large as the pitch P 0 .
  • ⁇ is ⁇ 3/2
  • penetrating electrodes TSV are laid out at apexes of an equilateral triangle. Therefore, closest packing is possible.
  • the pitch of the penetrating electrodes TSV on line a-a and the penetrating electrodes TSV on line b-b is P 0 .
  • the power-supply penetrating electrodes TSVv 1 and TSVv 2 are penetrating electrodes TSV 1 having the configuration shown in FIG. 2 .
  • FIG. 9 which is a cross-sectional view
  • the power-supply penetrating electrodes TSVv 1 and TSVv 2 are bonded to the substrate electrodes 91 on the interposer IP via the top-surface bumps FB.
  • the power-supply penetrating electrodes TSVv 1 and TSVv 2 are bonded to the corresponding top-surface bumps FB of the upper-layer core chips CC 3 via the back-surface bumps BB.
  • the penetrating electrodes TSVv 1 are penetrating electrodes for supplying high-level power supply potential VDD, and are connected to power supply lines that supply the high-level power supply potential VDD to internal circuits such as peripheral circuits PEIF.
  • the penetrating electrodes TSVv 2 are penetrating electrodes for supplying low-level power supply potential VSS, and are connected to power supply lines that supply the low-level power supply potential VSS to internal circuits such as peripheral circuits PEIF.
  • the penetrating electrodes TSVv 1 and TSVv 2 are bonded to the substrate electrodes 91 on the interposer IP via the top-surface bumps FB. Therefore, the penetrating electrodes TSVv 1 and TSVv 2 are arranged with a pitch of P 1 .
  • the signal penetrating electrodes TSVs are penetrating electrodes TSV 2 having the configuration shown in FIG. 3 . As shown in FIGS. 9 and 10 , the signal penetrating electrodes TSVs are not bonded directly to the substrate electrodes 91 on the interposer IP. The signal penetrating electrodes TSVs are bonded to the corresponding top-surface bumps FB of the upper-layer core chip CC 3 via the back-surface bumps BB. In this manner, the signal penetrating electrodes TSVs are penetrating electrodes for connecting the chips to each other. Therefore, the signal penetrating electrodes TSVs are disposed with a pitch of P 0 .
  • the dummy penetrating electrodes TSVd are penetrating electrodes TSV 2 having the configuration shown in FIG. 3 . As shown in FIGS. 9 and 10 , the dummy penetrating electrodes TSVd are not bonded directly to the substrate electrodes 91 on the interposer IP. The dummy penetrating electrodes TSVd are bonded to the corresponding top-surface bumps FB of the upper-layer core chip CC 3 via the back-surface bumps BB. The dummy penetrating electrodes TSVd are not connected to any internal circuit in the interface chip IF, and are in the state of floating. As shown in FIG.
  • the dummy penetrating electrodes TSVd provided on the core chips CC 1 to CC 3 are penetrating electrodes TSV 1 having the configuration shown in FIG. 2 .
  • the dummy penetrating electrodes TSVd provided on the core chips CC 1 to CC 3 are not connected to any internal circuit in the core chips CC 1 to CC 3 , and are in the state of floating.
  • the penetrating electrodes TSV 2 having the configuration shown in FIG. 3 may be used.
  • the penetrating electrodes TSV disposed on coordinates X 1 to X 5 may be referred to as first to fifth penetrating electrode respectively.
  • the penetrating electrodes TSV provided on the upper-layer core chip CC 3 , the penetrating electrodes TSV that are so disposed as to overlap with the penetrating electrodes TSV disposed on coordinates X 1 to X 4 in planar view may be referred to as tenth to thirteenth penetrating electrodes, respectively.
  • the power supply assistance penetrating electrodes TSVv 1 a and TSVv 2 a are penetrating electrodes TSV 2 having the configuration shown in FIG. 3 .
  • FIG. 10 which is a cross-sectional view
  • the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are not bonded to the substrate electrodes 91 on the interposer IP via the top-surface bumps FB.
  • the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are connected to the power-supply penetrating electrodes TSVv 1 and TSVv 2 , respectively.
  • the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a may not be provided. However, if the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are provided, it is possible to make power-supply main lines thicker in the interface chip IF, thereby lowering the resistance of the power-supply lines. Moreover, the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a function as bypass routes the power-supply lines between the chips, making it possible to increase reliability.
  • one power supply-assistance penetrating electrode TSVv 1 a and one power supply-assistance penetrating electrode TSVv 2 a are provided with a pitch of P 1 .
  • the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are disposed next to the power-supply penetrating electrodes TSVv 1 and TSVv 2 , respectively, which are provided on line a-a.
  • Three dummy penetrating electrodes TSVd are provided on line b-b in such a way that the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are sandwiched therebetween.
  • the penetrating electrodes TSV disposed on coordinates X 6 to X 9 may be referred to as sixth to ninth penetrating electrodes, respectively.
  • the power-supply penetrating electrodes TSVv 1 and TSVv 2 provided on line a-a are bonded to the substrate electrodes 91 on the interposer IP. Therefore, the array pitch thereof is P 1 .
  • the dummy penetrating electrodes TSVd are so provided that the above electrodes are sandwiched therebetween. Therefore, the array pitch of the penetrating electrodes TSV on line a-a is P 0 even in the vicinity of the side L 23 .
  • the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are provided, and the dummy penetrating electrodes TSVd are so provided that the above electrodes are sandwiched therebetween. Therefore, the array pitch of the penetrating electrodes TSV on line b-b is P 0 even in the vicinity of the side L 23 .
  • the above configuration increases the formation density of the penetrating electrodes TSV in the vicinity of the side L 23 , leading to an increase in thermal conductivity at the time of flip-chip stacking.
  • the penetrating electrodes TSV are made of metal (e.g. copper), which is higher in thermal conductivity than silicon that is used to make the semiconductor chips.
  • metal e.g. copper
  • a connection failure can occur between the upper and lower chips due to warping of the chips.
  • the formation density of the penetrating electrodes TSV has been increased, resulting in an increase in bonding strength between the chips. Therefore, even if the chips become warped to a certain extent, the possibility is low that the bond sections between the chips would be broken.
  • connection failure that could occur at the peripheries of the chips is more likely to occur in areas closer to the sides of the chips.
  • the dummy penetrating electrodes TSVd closest to the sides of the chips are in the state of floating. Therefore, even if a connection failure occurs on the dummy penetrating electrodes TSVd, the dummy penetrating electrodes TSVd do not have an influence on the internal circuits. Even if the dummy penetrating electrodes TSVd come in contact with other unintended electrodes and the like, the dummy penetrating electrodes TSVd do not have an influence on the internal circuits.
  • regions A′ that are positioned close to the side L 23 or L 24 have a similar configuration. While the above description focuses on the interface chip IF, the same layout as that of the penetrating electrodes TSV that are so provided as to overlap with the regions A and A′ in planar view is used in the core chips CC 1 to CC 3 . Accordingly, an improvement in thermal conductivity at the time of flip-chip stacking, and an improvement in bonding strength against warping of the chips can be achieved not only between the interface chip IF and the core chip CC 3 , but also between the core chips CC 0 to CC 3 . Therefore, the reliability of the product can be improved.
  • the dummy penetrating electrodes TSVd and the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are disposed in a free space where the penetrating electrodes TSV are originally not provided, thereby avoiding an increase in the chip size.
  • FIG. 11 shows the situation where the distance between a substrate electrode 91 v 1 , which should be bonded to the penetrating electrode TSVv 1 , and a substrate electrode 91 v 2 , which should be bonded to the penetrating electrode TSVv 2 , is shorter than a design value. If the substrate electrodes 91 remain displaced as described above during the process of stacking the chips, as shown in FIG.
  • the dummy penetrating electrode TSVd at coordinate X 5 between the power-supply penetrating electrodes TSVv 1 and TSVv 2 is removed.
  • the configuration of the other components is the same as the layout shown in FIG. 8 . According to the configuration, even if displacement of the substrate electrodes 91 occurs on the interposer IP, the power supply is not short-circuited.
  • the configuration of the other components is the same as the layout shown in FIG. 8 .
  • FIGS. 14 and 15 which are cross-sectional views, even on the core chips CC 1 to CC 3 , the penetrating electrodes TSV at coordinates X 5 and X 0 are removed.
  • the top-surface bump FB 1 to back-surface bump BB 8 shown in FIG. 14 may be referred to as “first bump” to “eighth bump”, respectively.
  • the power supply is short-circuited basically when the distance between the substrate electrodes 91 v 1 and 91 v 2 is narrower than the diameter of the dummy penetrating electrode TSVd.
  • the power supply can be short-circuited even when the distance is wider than the diameter of the dummy penetrating electrode TSVd.
  • the penetrating electrodes TSVv 1 and TSVv 2 can be short-circuited via the power supply-assistance penetrating electrode TSVv 2 a shown in FIG. 12 and the dummy penetrating electrode TSVd adjacent to the penetrating electrode TSVv 2 a .
  • such a possibility is eliminated. Therefore, it is possible to increase the reliability of the product.
  • the distance between the power-supply penetrating electrodes TSVv 1 and TSVv 2 is designed in advance so as to be wider than pitch P 1 . More specifically, while the distance between the power-supply penetrating electrodes TSVv 1 and TSVv 2 is pitch P 1 according to the first to third embodiments, the distance is increased to P 1 +P 0 according to the present embodiment. Therefore, between the power-supply penetrating electrodes TSVv 1 and TSVv 2 , two dummy penetrating electrodes TSVd can be placed. Therefore, even if the substrate electrodes 91 are displaced or deformed, the power supply is not short-circuited. Moreover, there is no need to remove some of the dummy penetrating electrodes TSVd. Therefore, the formation density of the penetrating electrodes TSV can be increased to the same level as in the first embodiment.
  • the present invention is not limited to the above type. Accordingly, the type and number of semiconductor chips stacked are not specifically limited. Moreover, the technical concept of the present invention is realized not only in the situation where a plurality of semiconductor chips are stacked, but also in a single semiconductor chip that has not yet been stacked. The reason is that even a semiconductor chip that has not yet been stacked can achieve the above-described advantageous effects in the subsequent stacking process. Therefore, the scope of the present invention is not limited to the stacked semiconductor device.
  • the dummy penetrating electrodes TSVd are provided adjacent to the power-supply penetrating electrodes TSVv 1 and TSVv 2 .
  • the dummy penetrating electrodes TSVd may also be provided adjacent to the signal penetrating electrodes TSVs.
  • the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a are provided adjacent to the power-supply penetrating electrodes TSVv 1 and TSVv 2 .
  • no power supply-assistance penetrating electrodes may be provided.
  • dummy penetrating electrodes TSVd may be provided instead of the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a of the first to fourth embodiments.
  • the penetrating electrodes TSV arranged on lines a-a to d-d work as dummy penetrating electrodes TSVd.
  • the power supply-assistance penetrating electrodes TSVv 1 a and TSVv 2 a may be disposed.
  • lines a-a to d-d shown in each of the above-described embodiments are not necessarily perfect straight lines. The lines may be curved as in line e-e or f-f shown in FIG. 17 .
US13/780,979 2012-03-05 2013-02-28 Semiconductor device having penetrating electrodes each penetrating through substrate Active US9136204B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012047803A JP2013183120A (ja) 2012-03-05 2012-03-05 半導体装置
JP2012-047803 2012-03-05

Publications (2)

Publication Number Publication Date
US20130228898A1 US20130228898A1 (en) 2013-09-05
US9136204B2 true US9136204B2 (en) 2015-09-15

Family

ID=49042365

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/780,979 Active US9136204B2 (en) 2012-03-05 2013-02-28 Semiconductor device having penetrating electrodes each penetrating through substrate

Country Status (2)

Country Link
US (1) US9136204B2 (ja)
JP (1) JP2013183120A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10211176B2 (en) 2015-12-21 2019-02-19 Samsung Electronics Co., Ltd. Semiconductor package
US10431648B2 (en) 2014-05-02 2019-10-01 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US10679969B2 (en) * 2017-02-28 2020-06-09 Fujitsu Limited Electronic circuit device and method for manufacturing electronic circuit device

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101690487B1 (ko) * 2010-11-08 2016-12-28 삼성전자주식회사 반도체 장치 및 제조 방법
JP2012209497A (ja) * 2011-03-30 2012-10-25 Elpida Memory Inc 半導体装置
US8907494B2 (en) * 2013-03-14 2014-12-09 International Business Machines Corporation Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structures
US9196549B2 (en) * 2013-12-04 2015-11-24 United Microelectronics Corp. Method for generating die identification by measuring whether circuit is established in a package structure
EP2889901B1 (en) * 2013-12-27 2021-02-03 ams AG Semiconductor device with through-substrate via and corresponding method
US9355997B2 (en) 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9741649B2 (en) 2014-06-04 2017-08-22 Invensas Corporation Integrated interposer solutions for 2D and 3D IC packaging
US9412806B2 (en) 2014-06-13 2016-08-09 Invensas Corporation Making multilayer 3D capacitors using arrays of upstanding rods or ridges
US9252127B1 (en) 2014-07-10 2016-02-02 Invensas Corporation Microelectronic assemblies with integrated circuits and interposers with cavities, and methods of manufacture
KR102188644B1 (ko) * 2014-11-13 2020-12-08 에스케이하이닉스 주식회사 확장된 대역폭을 갖는 반도체 패키지
JP2016131245A (ja) * 2015-01-13 2016-07-21 デクセリアルズ株式会社 多層基板
US9478504B1 (en) 2015-06-19 2016-10-25 Invensas Corporation Microelectronic assemblies with cavities, and methods of fabrication
JP6464108B2 (ja) * 2016-02-25 2019-02-06 株式会社豊田中央研究所 半導体装置
KR102556517B1 (ko) * 2018-08-28 2023-07-18 에스케이하이닉스 주식회사 브리지 다이를 포함하는 스택 패키지
KR20210005340A (ko) * 2019-07-03 2021-01-14 삼성전자주식회사 반도체 패키지
JP7272587B2 (ja) * 2019-10-04 2023-05-12 本田技研工業株式会社 半導体装置
CN112687614A (zh) 2019-10-17 2021-04-20 美光科技公司 包含多个装置堆叠的微电子装置组合件和封装体以及相关方法
US11456284B2 (en) * 2019-10-17 2022-09-27 Micron Technology, Inc. Microelectronic device assemblies and packages and related methods
CN112687615A (zh) 2019-10-17 2021-04-20 美光科技公司 微电子装置组合件、封装体和相关方法
KR20210075662A (ko) * 2019-12-13 2021-06-23 삼성전자주식회사 반도체 패키지
US10966338B1 (en) * 2020-03-11 2021-03-30 Peter C. Salmon Densely packed electronic systems
US11393807B2 (en) 2020-03-11 2022-07-19 Peter C. Salmon Densely packed electronic systems
US11546991B2 (en) 2020-03-11 2023-01-03 Peter C. Salmon Densely packed electronic systems
KR20220006932A (ko) * 2020-07-09 2022-01-18 삼성전자주식회사 인터포저를 포함하는 반도체 패키지 및 반도체 패키지의 제조 방법
US11523543B1 (en) 2022-02-25 2022-12-06 Peter C. Salmon Water cooled server
US11445640B1 (en) 2022-02-25 2022-09-13 Peter C. Salmon Water cooled server

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005136187A (ja) 2003-10-30 2005-05-26 Japan Science & Technology Agency 半導体装置及びその製造方法
JP2006049417A (ja) 2004-08-02 2006-02-16 Seiko Epson Corp 半導体装置の実装装置及び実装方法、並びに半導体装置、電子機器
US7115972B2 (en) * 2002-10-28 2006-10-03 Sharp Kabushiki Kaisha Semiconductor device and chip-stack semiconductor device
US20100052111A1 (en) * 2008-08-26 2010-03-04 Kabushiki Kaisha Toshiba Stacked-chip device
US20100171226A1 (en) * 2008-12-29 2010-07-08 Texas Instruments, Inc. Ic having tsv arrays with reduced tsv induced stress
US20110140126A1 (en) * 2009-12-10 2011-06-16 Stephen Joseph Gaul Heat conduction for chip stacks and 3-d circuits
US8269350B1 (en) * 2011-05-31 2012-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing the switching noise on substrate with high grounding resistance
US20130049220A1 (en) * 2011-08-31 2013-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Through Silicon Via Keep Out Zone Formation Method and System

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002076247A (ja) * 2000-08-25 2002-03-15 Matsushita Electric Ind Co Ltd 積層型半導体装置およびその製造方法
JP5157427B2 (ja) * 2007-12-27 2013-03-06 株式会社ニコン 積層型半導体装置、半導体基板及び積層型半導体装置の製造方法。
JP2011082450A (ja) * 2009-10-09 2011-04-21 Elpida Memory Inc 半導体装置及びこれを備える情報処理システム

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115972B2 (en) * 2002-10-28 2006-10-03 Sharp Kabushiki Kaisha Semiconductor device and chip-stack semiconductor device
JP2005136187A (ja) 2003-10-30 2005-05-26 Japan Science & Technology Agency 半導体装置及びその製造方法
US7944058B2 (en) 2003-10-30 2011-05-17 Oki Semiconductor Co., Ltd. Semiconductor device and process for fabricating the same
US20110201178A1 (en) 2003-10-30 2011-08-18 Oki Semiconductor Co., Ltd. Semiconductor device and process for fabricating the same
JP2006049417A (ja) 2004-08-02 2006-02-16 Seiko Epson Corp 半導体装置の実装装置及び実装方法、並びに半導体装置、電子機器
US20100052111A1 (en) * 2008-08-26 2010-03-04 Kabushiki Kaisha Toshiba Stacked-chip device
US20100171226A1 (en) * 2008-12-29 2010-07-08 Texas Instruments, Inc. Ic having tsv arrays with reduced tsv induced stress
US20110140126A1 (en) * 2009-12-10 2011-06-16 Stephen Joseph Gaul Heat conduction for chip stacks and 3-d circuits
US8269350B1 (en) * 2011-05-31 2012-09-18 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing the switching noise on substrate with high grounding resistance
US20130049220A1 (en) * 2011-08-31 2013-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Through Silicon Via Keep Out Zone Formation Method and System

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10431648B2 (en) 2014-05-02 2019-10-01 Invensas Corporation Making electrical components in handle wafers of integrated circuit packages
US10211176B2 (en) 2015-12-21 2019-02-19 Samsung Electronics Co., Ltd. Semiconductor package
US10943881B2 (en) 2015-12-21 2021-03-09 Samsung Electronics Co., Ltd. Semiconductor package
US11769746B2 (en) 2015-12-21 2023-09-26 Samsung Electronics Co., Ltd. Semiconductor package
US10679969B2 (en) * 2017-02-28 2020-06-09 Fujitsu Limited Electronic circuit device and method for manufacturing electronic circuit device

Also Published As

Publication number Publication date
US20130228898A1 (en) 2013-09-05
JP2013183120A (ja) 2013-09-12

Similar Documents

Publication Publication Date Title
US9136204B2 (en) Semiconductor device having penetrating electrodes each penetrating through substrate
US9252091B2 (en) Semiconductor device having penetrating electrodes each penetrating through semiconductor chip
US11193953B2 (en) 3D chip testing through micro-C4 interface
US10748870B2 (en) Tri-layer COWOS structure
JP5265768B2 (ja) シリコン貫通ビアのブリッジする相互接続
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
US9018969B2 (en) Semiconductor device with aligned bumps
US20140131854A1 (en) Multi-chip module connection by way of bridging blocks
US9935081B2 (en) Hybrid interconnect for chip stacking
CN104517930A (zh) 半导体封装
US10083937B2 (en) Semiconductor devices and packages and methods of forming semiconductor device packages
JP2010278334A (ja) 半導体装置
US20130105939A1 (en) Semiconductor device
US9411015B2 (en) Semiconductor device having penetrating electrodes each penetrating through substrate
US20230085054A1 (en) Semiconductor device
US8765526B2 (en) Method of manufacturing semiconductor device including plural semiconductor chips stacked together
TWI708293B (zh) 包括升高襯墊上的貫穿模球連接體的半導體封裝及其製造方法
JP2016004860A (ja) 半導体装置
US20230230902A1 (en) Semiconductor package structure and manufacturing method thereof
TWM537303U (zh) ３ｄ多晶片模組封裝結構（二）
TW201639107A (zh) 半導體裝置
CN112397475A (zh) 具有微细间距硅穿孔封装的扇出型封装晶片结构及单元
US20230378132A1 (en) Semiconductor package and method of manufacturing the same
US20210082854A1 (en) Semiconductor device and method for manufacturing semiconductor device
TW202347675A (zh) 電子封裝件及其製法

Legal Events

Date Code Title Description
AS Assignment

Owner name: ELPIDA MEMORY, INC., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IDE, AKIRA;REEL/FRAME:029903/0505

Effective date: 20130218

AS Assignment

Owner name: ELPIDA MEMORY INC., JAPAN

Free format text: SECURITY AGREEMENT;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:032414/0261

Effective date: 20130726

AS Assignment

Owner name: PS4 LUXCO S.A.R.L., LUXEMBOURG

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ELPIDA MEMORY, INC.;REEL/FRAME:032901/0196

Effective date: 20130726

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: PS5 LUXCO S.A.R.L., LUXEMBOURG

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PS4 LUXCO S.A.R.L.;REEL/FRAME:039818/0506

Effective date: 20130829

Owner name: LONGITUDE SEMICONDUCTOR S.A.R.L., LUXEMBOURG

Free format text: CHANGE OF NAME;ASSIGNOR:PS5 LUXCO S.A.R.L.;REEL/FRAME:039793/0880

Effective date: 20131112

AS Assignment

Owner name: LONGITUDE LICENSING LIMITED, IRELAND

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LONGITUDE SEMICONDUCTOR S.A.R.L.;REEL/FRAME:046863/0001

Effective date: 20180731

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8