US8519756B2 - PLL dual edge lock detector - Google Patents

PLL dual edge lock detector Download PDF

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US8519756B2
US8519756B2 US13/272,560 US201113272560A US8519756B2 US 8519756 B2 US8519756 B2 US 8519756B2 US 201113272560 A US201113272560 A US 201113272560A US 8519756 B2 US8519756 B2 US 8519756B2
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signal
circuit
reference signal
level
output
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US20120098570A1 (en
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Xiaoyue Wang
Shafiq M. Jamal
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Marvell International Ltd
Cavium International
Marvell Asia Pte Ltd
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Marvell World Trade Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation

Definitions

  • the present disclosure relates to phase locked loop (PLL) circuits and in particular to circuitry for detecting when the output of the PLL has locked onto a reference signal.
  • PLL phase locked loop
  • PPLs Phase locked loops
  • wireless products PLLs are typically used to generate high speed system clocks.
  • a lock detector circuit is typically provided to detect when the frequency of the PLL output signal has settled. The lock detector can generate a lock signal that can be used by the system for clock gating.
  • the main blocks of a PLL circuit 100 typically include a phase frequency detector 112 , a charge pump 114 , a low-pass filter 116 , a voltage controlled oscillator (VCO) 118 , and a feedback counter 120 .
  • the phase frequency detector 112 detects the difference in phase and frequency between a reference signal (clock) F ref and a feedback signal (clock) F fb , and generates an “up” (U) or a “down” (D) control signal based on whether the frequency of the feedback signal F fb (feedback frequency) is lagging or leading the frequency of the reference signal F ref (reference frequency).
  • the phase frequency detector 112 outputs these “up” and “down” signals to the charge pump 114 . If the charge pump receives an “up” signal, current is driven into the low-pass filter 116 . Conversely, if the charge pump 114 receives a “down” signal, current is drawn from the low-pass filter 116 . The low-pass filter 116 converts these signals to a control voltage (a DC level) that is used to control the VCO 118 .
  • a PLL output signal F o of the VCO 118 oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback signal F fb .
  • the phase detector 112 produces an “up” s signal
  • the frequency of PLL output signal F o increases.
  • a “down” signal decreases the frequency of the PLL output signal F o .
  • the output of the VCO 118 stabilizes once the reference signal F ref and the feedback signal F fb have the same phase and frequency.
  • the PLL output signal F o is referred to variously as “locked,” “locked to the reference signal,” and the like.
  • a divide-by-N counter 120 may be inserted in the feedback loop to increase an amplitude of the PLL output signal F o above the reference signal F ref .
  • the PLL output signal F o is equal to N times the reference signal F ref .
  • a lock detector 102 compares the reference signal F ref and the feedback signal F fb to determine when a lock condition has occurred. A lock signal is output when the lock condition has occurred.
  • FIG. 1 further illustrates a simple timing chart.
  • the frequency of the PLL output signal F o begins to increase.
  • the PLL frequency is not unstable and cannot be used by the system.
  • the PLL frequency has stabilized, but typically a period of time (t 2 -t 1 ) is allowed to pass to ensure that the PLL output signal F o has fully settled.
  • the lock signal remains “LO”.
  • the lock signal goes “HI” to signify that the PLL output signal F o is ready to clock the system logic.
  • FIG. 2 illustrates a conventional implementation for the lock detector 102 which determines signal lock based on the rising edges of the reference signal F ref and the feedback signal F fb .
  • the lock detector comprises two flip flop circuits, such as the flip flops 202 and 204 .
  • the reference signal F ref is delayed by an inverted delay line 206 , and the delayed signal F ref ′ feeds into the flip flop 202 .
  • the feedback signal F fb clocks the flip flop 202 .
  • the feedback signal F fb is delayed by an inverted delay line 208 , and the delayed signal F fb ′ feeds into the flip flop 204 .
  • the feedback signal F ref clocks the flip flop 204 .
  • the outputs of the flip flops 202 and 204 feed into NAND gate 210 .
  • a timing circuit 212 comprises a capacitor 222 that is charged by a current source 224 . So long as transistor 228 remains in the OFF condition, then after a certain amount of time proportional to I/C, where I is the current and C is the capacitance, the capacitor 222 will charge to a voltage level (i.e., a threshold voltage level) sufficient to trigger a buffer 228 and output a signal that constitutes the lock detect signal.
  • the transistor 228 is controlled by the output of the NAND gate 210 .
  • the phase between the reference signal F ref and the feedback signal F fb will vary until the feedback signal attains a lock with the reference signal.
  • FIG. 3 a timing diagram of the reference signal F ref and the feedback signal F fb is illustrated for the lock condition.
  • the shaded areas in the timing diagrams represent prior output states (“HI” or “LO”) that depend on the previous phase relation of the signals F ref and F fb .
  • the flip flops 202 and 204 shown in FIG. 2 are clocked on the rising edges of F fb and F ref respectively. Accordingly, the flip flops will latch respective inverted signals F ref ′ and F fb ′ delayed by ⁇ (the propagation delay of inverted delay lines 206 and 208 ).
  • ⁇ the propagation delay of inverted delay lines 206 and 208
  • the rising edges of the reference signal F ref and the feedback signal F fb are aligned.
  • the flip flop outputs Q 202 and Q 204 are “HI”, and consequently the output of NAND gate 210 is “LO”.
  • the transistor 228 is OFF and will remain in the OFF state so long as the lock condition exists, allowing the capacitor 222 to continue charging and the lock detect signal asserted.
  • FIG. 4 a timing diagram is illustrated for a “no lock” condition where the reference signal F ref and the feedback signal F fb are not in phase.
  • the timing diagram shows that the output of flip flop 202 is “LO” because of the timing of the rising edge of F fb relative to the inverted and delayed reference signal F ref ′. Accordingly, the NAND gate 210 is “HI” for this condition.
  • the transistor 228 is turned ON and consequently the capacitor 222 does not charge.
  • a timing diagram is illustrated for a “no lock” condition, where the phase relation between the reference signal F ref and the feedback signal F fb create a condition at time t x that causes the NAND gate 210 to incorrectly outputs a “LO” logic level.
  • the “LO” output of the NAND gate 210 turns OFF the transistor 228 , allowing the capacitor 222 to charge and the lock detect signal to erroneously assert.
  • a circuit includes inputs for receiving a reference signal and a target signal.
  • the circuit includes first circuitry to output first levels of the reference signal taken at the rising and falling edges of the target signal.
  • Second circuitry outputs second levels of the target signal taken at the rising and falling edges of the reference signal.
  • Third circuitry asserts a third level when the first and second levels indicate that the target signal is not in phase with the reference signal.
  • fourth circuitry outputs a fourth signal after an amount of time has passed, and is operative to be reset in response to occurrence of the third level.
  • the fourth circuitry may include a counter that includes a reset input connected to the third circuitry.
  • the fourth circuitry may include a current source, a transistor, and a capacitor. The capacitor is charged by a current from the current source, and can be discharged by the transistor.
  • the fourth circuitry may include a digital processing unit executing firmware.
  • the first circuitry includes a delay element to output a delayed reference signal, wherein the first levels are based on the delayed reference signal.
  • the second circuitry includes a delay element output a delayed target signal, wherein the third and fourth levels are based on the delayed target signal.
  • the circuit further includes a phase locked loop (PLL) circuit having an input to receive the reference signal and having a PLL feedback signal based on an output of the PLL circuit, wherein the PLL feedback signal is the target signal.
  • PLL phase locked loop
  • a method of operating a circuit includes receiving a reference signal and receiving a target signal. First levels of the reference signal are generated at the rising and falling edges of the target signal. Second levels of the target signal are generated at the rising and falling edges of the reference signal. An operation is performed which includes asserting a lock signal after an amount of time has passed. The operation is restarted when the first and second levels indicate that the target signal is not in phase with the reference signal.
  • FIGS. 1 and 2 show a prior art lock detector.
  • FIGS. 3-5 illustrate timing charts based on the prior art lock detector.
  • FIG. 6 shows an illustrative embodiment of a lock detector in accordance with principles of the present disclosure.
  • FIG. 6A illustrates the use of firmware for the timing circuitry.
  • FIGS. 7-9 show timing diagrams for various phase relations between the reference signal and the target signal in accordance with principles of the present disclosure.
  • FIG. 10 shows an embodiment of a lock detector of the present disclosure using an analog-based timing circuit.
  • a lock detector circuit in accordance with principles of the present disclosure can provide an indication of a lock condition between a reference signal and a target signal.
  • the reference signal may be a reference signal in a phase locked loop (PLL) circuit and the target signal may be a feedback signal in a feedback loop of the PLL circuit.
  • PLL phase locked loop
  • An example of a PLL circuit is illustrated in FIG. 1 .
  • the lock detector circuit in accordance with principles of the present disclosure can be used in any circuitry where it is desired to determine if one signal (e.g., the target signal) has achieved a lock with another signal (e.g., the reference signal).
  • a lock detector 600 may comprises flip flops 602 , 604 , 606 , and 608 .
  • the flip flops 602 and 604 constitute a dual edge-triggered detector.
  • flip flops 606 and 608 also constitute a dual edge-triggered detector.
  • the flip flops 602 , 604 , 606 , and 608 are D-type flip flops. It will be appreciated, however, that other types of flip flops may be substituted.
  • the lock detector 600 receives a reference signal F ref and a target signal F target , and may output a lock detect signal.
  • the reference signal F ref feeds into an inverted delay line 610 .
  • the inverted delay line 610 is associated with a propagation delay ⁇ .
  • the output of the inverted delay line 610 is an inverted signal F ref ′, which is delayed relative to the incoming reference signal F ref by an amount based on the propagation delay ⁇ .
  • the inverted signal F ref ′ feeds into flip flops 602 and 604 .
  • the flip flops 602 and 604 are clocked by the target signal F target .
  • the flip flop 602 is configured with a non-inverting clock input, and thus is triggered by the rising edges of the target signal F target ; while the flip flop 604 is configured with an inverting clock input, and so is triggered on the falling edges of the target signal.
  • the target signal F target feeds into an inverter 612 for detection, in addition to serving as a trigger.
  • the inverter 612 may have substantially the same propagation delay ⁇ as inverter 610 .
  • the output of the inverter 612 is an inverted signal F target ′, which is delayed relative to the incoming target signal F target by an amount proportional to ⁇ .
  • the inverted signal F target ′ feeds into flip flops 606 and 608 .
  • the flip flops 606 and 608 are clocked by the reference signal F ref .
  • the flip flop 606 is configured with a non-inverting clock input, and thus is triggered on the rising edges of the reference signal F ref .
  • the flip flop 608 is configured with an inverting clock input, and thus is triggered on the falling edges of the reference signal F ref .
  • any suitable means for detecting and holding a level of the reference signal F ref in synchrony with the rising edge and falling edge of the target signal F target may be used in place of the flip flops 602 and 604 .
  • any suitable means for detecting and holding a level of the target signal F target in synchrony with the rising edge and falling edge of the reference signal F ref may be used in place of the flip flops 606 and 608 .
  • the lock detector 600 may further include a NAND gate 614 for receiving outputs Q 604 and Q 608 of respective flip flops 604 and 608 .
  • An output of NAND gate 614 feeds into an input of an AND gate 616 .
  • the outputs Q 604 and Q 608 represent levels, respectively, of the inverted and delayed signals F ref ′ and F target ′ detected on the falling edges of signals F target and F ref , respectively.
  • the AND gate 616 receives input from flip flops 602 and 606 , in addition to input from NAND gate 614 .
  • the output Q 602 from flip flop 602 and the output Q 606 from flip flop 606 feed into AND gate 616 .
  • the outputs Q 602 and Q 606 represent levels, respectively, of the inverted and delayed signals F ref ′ and F target ⁇ detected on the rising edges of signals F target and F ref , respectively.
  • the lock detector 600 may further include a timing circuit 618 .
  • the timing circuit 618 operates for a given amount of time T from an initial state, and then asserts a signal at an output 618 a .
  • the timing circuit 618 may include a reset line 618 b that resets the timing circuit to the initial state, thus restarting the timing operation from that initial state.
  • the amount of time T may be configurable.
  • the output of AND gate 616 is connected to the reset line 618 b of the timing circuit 618 .
  • the timing circuit 618 may comprise a counter 622 .
  • the counter 622 may count from an initial state of zero to some maximum count value. It will be appreciated that any of numerous implementations for a counter may be employed.
  • An output of the counter 622 may serve as the output 618 a of the timing circuit 618 . For example, the output may be asserted when the counter has reached its maximum count value.
  • the counter 622 includes a reset input R (the figure shows an inverting reset input) that is connected to the reset line 618 b of the timing circuit 618 , which in turn is connected to the output of AND gate 616 . When the reset input R is asserted by the AND gate 616 , the counter 622 resets to the initial state and restarts the counting sequence; e.g., starts counting from zero.
  • the counter 622 may be clocked using the reference signal F ref and may be configured to assert a signal at its output after a maximum count value has been reached. Accordingly, the counter 622 can be configured to run for a suitable amount of time T by appropriately configuring the maximum count value.
  • the maximum count value may be programmable and hence the amount of time T can be programmed. In other embodiments, the maximum count value may be a fixed value.
  • the lock detector 600 may employ a timing circuit 618 ′ that is implemented with firmware comprising executable program code executing on a suitable digital processing unit 622 ′, such as a general purpose IO (GPIO) processor.
  • a suitable digital processing unit 622 ′ such as a general purpose IO (GPIO) processor.
  • the reset line 618 b and the reference signal F ref may be connected to input pins of the GPIO processor 622 ′.
  • the output 618 a may be connected to an output pin of the GPIO processor 622 ′.
  • the firmware can be programmed to respond to signals on the input pins to output a signal on the output pin to behave in the same manner as discussed above for timing circuit 618 shown in FIG. 6 .
  • FIG. 7 a timing diagram for the lock condition, where the target signal F target is locked to (i.e., in phase with) the reference signal F ref .
  • the shaded areas in the timing diagrams represent prior output states of the flip flops that depend on the previous phase relation of the signals F ref and F target .
  • the prior output states of the flip flops are not known and hence shaded.
  • the output Q 604 is “LO” when the flip flop 604 is triggered by the falling edge of the target signal F target because the signal level of the inverted signal F ref ′ is “LO” at the time of the trigger.
  • the output Q 608 is “LO” when the flip flop 608 is triggered by the falling edge of the reference signal F ref because the signal level of the inverted signal F target ′ is “LO” at the time of the trigger. Consequently, the output of NAND gate 614 is “HI”.
  • the output Q 602 is “HI” when the flip flop 602 is triggered by the rising edge of the target signal F target because the signal level of the inverted signal F ref ′ is “HI” at the time of the trigger.
  • the output Q 606 is “HI” when the flip flop 606 is triggered by the rising edge of the reference signal F ref because the signal level of the inverted signal F target is “HI” at the time of the trigger. Since all three inputs to the AND gate 616 are “HI”, the AND gate asserts a “HI” level on the reset line 618 b of the timing circuit 618 .
  • the counter 622 Since the reset input of the counter 622 is an inverted input, the counter does not reset and continues to count at rate based on the frequency of the clock signal, which in the embodiment shown in FIG. 6 is the reference signal F ref . When a period of time based on the maximum count value has passed, the counter 622 will assert a signal (e.g., “HI” level) on the output 618 a of the timing circuit 618 .
  • a signal e.g., “HI” level
  • the period of time can be adjusted depending on how much time is desired to determine that a lock condition has been achieved.
  • the feedback signal F fb i.e., the target signal
  • the feedback signal F ref may enter into a period where its frequency fluctuates above and below the reference frequency (signal F ref ), and hence a lock has not been achieved.
  • the period of time provided by the counter 622 therefore, should be long enough to avoid a false positive lock indication during those fluctuations.
  • timing charts similar to FIG. 7 can be used to arrive at the conclusion that other “no lock” (out of phase) conditions between F ref and F target will cause the timing circuit 618 to be held in a reset state.
  • an out of phase condition between F ref and F target places the timing circuit 618 in reset and prevents it from timing out.
  • the timing circuit 618 is enabled only when the F target is locked with F ref, where the timing circuit 618 can time out so that lock detect signal can be asserted, thus indicating that the target signal F target is deemed to be locked to the reference signal F ref.
  • FIG. 8 which shows a timing diagram of the lock detector 600 for the phase relation between F ref and F target shown in FIG. 4 .
  • the output of the AND gate 616 is “LO”, which will hold the counter 622 in reset.
  • FIG. 9 shows a timing diagram of the lock detector 600 for the “no lock” situation shown in FIG. 5 , where a conventional lock detector gave a false positive indication of a lock.
  • the output of AND gate 616 outputs “LO” when the falling edge of the target signal F target clocks the inverted signal F ref ′.
  • “LO” logic level at the output of AND gate 616 resets the counter 622 in the timing circuit 618 .
  • the AND gate 616 will maintain a “LO” output for the given phase relationship between F ref and F target, and thus will hold the counter 622 in reset.
  • a lock detector in accordance with principles of the present disclosure will correctly indicate a no lock situation (e.g., by not asserting the lock detect signal).
  • the lock detector 600 employs a timing circuit 618 comprising a counter 622 , which in some embodiments is a digital circuit.
  • a lock detector in accordance with principles of the present disclosure may employ an analog-based timing circuit.
  • a lock detector 1000 may include an analog timing circuit 1018 .
  • the timing circuit 1018 may employ a circuit similar to the circuit 212 shown in FIG. 2 .
  • the initial state of the timing circuit 1018 may be a fully discharged capacitor 1022 . When the capacitor 1022 charges to a level above a trigger level of the buffer 1024 , the buffer will assert a signal that constitutes the lock detect signal.
  • the timing circuit 1018 may be reset to the initial state when the output of AND gate 616 asserts a signal that turns ON transistor 1026 to discharge the capacitor 1022 .
  • the charge time of the capacitor 1022 is proportional to the current flow I into the capacitor and the capacitance of the capacitor.
  • the digital counter such as the counter 622 in FIG. 6 uses smaller components (and thus is more efficient in terms of area) and may consume less power than the analog counterpart.
  • the digital counter is more easily configurable. For example, the time can be varied by removing or adding counting stages (typically a flip flop) to the counter 622 without significant impact silicon area. Nonetheless, it will be appreciated that a lock detector in accordance with the principles of the present disclosure may employ the analog-based timing circuit 1018 instead of a digital circuit.

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  • Engineering & Computer Science (AREA)
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US13/950,427 US8624642B2 (en) 2010-10-26 2013-07-25 PLL dual edge lock detector
US14/100,274 US8749283B2 (en) 2010-10-26 2013-12-09 PLL dual edge lock detector

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US9584303B1 (en) * 2015-10-28 2017-02-28 Futurewei Technologies, Inc. Reference-less frequency detector with high jitter tolerance

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KR20140112656A (ko) * 2013-03-13 2014-09-24 한국전자통신연구원 디지털 위상 고정 루프
US9594100B2 (en) * 2013-09-06 2017-03-14 Analog Devices Global Apparatus and method for evaluating the performance of a system in a control loop
US9077512B2 (en) 2013-09-18 2015-07-07 Analog Devices, Inc. Lock detector for phase-locked loop
KR20160090796A (ko) * 2013-11-27 2016-08-01 마이크로칩 테크놀로지 인코포레이티드 메인 클록의 높은 정밀 발진기
US9467154B2 (en) 2015-01-12 2016-10-11 Microchip Technology Incorporated Low power and integrable on-chip architecture for low frequency PLL
US9647671B2 (en) 2015-01-22 2017-05-09 Wright State University High performance phase frequency detectors
KR102375952B1 (ko) 2015-01-22 2022-03-17 삼성전자주식회사 위상 고정 검출 장치 및 검출 방법
JP6863373B2 (ja) * 2016-05-11 2021-04-21 ソニーグループ株式会社 検出装置および検出方法
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US20140097879A1 (en) 2014-04-10
WO2012058010A2 (en) 2012-05-03
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US8624642B2 (en) 2014-01-07
US20120098570A1 (en) 2012-04-26
EP2633620A4 (en) 2015-04-01
US20130307596A1 (en) 2013-11-21
EP2633620B1 (en) 2018-02-28
CN103563249B (zh) 2017-02-15
EP2633620A2 (en) 2013-09-04
KR101811020B1 (ko) 2017-12-20
US8749283B2 (en) 2014-06-10
CN103563249A (zh) 2014-02-05
WO2012058010A3 (en) 2014-04-03
CN106603071A (zh) 2017-04-26

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