US8227788B2 - Nonvolatile memory element, and nonvolatile memory device - Google Patents

Nonvolatile memory element, and nonvolatile memory device Download PDF

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US8227788B2
US8227788B2 US12/863,535 US86353509A US8227788B2 US 8227788 B2 US8227788 B2 US 8227788B2 US 86353509 A US86353509 A US 86353509A US 8227788 B2 US8227788 B2 US 8227788B2
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electrode
resistance variable
resistance
current
nonvolatile memory
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US20100295012A1 (en
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Takumi Mikawa
Kiyotaka Tsuji
Takashi Okada
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Nuvoton Technology Corp Japan
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Panasonic Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
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    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/066—Shaping switching materials by filling of openings, e.g. damascene method
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0073—Write using bi-directional cell biasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10—Resistive cells; Technology aspects
    • G11C2213/15—Current-voltage curve
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/32—Material having simple binary metal oxide structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50—Resistive cell structure aspects
    • G11C2213/56—Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/72—Array wherein the access device being a diode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode

Definitions

  • the present invention relates to a nonvolatile memory element and a nonvolatile memory device which include a resistance variable element which stably changes resistance values to be retained, in response to voltage pulses applied.
  • the resistance variable element refers to an element which has a characteristic in which a resistance value changes reversibly in response to electric signals and is able to store information corresponding to the resistance value in a nonvolatile manner.
  • PCRAM phase change random access memory
  • the resistance variable element changes its resistance value by changing redox states of a resistance variable material, directly in response to the electric stresses applied thereto, i.e., by migration of electrons.
  • the cross-point nonvolatile memory element has a structure suitable for miniaturization, and an element including a resistance variable layer as a memory section and a non-linear element such as a varistor as a current controlling element is disclosed (e.g., see patent document 1).
  • FIG. 19 is a view showing a nonvolatile memory device including a conventional resistance variable element.
  • FIG. 19 is a cross-sectional view of a memory cell 380 taken along the direction of a bit line 310 , in a cross-point memory cell array including bit lines 310 , word lines 320 and memory cells 380 formed at cross-points of the bit lines 310 and the word lines 320 .
  • a resistance variable element 360 includes a resistance variable layer 330 for storing data according to a change in an electric resistance because of electric stresses applied thereto, an upper electrode 340 and a lower electrode 350 sandwiching the resistance variable layer 330 between them.
  • the memory cell 380 is constituted by a series circuit including the resistance variable element 360 and the non-linear element 370 .
  • the non-linear element 370 is a two-terminal element such as a diode, having a nonlinear current-voltage characteristic in which a current changes inconstantly with respect to a voltage change.
  • the bit line 310 serving as an upper wire is electrically connected to the non-linear element 370 .
  • the word line 320 serving as a lower wire is electrically connected to the lower electrode 350 of the resistance variable element 360 .
  • a varistor ZnO or SrTiO 3
  • a current-voltage characteristic which is bidirectionally (both at positive voltage side and negative voltage side) symmetric and non-linear.
  • the current controlling element having a current-voltage characteristic which is bidirectionally symmetric and non-linear, like the varistor, a resistance changing operation (reversible switching between a high-resistance state and a low-resistance state by application of voltages) is unstable, and in some cases the resistance variable element or the current controlling element is broken down due to an excess current.
  • the present invention is directed to solving the above mentioned problem, and an object of the present invention is to provide a resistance variable nonvolatile memory element and a resistance variable nonvolatile memory device which are capable of stabilizing a resistance changing operation and of reducing a sneak current in a cross-point memory.
  • a bipolar resistance variable element which reversibly changes between a high-resistance state and a low-resistance state by application of voltages with different polarities
  • currents and voltages for allowing the resistance variable element to change from the low-resistance state to the high-resistance state are higher than currents and voltages for allowing the resistance variable element to change from the high-resistance state to the low-resistance state (attain the low-resistance state: perform a set operation).
  • the bipolar resistance variable element has an unsymmetric current-voltage characteristic with respect to polarity.
  • the resistance variable element having such a characteristic is connected to the bidirectionally symmetric current controlling element (element in which resistance is higher when the absolute value of an applied voltage is smaller and a slope ( ⁇ I/ ⁇ V) of a current-voltage curve is larger as the absolute value of the applied voltage is larger).
  • the current controlling element relatively insufficiently restricts the current when the resistance variable element changes to the low-resistance state, so that an excess current flows through the resistance variable element.
  • a sneak current flowing through unselected cells increases, making it difficult to write data to and read data from a selected cell.
  • a nonvolatile memory element of the present invention comprises a resistance variable element configured to reversibly change between a low-resistance state and a high-resistance state in response to electric signals with different polarities which are applied thereto; and a current controlling element configured such that when a current flowing when a voltage whose absolute value is a first value as a desired value which is larger than 0 and smaller than a predetermined voltage value and whose polarity is a first polarity is applied is a first current and a current flowing when a voltage whose absolute value is the first value and whose polarity is a second polarity different from the first polarity is applied is a second current, the first current is higher than the second current; the resistance variable element including a first electrode, a second electrode, and a resistance variable layer which comprises oxygen-deficient transition metal oxide and is provided between the first electrode and the second electrode; the resistance variable element being connected in series with the current controlling element such that a
  • Another nonvolatile memory element of the present invention comprises a resistance variable element configured to reversibly change between a low-resistance state and a high-resistance state corresponding to a resistance value larger than a resistance value corresponding to the low-resistance state, in response to electric signals with different polarities which are applied thereto; and a bidirectional current controlling element having an unsymmetric characteristic in which when a current flowing when a voltage whose absolute value is a first value as a desired value which is larger than 0 and smaller than a predetermined voltage value and whose polarity is a first polarity is applied is a first current and a current flowing when a voltage whose absolute value is the first value and whose polarity is a second polarity different from the first polarity is applied is a second current, the first current is higher than the second current;
  • the resistance variable element including a first electrode, a second electrode, and a resistance variable layer which comprises oxygen-deficient transition metal oxide and is provided between the first electrode and the
  • the resistance variable element may include a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode.
  • the resistance variable element may be configured such that a resistance value between the first electrode and the second electrode increases when an electric signal with a positive polarity is applied between the first electrode and the second electrode on the basis of the first electrode, and decreases when an electric signal with a negative polarity is applied between the first electrode and the second electrode on the basis of the first electrode.
  • the resistance variable layer may include oxygen-deficient transition metal oxide.
  • the current controlling element may include a third electrode, a fourth electrode and a semiconductor layer provided between the third electrode and the fourth electrode and may be configured such that a polarity with which the fourth electrode is placed at a positive potential on the basis of the third electrode between the third electrode and the fourth electrode is the first polarity.
  • the current controlling element may be configured such that (A) the second electrode is connected to the third electrode such that the resistance variable layer and the semiconductor layer do not intervene between the second electrode and the third electrode; or (B) the first electrode is connected to the fourth electrode such that the resistance variable layer and the semiconductor layer do not intervene between the first electrode and the fourth electrode.
  • the resistance variable element may include a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode.
  • the resistance variable element may be configured such that a resistance value between the first electrode and the second electrode increases when an electric signal with a positive polarity is applied between the first electrode and the second electrode on the basis of the first electrode, and decreases when an electric signal with a negative polarity is applied between the first electrode and the second electrode on the basis of the first electrode.
  • the resistance variable layer may include oxygen-deficient transition metal oxide.
  • the current controlling element may include a third electrode, the first electrode and a semiconductor layer provided between the third electrode and the first electrode and may be configured such that a polarity with which the first electrode is placed at a positive potential on the basis of the third electrode between the third electrode and the first electrode is the first polarity.
  • the resistance variable element may include a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode.
  • the resistance variable element may be configured such that a resistance value between the first electrode and the second electrode increases when an electric signal with a positive polarity is applied between the first electrode and the second electrode on the basis of the first electrode, and decreases when an electric signal with a negative polarity is applied between the first electrode and the second electrode on the basis of the first electrode.
  • the resistance variable layer may include oxygen-deficient transition metal oxide.
  • the current controlling element may include the second electrode, a fourth electrode and a semiconductor layer provided between the second electrode and the fourth electrode and may be configured such that a polarity with which the fourth electrode is placed at a positive potential on the basis of the second electrode between the second electrode and the fourth electrode is the first polarity.
  • the first electrode may comprise a first material; the second electrode may comprise a second material; and when a standard electrode potential of the first material is V1, a standard electrode potential of the second material is V2, and a standard electrode potential of transition metal of the oxygen-deficient transition metal oxide is Vt, Vt ⁇ V2 and V1 ⁇ V2 may be satisfied.
  • the resistance variable layer is allowed to change its resistance only at a specified region which is the interface between the resistance variable layer and the second electrode with the higher standard electrode potential V2, and it is possible to suppress an incorrect operation at the interface between the resistance variable layer and the first electrode with the standard electrode potential V1 lower than the standard electrode potential Vt of the transition metal of the oxygen-deficient transition metal oxide.
  • the polarity with which the resistance changes is always invariable, it is possible to implement a resistance variable nonvolatile memory device which performs a resistance changing operation more stably.
  • the resistance variable layer may include a first layer which is configured to physically contact the first electrode and has a composition expressed as MO x (M: transition metal element) and a second layer which is configured to physically contact the second electrode and has a composition expressed as MO y , and x ⁇ y may be satisfied.
  • the resistance variable layer is allowed to change its resistance only at a specified region with higher oxygen content which is the interface between the resistance variable layer and the second electrode. This is because, in a mechanism of the resistance changing operation, oxidation and reduction of oxygen in the vicinity of the electrode interface are dominant, and therefore the resistance changing phenomenon occurs preferentially at the interface where oxygen which contributes to oxidation and reduction is more in amount. In such a configuration, also, since the polarity with which the resistance changes is always invariable, it is possible to implement a resistance variable nonvolatile memory device which performs the resistance changing operation more stably.
  • the semiconductor layer may comprise n-type semiconductor; the third electrode and the fourth electrode may comprise different materials; and when electron affinity of the semiconductor layer is ⁇ s, a work function of the third electrode is ⁇ 1 , and a work function of the fourth electrode is ⁇ 2 , ⁇ s ⁇ 1 ⁇ 2 may be satisfied.
  • the diode element Since the current drivability of a diode element is determined by the current in a direction in which a reverse bias voltage is applied at the interface between the semiconductor layer and the metal, the diode element is allowed to have a higher current drivability in the direction in which the reverse bias voltage is applied to the third electrode with a lower barrier. In this case, the current flows more easily in a direction from the fourth electrode to the third electrode than in an opposite direction.
  • the diode elements can be fabricated using the same mask, which effectively reduces the process cost and achieves miniaturization.
  • the semiconductor layer may comprise n-type semiconductor; the third electrode and the first electrode may comprise different materials; and when electron affinity of the semiconductor layer is ⁇ s, a work function of the third electrode is ⁇ 1 , and a work function of the first electrode is ⁇ 2 , ⁇ s ⁇ 1 ⁇ 2 may be satisfied.
  • the semiconductor layer may comprise n-type semiconductor; the second electrode and the fourth electrode may comprise different materials; and when electron affinity of the semiconductor layer is ⁇ s, a work function of the second electrode is ⁇ 1 , and a work function of the fourth electrode is ⁇ 2 , ⁇ s ⁇ 1 ⁇ 2 may be satisfied.
  • a high current required to change the resistance variable element to the high-resistance state is obtained during a reset operation for attaining the high-resistance state, while a controlled less and necessary current can be flowed to change the resistance variable element to the low-resistance state during a set operation for attaining the low-resistance state.
  • a resistance variable nonvolatile memory device which performs a resistance changing operation stably.
  • the diode elements can be fabricated using the same mask, which effectively reduces the process cost and provide miniaturization.
  • the current controlling element is allowed to have a higher current drivability in the direction in which a reverse bias voltage is applied to the third electrode with a larger contact area. In this case, also, the current flows more in a direction from the fourth electrode to the third electrode. Therefore, it is desirable to connect the first electrode of the resistance variable element to the fourth electrode of the diode element, or the second electrode of the resistance variable element to the third electrode of the diode element when the resistance changes at the interface between the resistance variable layer and the second electrode.
  • the nonvolatile memory element when an area of a portion of the third electrode and a portion of the semiconductor layer which are in contact with each other is S 1 , and an area of a portion of the first electrode and a portion of the semiconductor layer which are in contact with each other is S 2 , S 1 >S 2 may be satisfied. Or, in the nonvolatile memory element, when an area of a portion of the second electrode and a portion of the semiconductor layer which are in contact with each other is S 1 , and an area of a portion of the fourth electrode and a portion of the semiconductor layer which are in contact with each other is S 2 , S 1 >S 2 may be satisfied.
  • the transition metal oxide may be tantalum oxide or hafnium oxide.
  • a nonvolatile memory device which has a stable and reversible rewrite characteristic, has a good retention characteristic of a resistance value, as well as high-speed operability, and can be manufactured with a manufacturing process which is highly compatible with a standard Si semiconductor process especially when tantalum oxide is used.
  • a nonvolatile memory device of the present invention provides a cross-point nonvolatile memory device comprising a substrate; a plurality of first wires which are formed to extend in parallel with each other on the substrate; a plurality of second wires which are formed above the plurality of first wires such that the plurality of second wires extend in parallel with each other within a plane parallel to a main surface of the substrate and three-dimensionally cross the plurality of first wires, respectively; and a plurality of nonvolatile memory elements each of which is described above and which are provided to respectively correspond to three-dimensional cross-points of the plurality of first wires and the plurality of second wires and to electrically connect the first wires to the second wires, respectively.
  • a resistance changing operation is stabilized in a nonvolatile memory element including a bipolar resistance variable element.
  • a sneak current flowing to unselected cells can be reduced.
  • FIG. 1 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 1 of the present invention.
  • FIG. 2 is a top view showing an exemplary schematic configuration of the nonvolatile memory element and the nonvolatile memory device according to Embodiment 1 of the present invention.
  • FIG. 3 is a view showing a characteristic of a resistance variable element, in which FIG. 3( a ) is a graph showing an exemplary current-voltage characteristic of a resistance variable element 105 and FIG. 3( b ) is a graph showing an exemplary change in a resistance value in a case where electric pulses are applied to the resistance variable element 105 .
  • FIG. 4 is a view for explaining a current controlling element having a symmetric current-voltage characteristic, in which FIG. 4( a ) is a view of an energy band in a thickness direction of a current controlling element including n-type semiconductor, and lower and upper electrodes which comprise the same metal and sandwich the n-type semiconductor, and FIG. 4( b ) is a graph schematically showing a current-voltage characteristic of the current controlling element of FIG. 4( a ).
  • FIG. 5 is a view for explaining a current controlling element having a unsymmetric current-voltage characteristic, in which FIG. 5( a ) is a view of an energy band in a thickness direction of a current controlling element 112 (current controlling element including n-type semiconductor, lower and upper electrodes which comprise different metals and sandwich the n-type semiconductor), and FIG. 5( b ) is a graph schematically showing the current-voltage characteristic of the current controlling element of FIG. 5( a ).
  • FIG. 6 is a view showing a voltage division relationship and a current at each of interfaces in a current controlling element, in which FIG. 6( a ) is a view showing the voltage division relationship and the current at each of the interfaces in the symmetric current controlling element of FIG. 4 and FIG. 6( b ) is a view showing the voltage division relationship and the current at each of the interfaces in the unsymmetric current controlling element of FIG. 5 .
  • FIG. 7 is a view showing a circuit of a nonvolatile memory device according to Embodiment 1 of the present invention, in which FIG. 7( a ) is a circuit diagram of the nonvolatile memory device according to Embodiment 1 of the present invention, and FIG. 7( b ) is an equivalent circuit diagram showing a current flowing through a selected cell and unselected cells in a case where the selected cell of FIG. 7( a ) is used as a reference.
  • FIG. 8 is a table showing an example of metals and semiconductor layers which are selectable.
  • FIG. 9 is a process step view showing a manufacturing method of a nonvolatile memory device 10 of this embodiment, in which FIG. 9( a ) is a view showing a step of forming first wires on a substrate, FIG. 9( b ) is a view showing a step of forming a first interlayer insulating layer, first contact plugs and second contact plugs; FIG. 9( c ) is a view showing a step of forming resistance variable elements and FIG. 9( d ) is a view showing a step of forming a second interlayer insulating layer, third contact plugs and fourth contact plugs.
  • FIG. 10 is process step view showing a manufacturing method of the nonvolatile memory device 10 of this embodiment
  • FIG. 10( a ) is a view showing a step of forming current controlling elements
  • FIG. 10( b ) is a step of forming a third interlayer insulating layer, fifth contact plugs and sixth contact plugs
  • FIG. 10( c ) is a view showing a step of forming second wires and lead-out wires.
  • FIG. 11 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 2 of the present invention.
  • FIG. 12 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 3 of the present invention.
  • FIG. 13 is a process step view showing a manufacturing method of major constituents of a nonvolatile memory device 30 of this embodiment, in which FIG. 13( a ) is a view showing a step of forming a conductive layer, a semiconductor layer and a conductive layer over the second interlayer insulating layer in this order, FIG. 13( b ) is a view showing a step of forming a resist pattern over the conductive layer, FIG. 13( c ) is a view showing a step of forming the upper electrodes of current controlling elements, and FIG. 13( d ) is a view showing a step of forming a resist pattern on the semiconductor layer using a desired mask, and FIG. 13( e ) is a view showing a step of forming the semiconductor layers and the lower electrodes of the current controlling elements.
  • FIG. 14 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 4 of the present invention.
  • FIG. 15 is a process step view showing the manufacturing method of a nonvolatile memory device 40 of this embodiment, in which FIG. 15( a ) is a view showing a step of forming first wires and a first conductive layer on the substrate, FIG. 15( b ) is a view showing a step of forming the first interlayer insulating layer, through-holes and first resistance variable layers, FIG. 15( c ) is a view showing a step of filling a material of second resistance variable layers, FIG. 15( d ) is a view showing a step of forming first intermediate electrodes and FIG. 15( e ) is a view showing a step of forming first contact plugs.
  • FIG. 16 is a process step view showing the manufacturing method of the nonvolatile memory device 40 of this embodiment, in which FIG. 16( a ) is a view showing a step of forming a first semiconductor layer, a second conductive layer, second wires and a third conductive layer, FIG. 16( b ) is a view showing a step of forming a second interlayer insulating layer, through-holes and third resistance variable layers, and FIG. 16( c ) is a view showing a step of filling a material of fourth resistance variable layers.
  • FIG. 17 is a process step view showing the manufacturing method of the nonvolatile memory device 40 of this embodiment, in which FIG. 17( a ) is a view showing a step of forming second intermediate electrodes, FIG. 17( b ) is a view showing a step of forming second contact plugs and FIG. 17( c ) is a view showing a step of forming a second semiconductor layer, a fourth conductive layer and third wires.
  • FIG. 18 is a process step view showing the manufacturing method of the nonvolatile memory device 40 of this embodiment, in which FIG. 18( a ) is a view showing a step of forming a third interlayer insulating layer, third contact plugs 223 and fourth contact plugs, and FIG. 18( b ) is a view showing a step of forming first lead-out wires 225 and second lead-out wires 226 .
  • FIG. 19 is a view showing a nonvolatile memory device including a conventional resistance variable element.
  • FIG. 1 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 1 of the present invention.
  • FIG. 2 is a top view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 1 of the present invention.
  • the cross-sectional view which is taken in the direction of arrows along one-dotted line 1 A- 1 A′ of FIG. 2 , corresponds to FIG. 1 .
  • a nonvolatile memory device 10 of this embodiment includes in a schematic configuration, a substrate 100 , a plurality of first wires 101 which are formed to extend in parallel with each other in a first direction (rightward and leftward direction in FIGS. 1 and 2 ) on a main surface of the substrate 100 , a plurality of second wires 119 which are formed above the plurality of first wires 101 such that the plurality of second wires 119 extend in parallel with each other in a second direction (direction perpendicular to the depth direction of sheet of FIG. 1 and an upward and downward direction in FIG.
  • nonvolatile memory elements 11 which are provided to respectively correspond to three-dimensional cross-points of the first wires 101 and the second wires 119 such that the nonvolatile memory elements 11 connect (electrically connect, hereinafter the same occurs) the first wires 101 to the second wires 119 , respectively.
  • Each nonvolatile memory element 11 includes a resistance variable element 105 , a current controlling element 112 , and a third contact plug 110 connecting the resistance variable element 105 to the current controlling element 112 .
  • Each resistance variable element 105 includes a lower electrode 106 (first electrode), an upper electrode 108 (second electrode) and a resistance variable layer 107 provided between the lower electrode 106 and the upper electrode 108 .
  • the lower electrode 106 is physically in contact with the resistance variable layer 107
  • the upper electrode 108 is physically in contact with the resistance variable layer 107 .
  • Each current controlling element 112 includes a lower electrode 113 (third electrode), an upper electrode 115 (fourth electrode) and a semiconductor layer 114 provided between the lower electrode 113 and the upper electrode 115 .
  • the lower electrode 113 is physically in contact with the semiconductor layer 114
  • the upper electrode 115 is physically in contact with the semiconductor layer 114 .
  • a first interlayer insulating layer 102 is formed over the substrate 100 to cover the first wires 101 .
  • a plurality of resistance variable elements 105 are formed on the first interlayer insulating layer 102 such that the resistance variable elements 105 are arranged at equal intervals on the first electrode wires 101 when viewed in a stacking direction (upward direction in FIG. 1 : hereinafter thickness direction) of the first wires 101 .
  • the first wires 101 are connected to the lower electrodes 106 of the resistance variable elements 105 located above the first wires 101 via first contact plugs 103 penetrating the first interlayer insulating layer 102 , respectively.
  • a second interlayer insulating layer 109 is formed over the first interlayer insulating layer 102 to cover the resistance variable elements 105 .
  • a plurality of current controlling elements 112 are formed on the second interlayer insulating layer 109 such that the current controlling elements 112 overlap with the resistance variable elements 105 when viewed in the thickness direction.
  • Each third contact plug 110 connects (short-circuits) the upper electrode 108 of the resistance variable element 105 to the lower electrode 113 of the current controlling element 112 such that the resistance variable layer 107 and the semiconductor layer 114 do not intervene between them.
  • a third interlayer insulating layer 116 is formed over the second interlayer insulating layer 109 to cover the current controlling elements 112 .
  • Second wires 119 are formed on the third interlayer insulating layer 116 such that the second wires 119 cross the first electrode wires perpendicularly to the first electrode wires and overlap with the resistance variable elements 105 and the current controlling elements 112 , respectively when viewed in a thickness direction.
  • the second wires 119 are connected to the upper electrodes 115 of the current controlling elements 112 located below the second wires 119 via fifth contact plugs 117 penetrating the third interlayer insulating layer 116 , respectively.
  • Lead-out wires 120 are formed on the third interlayer insulating layer 116 such that the lead-out wires 120 are located outside the section where the nonvolatile memory elements 11 are arranged when viewed in the thickness direction and extend in parallel with the second wires 119 , i.e., in a second direction.
  • Second contact plugs 104 penetrate the first interlayer insulating layer 102
  • fourth contact plugs 111 penetrate the second interlayer insulating layer 109
  • sixth contact plugs 118 penetrate the third interlayer insulating layer 116 to connect the first wires 101 to the lead-out wires 120 , respectively.
  • the second contact plug 104 , the fourth contact plug 111 and the sixth contact plug 118 are stacked together in this order and interconnected to form a stacked contact for connecting the first wire 101 to the lead-out wire 120 .
  • the first wires 101 , the second wires 119 and the lead-out wires 120 comprise, for example, aluminum.
  • the first interlayer insulating layer 102 , the second interlayer insulating layer 109 , and the third interlayer insulating layer 116 comprise, for example, silicon oxide.
  • the first contact plugs 103 , the second contact plugs 104 , the third contact plugs 110 , the fourth contact plugs 111 , the fifth contact plugs 117 and the sixth contact plugs 118 comprise, for example, tungsten.
  • a nonvolatile memory device is implemented to include so-called a cross-point memory cell array in which the nonvolatile memory elements 11 are arranged at respective three-dimensional cross-points of the first wires 101 and the second wires 119 which three-dimensionally cross each other, when the nonvolatile memory device 10 is viewed in the thickness direction.
  • the resistance variable layer 107 contains an oxygen-deficient transition metal oxide (transition metal oxide having less oxygen content [atom ratio: ratio of oxygen atoms to total number of atoms] than a stoichiometric oxide).
  • the resistance variable layer 107 comprises a transition metal oxide made of oxygen-deficient oxide of tantalum (TaO x : 0 ⁇ x ⁇ 2.5) or oxygen-deficient oxide of hafnium (HfO x : 0 ⁇ x ⁇ 2). More preferably, the resistance variable layer 107 comprises oxygen-deficient oxide of tantalum or oxygen-deficient oxide of hafnium.
  • the standard electrode potential of a material (first material) making up the lower electrode 106 is V1
  • the standard electrode potential of a material (second material) making up the upper electrode 108 is V2
  • the standard electrode potential of a transition metal (in a case where the oxidation number of this transition metal is zero) in the oxygen-deficient transition metal oxide included in the resistance variable layer 107 is Vt, Vt ⁇ V2 and V1 ⁇ V2 are satisfied.
  • the material of the upper electrode 108 is oxidated less easily than the material of the resistance variable layer 107 .
  • the material of the upper electrode 108 is not oxidated and reduced but the material of the resistance variable layer 107 is oxidated and reduced when the electrons migrate at the interface between the upper electrode 108 and the resistance variable layer 107 . This causes a change in an oxidation state of the resistance variable layer 107 , and results in a resistance changing phenomenon.
  • a positive voltage (positive electric signal) is applied to the upper electrode 108 on the basis of the lower electrode 106 , and a current flows from the upper electrode 108 to the lower electrode 106 .
  • a current flows from the upper electrode 108 to the lower electrode 106 .
  • electrons migrate from the resistance variable layer 107 to the electrode.
  • the material of the resistance variable layer 107 is oxidated and the resistance value increases.
  • a negative voltage (negative electric signal) is applied to the upper electrode 108 on the basis of the lower electrode 106 , and a current flows from the lower electrode 106 to the upper electrode 108 .
  • electrons migrate from the electrode to the resistance variable layer 107 .
  • the material of the resistance variable layer 107 is reduced and the resistance value decreases.
  • the lower electrode 106 for example, tantalum nitride (TaN) may be used.
  • the upper electrode 108 for example, platinum (Pt) may be used.
  • Vt ⁇ 0.6V (standard electrode potential of tantalum). Therefore, Vt ⁇ V2 and V1 ⁇ V2 are satisfied.
  • Vt ⁇ 1.55V (standard electrode potential of hafnium). Therefore, Vt ⁇ V2 and V1 ⁇ V2 are satisfied.
  • the thickness of the resistance variable layer is set to, for example, 30 nm.
  • FIG. 3 is a view showing a characteristic of a resistance variable element, in which FIG. 3( a ) is a graph showing an exemplary current-voltage characteristic of the resistance variable element 105 and FIG. 3( b ) is a graph showing an exemplary change in a resistance value in a case where electric pulses are applied to the resistance variable element 105 .
  • the resistance variable element 105 changes from the low-resistance state to the high-resistance state at point A (attains the high-resistance state).
  • the voltage is about +0.9V and the current is about +9 mA.
  • the resistance variable element 105 changes from the high-resistance state to the low-resistance state at point C (attains the low-resistance state).
  • the voltage is about ⁇ 0.7V and the current is about ⁇ 0.1 mA.
  • the high-resistance state refers to a state in which the resistance value (resistance value between the lower electrode 106 and the upper electrode 108 ) is higher than the resistance value corresponding to the low-resistance state.
  • the low-resistance state refers to a state in which the resistance value is lower than the resistance value corresponding to the high-resistance state.
  • the resistance variable element 105 To change the resistance variable element 105 to the high-resistance state, it is necessary to flow a current of about 9 mA so that the point A is reached. On the other hand, to change the resistance variable element 105 to the low-resistance state, it is sufficient to flow a current which is as low as about 0.1 mA so that the point C is reached. In other words, the resistance variable element 105 exhibits a characteristic in which a current required to attain the high-resistance state is higher than a current required to attain the low-resistance state.
  • FIG. 3( b ) shows an example of a measurement result of the resistance value (resistance value between the lower electrode 106 and the upper electrode 108 ) of the resistance variable element 105 in a case where an electric pulse (electric signal) with a voltage of +1.5V and a pulse width of 100 nsec and an electric pulse with a voltage of ⁇ 1.2V and a pulse width of 100 nsec are applied alternately to the upper electrode 108 on the basis of the lower electrode 106 between the lower electrode 106 and the upper electrode 108 .
  • the resistance value reaches about 1200 ⁇ 1500 ⁇ (high-resistance state).
  • the resistance variable element 105 exhibits a characteristic in which the absolute value of the voltage of the electric pulse applied to attain the high-resistance state is larger than the absolute value of the voltage of the electric pulse applied to attain the low-resistance state, when the resistance variable element 105 repeats stable resistance change.
  • the resistance variable element 105 has an unsymmetric characteristic with respect to the polarity.
  • the current controlling element 112 having the above configuration is composed of the lower electrode 113 comprising tungsten, the semiconductor layer 114 comprising n-type semiconductor silicon, and the upper electrode 115 comprising tantalum nitride.
  • the thickness of the semiconductor layer 114 is set to, for example, 3 ⁇ 20 nm.
  • the work function of tungsten is 4.6 eV.
  • the electron affinity of silicon is 3.78 eV.
  • the work function of tantalum nitride is 4.76 eV.
  • the work function of the lower electrode is ⁇ 1
  • the electron affinity of the semiconductor layer is ⁇ s
  • the work function of the upper electrode is ⁇ 2
  • ⁇ s ⁇ 1 ⁇ 2 is satisfied.
  • the current controlling element 112 is a MSM diode utilizing a Schottky barrier formed at an interface between metal and semiconductor.
  • the current controlling element 112 has an unsymmetric current-voltage characteristic according to the voltage polarity.
  • the current controlling element 112 has a current-voltage characteristic in which when a current flowing when a voltage whose absolute value is a first value as a desired value which is larger than 0 and smaller than a predetermined voltage value and whose polarity is positive (first polarity) is applied to the upper electrode 115 on the basis of the lower electrode 113 is a first current and a current flowing when a voltage whose absolute value is the first value and whose polarity is negative (second polarity different from the first polarity) is applied to the upper electrode 115 on the basis of the lower electrode 113 is a second current, the first current is higher than the second current.
  • the current controlling element 112 has a higher current drivability when the voltage with the first polarity is applied than when the voltage with the second polarity is applied.
  • the current controlling element 112 has a characteristic in which, with respect to a desired value a which satisfies 0 ⁇ a ⁇ 1 (i.e., in a whole range of 0 ⁇ a ⁇ 1), a current flowing when the voltage of +aV is applied to the upper electrode on the basis of the lower electrode is higher than a current flowing when the voltage of ⁇ aV is applied to the upper electrode on the basis of the lower electrode, when the predetermined voltage value is, for example, 1V.
  • the current controlling element refers to an element having a current-voltage characteristic (monotonous increase characteristic) in which as the absolute value of the applied voltage is larger, the absolute value of the flowing current is larger regardless of whether the polarity is the first polarity or the second polarity, and a current-voltage characteristic (nonlinear characteristic) in which as the absolute value of the applied voltage is larger, a change rate (slope: change amount of the absolute value of the current/change amount of the absolute value of the voltage) of the current with respect to the voltage is larger regardless of whether the polarity is the first polarity or the second polarity, as depicted in FIG. 4( a ) and FIG. 4( b ) described later.
  • a current-voltage characteristic monotonous increase characteristic
  • the absolute value of the flowing current is larger regardless of whether the polarity is the first polarity or the second polarity
  • a current-voltage characteristic nonlinear characteristic
  • the predetermined voltage value may be specifically defined as follows.
  • the resistance variable element 105 and the current controlling element 112 are connected in series to constitute the nonvolatile memory element 11 .
  • the predetermined voltage value may be defined as a larger one of the absolute values of the voltages (voltage applied to the current controlling element 112 when the nonvolatile memory element 11 changes to the high-resistance state and voltage applied to the current controlling element 112 when the nonvolatile memory element 11 changes to the low-resistance state) applied between the lower electrode 113 and the upper electrode 115 of the current controlling element 112 when the voltage is applied between the both ends of the nonvolatile memory element 11 so that a voltage required to change the resistance variable element 105 to the high-resistance state or to the low-resistance state is applied between the lower electrode 106 and the upper electrode 108 of the resistance variable element 105 .
  • the current controlling element 112 properly restricts the current when the resistance state of the resistance variable element 105 is changed in an actual operation.
  • a specific example of the predetermined voltage value may be 3.0[V] when the above mentioned resistance variable element (lower electrode: tantalum nitride, upper electrode: platinum, resistance variable layer: tantalum oxide, thickness of resistance variable layer: 30 nm, shape in a thickness direction: square of 0.5 ⁇ m ⁇ 0.5 ⁇ m) and the above mentioned current controlling element (lower electrode: tungsten, upper electrode: tantalum nitride, semiconductor layer: silicon, thickness of semiconductor layer: 10 nm, shape in a thickness direction: square of 0.5 ⁇ m ⁇ 0.5 ⁇ m).
  • This current controlling element has a structure in which upper and lower electrodes comprise the same metal and n-type semiconductor is sandwiched between these electrodes.
  • FIG. 4 is a view of the current controlling element having the symmetric current-voltage characteristic, in which FIG. 4( a ) is a view of an energy band in a thickness direction of the current controlling element including the n-type semiconductor, the upper and lower electrodes which comprise the same metal and sandwich the n-type semiconductor, and FIG. 4( b ) is a graph schematically showing the current-voltage characteristic of the current controlling element of FIG. 4( a ).
  • ⁇ 1 indicates a work function of the metal which is the electrode material
  • ⁇ s indicates a work function of the n-type semiconductor
  • ⁇ s indicates electron affinity of the n-type semiconductor.
  • a current J (current flowing from the metal to the semiconductor) flowing through the Schottky barrier satisfies the following formula (1): J ⁇ exp( ⁇ B/kT)exp[(qV/kT) ⁇ 1] (1) where V indicates a potential of the metal on the basis of the semiconductor, q indicates an electric charge of electrons, k indicates a Boltzmann constant, and T indicates an absolute temperature.
  • the current flows from the metal to the semiconductor (electrons migrate from the semiconductor to the metal) when the voltage (forward bias voltage: V>0) is applied in such a manner that the potential of the metal is higher than the potential of the semiconductor).
  • V>0 forward bias voltage
  • the potential of the semiconductor decreases, the potential of the electrons inside the semiconductor rises.
  • the height of the barrier which is viewed from the semiconductor is relatively lowered, allowing the electrons to more easily travel beyond the barrier. Therefore, when the forward bias voltage is applied, the current increases exponentially as the absolute value of the voltage is larger.
  • the slope of the Schottky barrier at the interface which is reversely biased becomes steep, so that the barrier is thinner. If the absolute value of the voltage exceeds a certain level, then the electrons easily travel beyond the barrier because of a tunneling effect or the like. In other words, when the absolute value of the voltage is above a certain level, then an influence of the barrier at the interface reversely biased may be negligible.
  • the MSM diode has a feature that it exhibits a large resistance value because of the influence of the Schottky barrier generated at the interface reversely biased, when the absolute value of the voltage is below a certain level, but the resistance value drastically decreases when the absolute value of the voltage exceeds a certain level.
  • the current-voltage characteristic is symmetric with respect to the polarity and non-linear with respect to the voltage.
  • the fact that the current-voltage characteristic is symmetric with respect to the polarity means that the absolute value of the current is equal when the absolute value of the applied voltage V is equal.
  • the fact that the current-voltage characteristic is non-linear with respect to the voltage means that not a substantial current flows in a range where the absolute value of the applied voltage is smaller, but a higher current flows in a range where the absolute value of the applied voltage is larger (curve I). In other words, as the absolute value of the applied voltage is larger, the slope ( ⁇ I/ ⁇ V) is larger.
  • the current controlling element 112 having an unsymmetric current-voltage characteristic according to the polarity in this embodiment will be described.
  • the current controlling element 112 has a structure in which the lower and upper electrodes comprise different metals and sandwich the n-type semiconductor.
  • FIG. 5 is a view of a current controlling element having an unsymmetric current-voltage characteristic, in which FIG. 5( a ) is a view of an energy band in a thickness direction of the current controlling element 112 (current controlling element including the n-type semiconductor, the lower and upper electrodes which comprise different metals and sandwich the n-type semiconductor), and FIG. 5( b ) is a graph schematically showing the current-voltage characteristic of the current controlling element of FIG. 5( a ).
  • the material of the lower electrode is metal 1
  • the material of the upper electrode is metal 2
  • ⁇ 1 indicates a work function of the metal 1
  • ⁇ 2 indicates a work function of the metal 2 ( ⁇ 2> ⁇ 1)
  • ⁇ s indicates a work function of the n-type semiconductor
  • ⁇ s indicates electron affinity of the n-type semiconductor.
  • Schottky barriers with different heights are formed at the interface between the lower electrode and the n-type semiconductor and at the interface between the upper electrode and the n-type semiconductor.
  • the current-voltage characteristic is unsymmetric with respect to the polarity and non-linear with respect to the voltage.
  • the current-voltage characteristic is similar to that of the curve I of FIG. 4( b ) in that not a substantial current flows in a range where the absolute value of the applied voltage is smaller, but a higher current flows in a range where the absolute value of the applied voltage is larger. However, if the absolute value of the voltage is equal, a current flowing by applying the positive voltage to the upper electrode on the basis of the lower electrode is higher than a current flowing by applying the negative voltage to the upper electrode on the basis of the lower electrode (curve II).
  • the curve of the negative portion and the curve of the positive portion do not cross each other in at least a range in which a voltage is larger than 0 and smaller than a predetermined voltage value (e.g., 1V). Therefore, a relationship is satisfied, in which a current flowing by applying a voltage of +aV to the upper electrode on the basis of the lower electrode when a desired value which is larger than 0V and smaller than the predetermined voltage value is a is always higher than a current flowing by applying a voltage of ⁇ aV to the upper electrode on the basis of the lower electrode.
  • a predetermined voltage value e.g. 1V
  • a current flowing through a MSM diode element is restricted by a reversely biased interface in a range in which the absolute value of the applied voltage is below a certain level. Therefore, the current flowing through the MSM diode element may be explained using a model in which two Schottky diodes are connected in series such that they face different directions. Now, a mechanism in which the current-voltage characteristic of the current controlling element 112 is unsymmetric will be described using the model.
  • FIG. 6 is a view showing a voltage division relationship and a current at each of interfaces in the current controlling element, in which FIG. 6( a ) is a view showing a voltage division relationship and a current at each of the interfaces in the symmetric current controlling element of FIG. 4 and FIG. 6( b ) is a view showing a voltage division relationship and a current at each of the interfaces in the unsymmetric current controlling element of FIG. 5 .
  • a current (current in a reverse bias direction) I R (>0) flowing through the lower electrode interface satisfies the following formula (3) when a voltage allocated to the lower electrode interface is V R (>0): I R ⁇ exp( ⁇ B/kT)exp[( ⁇ qV R /kT) ⁇ 1] (3)
  • a negative voltage ⁇ V TOTAL is applied to the upper electrode on the basis of the lower electrode.
  • a flowing current is ⁇ I O
  • a voltage allocated to the upper electrode interface is ⁇ V R
  • a voltage allocated to the lower electrode interface is ⁇ V F .
  • the magnitude of the current is equal if the absolute value of the applied voltage is equal (see curve I in FIG. 5( b )).
  • FIG. 6( b ) is a view showing a voltage division relationship and a current at each of the interfaces in the unsymmetric current controlling element of FIG. 5 .
  • a positive voltage V TOTAL is applied to the upper electrode on the basis of the lower electrode in the unsymmetric current controlling element.
  • a forward bias occurs at the upper electrode interface and a reverse bias occurs at the lower electrode interface.
  • a current I 2F (>0) in a forward bias direction flowing through the upper electrode interface satisfies the following formula (4) when a voltage allocated to the upper electrode interface is V 2F (>0): I 2F ⁇ exp( ⁇ B2/kT)exp[(qV 2F /kT) ⁇ 1] (4)
  • a current I 1R (>0) in a reverse bias direction flowing through the lower electrode interface satisfies the following formula (5) when a voltage allocated to the lower electrode interface is V 1R (>0): I 1R ⁇ exp( ⁇ B1/kT)exp[( ⁇ qV 1R /kT) ⁇ 1] (5)
  • An actual current and an actual voltage converge at an intersection C of the two graphs.
  • a negative voltage ⁇ V TOTAL is applied to the upper electrode on the basis of the lower electrode.
  • a reverse bias occurs at the upper electrode interface because the metal (electrode) is at a lower potential than the semiconductor layer, while a forward bias occurs at the lower electrode interface because the metal (electrode) is at a higher potential than the semiconductor layer.
  • a current I 2R (>0) in a reverse bias direction flowing through the upper electrode interface satisfies the following formula (6) when a voltage allocated to the upper electrode interface is V 2R (>0): I 2R ⁇ exp( ⁇ B2/kT)exp[( ⁇ qV 2R /kT) ⁇ 1] (6)
  • a current I 1F (>0) in a forward bias direction flowing through the lower electrode interface satisfies the following formula (7) when a voltage allocated to the lower electrode interface is V 1F (>0): I 1F ⁇ exp( ⁇ B1/kT)exp[(qV 1F /kT) ⁇ 1] (7)
  • An actual current and an actual voltage converge at an intersection B of the two graphs.
  • the above description relates to a case where the applied voltage is relatively low and an influence of the reversely biased interface is not negligible. As the absolute value of the voltage is larger, then this influence may be negligible, and the resistance value of the current controlling element drastically decreases.
  • the specific characteristic of the current controlling element varies depending on the thickness of each layer, the size of the electrode surface, etc.
  • the specific configuration of the current controlling element may be suitably selected so that a desired characteristic is attained based on the relationship with the resistance variable elements and other constituents, with reference to the above explanation.
  • the specific design is easy to persons skilled in the art and therefore will not be described in detail.
  • the resistance variable element 105 and the current controlling element 112 are connected in series, and the voltage applied to the current controlling element 112 to change the resistance variable element 105 from the low-resistance state to the high-resistance state (attain the high-resistance state) has a polarity (first polarity) with which a higher current flows through the current controlling element when the absolute value of the voltage applied to the current controlling element is equal.
  • first polarity first polarity
  • the fact that the current flows in such a direction means that a voltage having a polarity with which the upper electrode 115 is placed at a positive potential on the basis of the lower electrode 113 , is applied to the associated current controlling element 112 .
  • the polarity, with which the upper electrode 115 is placed at a positive potential on the basis of the lower electrode 113 is the polarity (first polarity) with which the current controlling element 112 has a higher current drivability.
  • the upper electrode 108 of the resistance variable element 105 is connected to the lower electrode 113 of the current controlling element 112 such that the resistance variable layer 107 and the semiconductor layer 114 do not intervene between the upper electrode 108 and the lower electrode 113 so that the direction of the voltage for changing the resistance variable layer 107 of the resistance variable element 105 from the low-resistance state to the high-resistance state conforms to the direction in which the current drivability of the current controlling element 112 is higher and the direction of the voltage for changing the resistance variable layer 107 of the resistance variable element 105 from the high-resistance state to the low-resistance state conforms to the direction in which the current drivability of the current controlling element 112 is lower.
  • the resistance variable element 105 is connected in series with the current controlling element 112 such that the direction of the current flowing through the resistance variable element 105 when the resistance variable element 105 is changed from the low-resistance state to the high-resistance state conforms to the direction of the first current flowing through the current controlling element 112 .
  • a high current required to attain the high-resistance state is obtained when the positive voltage is applied to the second wire 119 on the basis of the first wire 101 (when the resistance variable element 105 is changed to the high-resistance state).
  • the negative voltage is applied to the second wire 119 on the basis of the first wire 101 (when the resistance variable element 105 is changed to the low-resistance state)
  • a minimum current required to attain the low-resistance state flows and the current controlling element 112 can prevent a high current from flowing abruptly after the low-resistance state is attained. Therefore, it is possible to implement a resistance variable nonvolatile memory element and a resistance variable nonvolatile memory device which perform a resistance changing operation stably.
  • FIG. 7 is a view showing a circuit of the nonvolatile memory device according to Embodiment 1 of the present invention, in which FIG. 7( a ) is a circuit diagram of the nonvolatile memory device according to Embodiment 1 of the present invention, and FIG. 7( b ) is an equivalent circuit diagram showing a current flowing through a selected cell and unselected cells in a case where the selected cell of FIG. 7( a ) is used as a reference.
  • a cross-point memory cell array is configured such that the resistance variable elements 105 and the current controlling elements 112 are formed to respectively correspond to the three-dimensional cross-points of N-rows of word lines (first wires 101 ) and M-columns of bit lines (second wires 119 ).
  • the current controlling element 112 has an unsymmetric characteristic with respect to the polarity and therefore, the current drivabilities of the diode elements are expressed as the magnitude of symbols ⁇ and ⁇ .
  • a rewrite current Icell flows through the selected cell.
  • sneak current paths which connect (M ⁇ 1) cells on the column to which the selected cell belongs to (N ⁇ 1) cells on the row to which the selected cell belongs, i.e., sneak current paths which are as many as (N ⁇ 1) ⁇ (M ⁇ 1) cells which is a product of these, and a sum of currents flowing therethrough is expressed as a sneak current I sneak.
  • one or more current controlling elements in a direction with a lower current drivability are always included in the sneak current paths, regardless of whether the positive voltage or the negative voltage is applied to the selected cell. This can lessen an overall amount of sneak current.
  • the upper electrode of one of the resistance variable element and the current controlling element and the lower electrode of the other may be an identical constituent.
  • the upper electrode of the resistance variable element and the lower electrode of the current controlling element may be an identical constituent.
  • the upper electrode of the current controlling element and the lower electrode of the resistance variable element may be an identical constituent.
  • the resistance variable element is changed to the high-resistance state, and the current controlling element is allowed to have a higher current drivability when the current flows from the second wire 119 to the first wire 101 (current flows from the upper side to the lower side with respect to the substrate).
  • the resistance variable element may be changed to the high-resistance state, and the current controlling element is allowed to have a higher current drivability when the current flows from the first wire 101 to the second wire 119 (current flows from the lower side to the upper side with respect to the substrate).
  • the materials of the upper electrode and the lower electrode may be reversed. Further, the arrangement (vertical positional relationship) of the resistance variable element and the current controlling element may be reversed.
  • FIG. 8 is a table showing examples of metals and semiconductor layers which are selectable.
  • silicon nitride As the semiconductor layer of the current controlling element, desired semiconductor materials such as silicon nitride may be used instead of silicon. In an actual nonvolatile memory device 10 , silicon nitride is desirably used in view of an electric resistance and a current supply capability.
  • FIGS. 9 and 10 are process step views showing the manufacturing method of the nonvolatile memory device 10 of this embodiment.
  • FIG. 9( a ) is a view showing a step of forming first wires on a substrate
  • FIG. 9( b ) is a view showing a step of forming a first interlayer insulating layer, first contact plugs and second contact plugs
  • FIG. 9( c ) is a view showing a step of forming resistance variable elements
  • FIG. 9( d ) is a view showing a step of forming a second interlayer insulating layer, third contact plugs and fourth contact plugs.
  • FIG. 10( a ) is a view showing a step of forming current controlling elements
  • FIG. 10( b ) is a step of forming a third interlayer insulating layer, fifth contact plugs and sixth contact plugs
  • FIG. 10( c ) is a view showing a step of forming second wires and lead-out wires.
  • the first wires 101 are formed on the substrate 100 provided with transistors and lower wires, using a desired mask.
  • the first interlayer insulating layer 102 is formed over the entire surface of the substrate 100 such that the first interlayer insulating layer 102 covers the first wires 101 .
  • the contact holes (holes) are formed to penetrate the first interlayer insulating layer 102 and reach the first wires 101 .
  • a filling material containing tungsten as a major component is filled into the contact holes, thereby forming the first contact plugs 103 and the second contact plugs 104 .
  • a conductive layer comprising tantalum nitride, a resistance variable layer comprising tantalum oxide and a conductive layer comprising platinum are formed over the first interlayer insulating layer 102 in this order.
  • Patterning is performed using a desired mask so as to cover the upper end surfaces of the first contact plugs 103 and expose the upper end surfaces of the second contact plugs 104 , thereby forming the lower electrodes 106 , the resistance variable layers 107 and the upper electrodes 108 of the resistance variable elements 105 .
  • the oxygen-deficient tantalum oxide can be deposited by, for example, so-called reactive sputtering in which sputtering is performed under an atmosphere of argon and oxygen gases, using a tantalum target.
  • the second interlayer insulating layer 109 is formed over the entire surface of the first interlayer insulating layer 102 so as to cover the resistance variable elements 105 .
  • Contact holes (holes) are formed to penetrate the second interlayer insulating layer 109 and reach the upper electrodes 108 of the resistance variable elements 105 , while contact holes (holes) are formed to penetrate the second interlayer insulating layer 109 and reach the second contact plugs 104 .
  • a filling material containing tungsten as a major component is filled into the former contact holes to form the third contact plugs 110 .
  • a filling material containing tungsten as a major component is filled into the latter contact holes to form the fourth contact plugs 111 .
  • the conductive layer comprising tungsten, the semiconductor layer comprising silicon or silicon nitride, and the conductive layer comprising tantalum nitride are formed in this order over the second interlayer insulating layer 109 .
  • Patterning is performed using a desired mask to cover the upper end surfaces of the third contact plugs 110 and expose the upper end surfaces of the fourth contact plugs 111 , thereby forming the lower electrodes 113 , the semiconductor layers 114 and the upper electrodes 115 of the current controlling elements 112 .
  • the third interlayer insulating layer 116 is formed over the entire surface of the second interlayer insulating layer so as to cover the current controlling elements 112 .
  • Contact holes (holes) are formed to penetrate the third interlayer insulating layer 116 and reach the upper electrodes 115 of the current controlling elements 112 , and contact holes (holes) are formed to penetrate the third interlayer insulating layer 116 and reach the fourth contact plugs 111 .
  • a filling material containing tungsten as a major component is filled into the former contact holes to form the fifth contact plugs 117 .
  • a filling material containing tungsten as a major component is filled into the latter contact holes to form the sixth contact plugs 118 .
  • the second wires 119 and the lead-out wires 120 are patterned using a desired mask on the third interlayer insulating layer 116 such that the second wires 119 cover the upper end surfaces of the fifth contact plugs 117 , respectively, and the lead-out wires 120 cover the upper end surfaces of the sixth contact plugs 118 , respectively.
  • FIG. 11 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 2 of the present invention.
  • a nonvolatile memory device 20 and a nonvolatile memory element 21 of Embodiment 2 are different from the nonvolatile memory device 10 and the nonvolatile memory element 11 of Embodiment 1 in that a resistance variable layer of a resistance variable element has a stacked structure.
  • the other constituents are similar to those of Embodiment 1. Therefore, in Embodiment 2, the same constituents as those in Embodiment 1 are designated by the same reference numerals and will not be described repetitively.
  • each resistance variable layer is composed of two layers which are a resistance variable layer 107 a (first layer) and a resistance variable layer 107 b (second layer).
  • the resistance variable layer 107 a and the resistance variable layer 107 b comprise the same element, i.e., oxygen-deficient oxide of the same transition metal.
  • the oxygen content (the value of x in a case where transition metal is expressed as M and the composition of the resistance variable layer 107 a is expressed as MO x ) of the resistance variable layer 107 a which is in contact with the lower electrode 106 is lower than the oxygen content (value of y in a case where transition metal is expressed as M and the composition of the resistance variable layer 107 b is expressed as MO y ) of the resistance variable layer 107 b which is in contact with the upper electrode 108 (x ⁇ y).
  • the thickness of the resistance variable layer 107 a and the thickness of the resistance variable layer 107 b are set to, for example, 30 ⁇ 50 nm.
  • the shape of the resistance variable layer 107 a and the resistance variable layer 107 b may be, for example, a square of 0.5 ⁇ m ⁇ 0.5 ⁇ m, when viewed in the thickness direction.
  • the resistance variable layers with different oxygen contents can be formed with the manufacturing method (reactive sputtering process) of the resistance variable layer described in Embodiment 1. That is, the oxygen content of the stacked tantalum oxide is higher as the oxygen flow rate is set higher during the deposition, while the oxygen content of the stacked tantalum oxide is lower as the oxygen flow rate is set lower during the deposition.
  • FIG. 12 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 3 of the present invention.
  • a nonvolatile memory device 30 and a nonvolatile memory element 31 of Embodiment 3 are different from the nonvolatile memory device 20 and the nonvolatile memory element 21 of Embodiment 2 in that the lower electrode and the upper electrode of the current controlling element are different in size (contact area).
  • the other constituents are similar to those of Embodiment 2. Therefore, in Embodiment 3, the same constituents as those in Embodiment 2 are designated by the same reference numerals and will not be described repetitively.
  • the current drivability of the MSM diode is determined by the magnitude of the current in the reverse bias direction.
  • a high current required to attain the high-resistance state is obtained when a positive voltage is applied to the second wire 119 on the basis of the first wire 101 (when the resistance variable element 105 is changed to the high-resistance state).
  • a negative voltage is applied to the second wire 119 on the basis of the first wire 101 (when the resistance variable element 105 is changed to the low-resistance state)
  • a minimum current required to attain the low-resistance state flows, and the current controlling element 112 ′ can prevent a high current from flowing abruptly after the low-resistance state is attained. Therefore, it is possible to implement a resistance variable nonvolatile memory element and a resistance variable nonvolatile memory device which perform a resistance changing operation stably.
  • FIG. 13 is a process step view showing the manufacturing method of major constituents of the nonvolatile memory device 30 of this embodiment.
  • the manufacturing method of other constituents is similar to that of Embodiment 1 and will not be described repetitively.
  • FIG. 13( a ) is a view showing a step of forming the conductive layer, the semiconductor layer and the conductive layer over the second interlayer insulating layer in this order
  • FIG. 13( b ) is a view showing a step of forming a resist pattern over the conductive layer
  • FIG. 13( c ) is a view showing a step of forming the upper electrodes of current controlling elements
  • FIG. 13( d ) is a view showing a step of forming a resist pattern on the semiconductor layer using a desired mask
  • FIG. 13( e ) is a view showing a step of forming the semiconductor layers and the lower electrodes of the current controlling elements.
  • a conductive layer 113 a comprising tungsten
  • a semiconductor layer 114 a comprising silicon or silicon nitride
  • a conductive layer 115 a comprising tantalum nitride
  • a photoresist pattern 121 is formed on the conductive layer 115 a comprising tantalum nitride using a desired mask.
  • the conductive layer 115 a comprising tantalum nitride is patterned using the photoresist pattern 121 , to form the upper electrodes 115 ′ of the current controlling elements. Then the photoresist left is removed.
  • a photoresist pattern 122 is formed using a desired mask on the semiconductor layer 114 a comprising silicon to cover the upper electrodes 115 ′ of the current controlling elements 112 ′.
  • the semiconductor layer 114 a comprising silicon or silicon nitride and the conductive layer 113 a comprising tungsten are patterned using the photoresist pattern 122 to cover the upper end surfaces of the third contact plugs 110 and expose the upper end surfaces of the fourth contact plugs 111 , thereby forming the semiconductor layers 114 and the lower electrodes 113 of the current controlling elements 112 ′.
  • FIG. 14 is a cross-sectional view showing an exemplary schematic configuration of a nonvolatile memory element and a nonvolatile memory device according to Embodiment 4 of the present invention.
  • a nonvolatile memory device 40 and a nonvolatile memory element 41 of Embodiment 4 are different from those in Embodiment 1 ⁇ Embodiment 3 in that the lower electrode of the resistance variable element is formed integrally with the wire, remaining constituents of the resistance variable element are formed inside the through-hole, the lower electrode of the current controlling element is formed inside the through-hole, remaining constituents of the current controlling element are formed integrally with the wire, and the memory cells are stacked in two layers.
  • Embodiment 4 is adapted for achievement of miniaturization and a large capacity.
  • the nonvolatile memory device 40 of this embodiment includes in a schematic configuration, a substrate 200 , a plurality of first wires 201 which are formed to extend in parallel with each other in a first direction (rightward and leftward direction in FIG. 14 ) on a main surface of the substrate 200 , a plurality of second wires 211 which are formed above the plurality of first wires 201 such that the plurality of second wires 211 extend in parallel with each other in a second direction (direction perpendicular to the depth direction of sheet of FIG.
  • first nonvolatile memory elements 41 which are provided to respectively correspond to three-dimensional cross-points of the first wires 201 and the second wires 211 such that the nonvolatile memory elements 41 connect the first wires 201 to the second wires 211 , respectively
  • second nonvolatile memory elements 42 which are provided to respectively correspond to three-dimensional cross-points of the second wires 211 and the third wires 221 such that the second nonvolatile elements 42 connect the second wires 211 to the third wires 221 , respectively.
  • the first wires 201 and the third wires 221 have the same shape and overlap with each other when viewed in the stacking direction (from above in FIG. 14 , hereinafter referred to as a thickness direction) of the first wires 201 .
  • Each first nonvolatile memory element 41 includes a first resistance variable element 204 and a first current controlling element 208 .
  • the upper electrode of the first resistance variable element 204 and the lower electrode of the first current controlling element 208 are an identical constituent.
  • Each first resistance variable element 204 includes a first conductive layer 202 constituting a lower electrode (second electrode), a first intermediate electrode 206 constituting an upper electrode (first electrode), and a resistance variable layer sandwiched between these two electrodes.
  • the resistance variable layer is composed of two layers which are a first resistance variable layer 205 b (second layer) and a second resistance variable layer 205 a (first layer).
  • the first resistance variable layer 205 b which is in contact with the first conductive layer 202 comprises oxygen-deficient tantalum oxide with high oxygen content.
  • the second resistance variable layer 205 a which is in contact with the first intermediate electrode 206 comprises oxygen-deficient tantalum oxide with low oxygen content.
  • hafnium oxide may be used, or other oxygen-deficient transition metal oxide may be used.
  • the definition of the oxygen content of the first resistance variable layer 205 b and the oxygen content of the second resistance variable layer 205 a is the same as that in Embodiment 2, and will not be described repetitively.
  • the thickness of the first resistance variable layer 205 a and the thickness of the second resistance variable layer 205 b may be set to, for example, 100 ⁇ 200 nm and 1 ⁇ 10 nm, respectively.
  • the diameter of the first resistance variable layer 205 a and the diameter of the second resistance variable layer 205 b in a thickness direction may be set to, for example, 50 ⁇ 300 nm ⁇ .
  • Each first current controlling element 208 includes a first intermediate electrode 206 constituting a lower electrode (first electrode), a second conductive layer 210 constituting an upper electrode (third electrode) and a first semiconductor layer 209 sandwiched between these two electrodes.
  • the first intermediate electrode 206 serves as the upper electrode of the first resistance variable element 204 and the lower electrode of the first current controlling element 208 .
  • Each second nonvolatile memory element 42 includes a second resistance variable element 214 and a second current controlling element 218 .
  • the upper electrode of the second resistance variable element 224 and the lower electrode of the second current controlling element 228 are an identical constituent.
  • Each second resistance variable element 214 includes a third conductive layer 212 constituting a lower electrode (second electrode), a second intermediate electrode 216 constituting an upper electrode (first electrode) and a resistance variable layer sandwiched between these two electrodes.
  • the resistance variable layer has two layers which are a third resistance variable layer 215 b (second layer) and a fourth resistance variable layer 215 a (first layer).
  • the third resistance variable layer 215 b which is in contact with the third conductive layer 212 comprises oxygen-deficient tantalum oxide with high oxygen content.
  • the fourth resistance variable layer 215 a which is in contact with the second intermediate electrode 216 comprises oxygen-deficient tantalum oxide with low oxygen content.
  • hafnium oxide may be used, or other oxygen-deficient transition metal oxide may be used.
  • the definition of the oxygen content of the third resistance variable layer 215 b and the oxygen content of the fourth resistance variable layer 215 a is the same as that in Embodiment 2, and will not be described repetitively.
  • the thickness of the third resistance variable layer 215 a and the thickness of the fourth resistance variable layer 215 b are set to, for example, 100 ⁇ 200 nm and 1 ⁇ 10 nm, respectively.
  • Each second current controlling element 218 includes a second intermediate electrode 216 constituting a lower electrode (first electrode), a fourth conductive layer 220 constituting an upper electrode (third electrode), and a second semiconductor layer 219 sandwiched between these two electrodes.
  • the second intermediate electrode 216 serves as the upper electrode of the second resistance variable element 214 and the lower electrode of the second current controlling element 218 .
  • the first wire 201 and the first conductive layer 202 are stacked together in this order to have the same shape and overlap with each other when viewed in the thickness direction.
  • a first interlayer insulating layer 203 is formed to cover the first wires 201 and the first conductive layers 202 .
  • a plurality of though-holes are formed on the first conductive layers 202 to penetrate the first interlayer insulating layer 203 and reach the first conductive layers 202 such that the through holes are arranged at equal intervals when viewed in the thickness direction.
  • the first resistance variable layer 205 b , the second resistance variable layer 205 a , and the first intermediate electrode 206 are stacked together in this order.
  • the first semiconductor layer 209 , the second conductive layer 210 , the second wire 211 and the third conductive layer 212 are stacked together in this order to have the same shape and overlap with each other when viewed in the thickness direction so as to cover the upper end surface of each of the first intermediate electrodes 206 .
  • a second interlayer insulating layer 213 is formed to cover the first semiconductor layers 209 , the second conductive layers 210 , the second wires 211 and the third conductive layers 212 .
  • a plurality of though-holes are formed on the third conductive layers 212 to penetrate the second interlayer insulating layer 213 and reach the third conductive layers 212 such that the through-holes are arranged at equal intervals when viewed in the thickness direction.
  • the third resistance variable layer 215 b , the fourth resistance variable layer 215 a , and the second intermediate electrode 216 are stacked together in this order.
  • the second interlayer insulating layer 213 On the second interlayer insulating layer 213 , the second semiconductor layer 219 , the fourth conductive layer 220 and the third wire 221 are stacked together in this order to have the same shape and overlap with each other when viewed in the thickness direction so as to cover the upper end surface of each of the second intermediate electrodes 216 .
  • a third interlayer insulating layer 222 is formed to cover the second semiconductor layers 219 , the fourth conductive layers 220 and the third wires 221 .
  • Contact holes are formed at end portions of the third wires to penetrate the third interlayer insulating layer 222 and reach the third wires.
  • Fourth contact plugs 224 are formed on the third wires exposed in the respective contact holes, and first lead-out wires 225 are formed to cover the upper end surfaces of the fourth contact plugs 224 and to extend in a fourth direction such that the first lead-out wires 225 three-dimensionally cross the third wires, respectively.
  • second lead-out wires 226 are formed to extend in parallel with the first lead-out wires 225 , i.e., in the fourth direction.
  • First contact plugs 207 , second contact plugs 217 and third contact plugs 223 penetrate the first interlayer insulating layer 203 , the second interlayer insulating layer 213 and the third interlayer insulating layer 222 , respectively such that the first wires 201 are connected to the lead-out wires 226 , respectively.
  • the first contact plug 107 , the second contact plug 217 and the third contact plug 223 are stacked together in this order and interconnected to form a stacked contact for connecting the first wire 201 to the lead-out wire 226 .
  • nonvolatile memory device including a two-layer cross-point memory cell array, in which the first nonvolatile memory elements 41 are provided at three-dimensional cross-points of the first wires 201 and the second wires 211 which three-dimensionally cross each other, and the second nonvolatile memory elements 42 are provided at three-dimensional cross-points of the second wires 211 and the third wires 221 which three-dimensionally cross each other, when the nonvolatile memory device 40 is viewed in the thickness direction.
  • the first conductive layer 202 and the third conductive layer 212 serve as the lower electrodes of the resistance variable elements, respectively, and comprise, for example, platinum.
  • the first intermediate electrode 206 and the second intermediate electrode 216 serve as the upper electrode of the resistance variable element and the lower electrode of the current controlling element, respectively, and comprise, for example, tantalum nitride.
  • the second conductive layer 210 and the fourth conductive layer 220 serve as the upper electrodes of the current controlling elements, respectively, and comprise, for example, tungsten.
  • the first semiconductor layer 209 and the second semiconductor layer 219 comprise, for example, silicon or silicon nitride.
  • the first wires 201 , the second wires 211 , the third wires 221 , the first lead-out wires 225 and the second lead-out wires 226 comprise, for example, copper.
  • the first contact plugs 207 , the second contact plugs 217 , the third contact plugs 223 and the fourth contact plugs 224 comprise, for example, tungsten.
  • the first interlayer insulating layer 203 , the second interlayer insulating layer 213 and the third interlayer insulating layer 222 comprise, for example, silicon oxide.
  • Vt ⁇ 0.6V (standard electrode potential of tantalum).
  • Vt ⁇ 1.55V (standard electrode potential of hafnium). In either case, Vt ⁇ V2 and V1 ⁇ V2 are satisfied.
  • the oxygen content of the first resistance variable layer 205 b which is in contact with the lower electrode is higher than the oxygen content of the second resistance variable layer 205 a which is in contact with the upper electrode.
  • the oxygen content of the third resistance variable layer 215 b which is in contact with the lower electrode is higher than the oxygen content of the fourth resistance variable layer 215 a which is in contact with the upper electrode.
  • the resistance changing phenomenon occurs preferentially at the interface between the lower electrode and the resistance variable layer.
  • the area of a portion of the upper electrode and a portion of the semiconductor layer which are in contact with each other is smaller than the area of a portion of the lower electrode and a portion of the semiconductor layer which are in contact with each other. Therefore, a current flowing in the case where the upper electrode side is reversely biased is higher than a current flowing in the case where the lower electrode side is reversely biased.
  • the current drivability of the first current controlling element 208 and the current drivability of the second current controlling element 218 are higher when the current flows from the lower electrode to the upper electrode (the vertical positional relationship is reversed between Embodiment 1 and Embodiment 3).
  • the nonvolatile memory device 40 and the nonvolatile memory elements 41 and 42 of this embodiment are configured such that the resistance variable element is connected in series with the current controlling element, and a voltage applied to the current controlling element when the resistance variable element is changed from the low-resistance state to the high-resistance state (attains the high-resistance state) is set to have a polarity with which a higher current is allowed to flow through the current controlling element if the absolute values of the voltages applied to the current controlling element are equal.
  • a current flows from the lower electrode to the upper electrode in the resistance variable element in this embodiment when the resistance variable element is changed to the high-resistance state.
  • the fact that the current flows in such a direction means that a voltage having a polarity with which the upper electrode is placed at a negative potential on the basis of the lower electrode is applied to the associated current controlling element.
  • the polarity with which the upper electrode is placed at a negative potential on the basis of the lower electrode is the polarity with which the current drivability of the current controlling element is higher.
  • the upper electrode of the resistance variable element and the lower electrode of the current controlling element are formed by an identical constituent so that the direction of the voltage for changing the resistance variable layer of the resistance variable element from the low-resistance state to the high-resistance state is the same as the direction for allowing the current controlling element to have a higher current drivability and the direction of the voltage for changing the resistance variable layer of the resistance variable element from the high-resistance state to the low-resistance state is the same as the direction for allowing the current controlling element to have a lower current drivability.
  • a high current required to attain the high-resistance state is obtained when a negative voltage is applied to the second wire 211 on the basis of the first wire 201 (when the resistance variable element 204 is changed to the high-resistance state).
  • a positive voltage is applied to the second wire 211 on the basis of the first wire 201 (when the resistance variable element 204 is changed to the low-resistance state)
  • a minimum current required to attain the low-resistance state flows, and the current controlling element 208 can prevent a high current from flowing abruptly after the low-resistance state is attained.
  • a high current required to attain the high-resistance state is obtained when a negative voltage is applied to the third wire 211 on the basis of the second wire 211 (when the resistance variable element 214 is changed to the high-resistance state).
  • a positive voltage is applied to the third wire 221 on the basis of the second wire 211 (when the resistance variable element 214 is changed to the low-resistance state)
  • a minimum current required to attain the low-resistance state flows, and the current controlling element 218 can prevent a high current from flowing abruptly after the low-resistance state is attained.
  • the upper electrode of the resistance variable element and the lower electrode of the current controlling element are formed by an identical constituent, and the lower electrode of the resistance variable element and the semiconductor layer and the upper electrode of the current controlling element have the same shape as the wire and overlap with the wire when viewed in the thickness direction. Therefore, the nonvolatile memory device 40 and the nonvolatile memory elements 41 and 42 of this embodiment are adapted for miniaturization and achievement of a larger capacity.
  • the lower electrode of the resistance variable element and the upper electrode of the current controlling element are an identical constituent (second electrode).
  • the nonvolatile memory device 40 and the nonvolatile memory elements 41 and 42 may be configured such that the resistance variable element 204 is changed to the high-resistance state when a positive voltage is applied to the second wire 211 on the basis of the first wire 201 , and the resistance variable element 214 is changed to the high-resistance state when a positive voltage is applied to the third wire 221 on the basis of the second wire 211 .
  • the direction in which a current for attaining the high-resistance state flows from the upper side to the lower side or from the lower side to the upper side may be different between the resistance variable element 204 and the resistance variable element 214 .
  • FIGS. 15 to 18 are process step views showing the manufacturing method of the nonvolatile memory device 40 of this embodiment.
  • FIG. 15( a ) is a view showing a step of forming the first wires and the first conductive layer on the substrate
  • FIG. 15( b ) is a view showing a step of forming the first interlayer insulating layer, the through-holes and the first resistance variable layers
  • FIG. 15( c ) is a view showing a step of filling a material of the second resistance variable layers
  • FIG. 15( d ) is a view showing a step of forming the first intermediate electrodes
  • FIG. 15( e ) is a view showing a step of forming the first contact plugs.
  • FIG. 16( a ) is a view showing a step of forming the first semiconductor layer, the second conductive layer, the second wires and the third conductive layer
  • FIG. 16( b ) is a view showing a step of forming the second interlayer insulating layer, the through-holes and the third resistance variable layers
  • FIG. 16( c ) is a view showing a step of filling a material of the fourth resistance variable layers.
  • FIG. 17( a ) is a view showing a step of forming the second intermediate electrodes
  • FIG. 17( b ) is a view showing a step of forming the second contact plugs
  • FIG. 17( c ) is a view showing a step of forming the second semiconductor layer, the fourth conductive layer and the third wires.
  • FIG. 18( a ) is a view showing a step of forming the third interlayer insulating layer, the third contact plugs 223 and the fourth contact plugs
  • FIG. 18( b ) is a view showing a step of forming the first lead-out wires 225 and the second lead-out wires 226 .
  • the material (copper) of the first wires 201 and the material (platinum) of the first conductive layer 202 are stacked together in this order over the substrate 200 provided with transistors and lower wires, and are patterned using a desired mask, thereby forming the first wires 201 and the first conductive layers 202 .
  • the first interlayer insulating layer 203 is formed over the entire surface of the substrate 200 to cover the first wires 201 and the first conductive layers 202 .
  • the through-holes (holes) are formed to penetrate the first interlayer insulating layer 203 and reach the first conductive layers 202 .
  • Oxygen-deficient tantalum oxide with high oxygen content is deposited on the first conductive layers 202 exposed at the bottom of the through-holes, respectively, by sputtering, to form the first resistance variable layers 205 b (An unnecessary portion of resistance variable layer deposited on the first interlayer insulating layer 203 is removed by CMP).
  • first intermediate electrodes 206 comprising tantalum nitride are filled into the recesses formed on the second resistance variable layers 205 a , respectively, by sputtering (an unnecessary portion of tantalum nitride deposited on the first interlayer insulating layer 203 is removed by CMP).
  • the contact holes are formed to penetrate the first interlayer insulating layer 203 and reach the first conductive layers 202 .
  • the contact holes are filled with tungsten, to form the first contact plugs 207 .
  • the material (silicon or silicon nitride) of the first semiconductor layer 209 , the material (tungsten) of the second conductive layer 210 , the material (copper) of the second wires 211 , and the material (platinum) of the third conductive layer 212 are formed in this order over the first interlayer insulating layer 203 .
  • patterning is performed using a desired mask in such a manner that the upper end surfaces of the first intermediate electrodes 206 are covered and the upper end surfaces of the first contact plugs 207 are exposed.
  • the patterning is performed so that the second wires 211 cross the first wires 201 perpendicularly to the first wires 201 when viewed in the thickness direction.
  • the first semiconductor layers 209 , the second conductive layers 210 , the second wires 211 and the third conductive layers 212 are completed.
  • the second interlayer insulating layer 213 is formed over the entire surface of the first interlayer insulating layer 203 to cover the first semiconductor layers 209 , the second conductive layers 210 , the second wires 211 and the third conductive layers 212 .
  • the through-holes (holes) are formed to penetrate the second interlayer insulating layer 213 and reach the third conductive layers 212 .
  • Oxygen-deficient tantalum oxide with high oxygen content is deposited on the third conductive layers 212 exposed at the bottom of the through-holes, respectively, by sputtering, to form the third resistance variable layers 215 b (an unnecessary portion of resistance variable layer deposited on the second interlayer insulating layer 213 are removed by CMP).
  • the second intermediate electrodes a portion of the oxygen-deficient tantalum oxide with low oxygen content is removed by etching, completing the fourth resistance variable layers 215 a .
  • the second intermediate electrodes 216 comprising tantalum nitride are filled into the recesses formed on the fourth resistance variable layers 215 a , respectively, by sputtering (an unnecessary portion of tantalum nitride deposited on the second interlayer insulating layer 213 is removed by CMP).
  • contact holes are formed to penetrate the second interlayer insulating layer 213 and reach the third conductive layers 212 .
  • the contact holes are filled with tungsten to form the second contact plugs 217 .
  • the material (silicon or silicon nitride) of the second semiconductor layer 219 , the material (tungsten) of the fourth conductive layer 220 and the material (copper) of the third wires 221 are formed in this order over the second interlayer insulating layer 213 .
  • patterning is performed using a desired mask so as to cover the upper end surfaces of the second intermediate electrodes 216 and expose the upper end surfaces of the second contact plugs 217 .
  • the patterning is performed so that the third wires 221 cross the second wires 211 perpendicularly to the second wires 211 , respectively, when viewed in the thickness direction.
  • the third interlayer insulating layer 222 is formed over the entire surface of the second interlayer insulating layer 213 to cover the second semiconductor layers 219 , the fourth conductive layers 220 and the third wires 221 .
  • the contact holes (holes) are formed to penetrate the third interlayer insulating layer 222 and reach the upper end surfaces of the second contact plugs 217 and the upper end surfaces of the third wires 221 .
  • the contact holes are each filled with tungsten, thereby forming the third contact plugs 223 and the fourth contact plugs 224 (an unnecessary portion of tungsten deposited on the third interlayer insulating layer 222 is removed by CMP).
  • the lead-out wires 225 and the lead-out wires 226 are patterned using a desired mask on the third interlayer insulating layer 222 such that the lead-out wire 225 and the lead-out wire 226 cover the upper end surface of the fourth contact plugs 224 and the upper end surface of the third contact plugs 223 , respectively.
  • a nonvolatile memory element and a nonvolatile memory device of the present invention are useful as a resistance variable nonvolatile memory element and a resistance variable nonvolatile memory device which can perform a resistance changing operation stably and can reduce a sneak current in a cross-point memory.

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Publication number Priority date Publication date Assignee Title
US20100258779A1 (en) * 2007-11-29 2010-10-14 Takumi Mikawa Nonvolatile memory device and manufacturing mehtod thereof
US20130016557A1 (en) * 2010-04-05 2013-01-17 Mosaid Technologies Incorporated Semiconductor memory device having a three-dimensional structure
US20140098595A1 (en) * 2012-03-29 2014-04-10 Panasonic Corporation Non-volatile memory device
US20140138607A1 (en) * 2012-10-15 2014-05-22 Panasonic Corporation Non-volatile memory device and manufacturing method thereof
US8952470B2 (en) 2012-09-10 2015-02-10 James John Lupino Low cost high density nonvolatile memory array device employing thin film transistors and back to back Schottky diodes
US9042158B2 (en) 2013-05-21 2015-05-26 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with protective resistance film
US9105332B2 (en) 2012-03-15 2015-08-11 Panasonic Intellectual Property Management Co., Ltd. Variable resistance nonvolatile memory device
US9142292B2 (en) 2011-02-02 2015-09-22 Panasonic Intellectual Property Management Co., Ltd. Method for reading data from nonvolatile storage element, and nonvolatile storage device
US20160086661A1 (en) * 2011-03-24 2016-03-24 Kabushiki Kaisha Toshiba Semiconductor memory device
US9530822B2 (en) 2013-04-28 2016-12-27 Alexander Mikhailovich Shukh High density nonvolatile memory
US20170330915A1 (en) * 2016-05-10 2017-11-16 Winbond Electronics Corp. Resistive random access memory
US9853053B2 (en) 2012-09-10 2017-12-26 3B Technologies, Inc. Three dimension integrated circuits employing thin film transistors
US10475815B2 (en) 2013-09-09 2019-11-12 Tacho Holdings, Llc Three dimension integrated circuits employing thin film transistors
US20230284462A1 (en) * 2022-03-01 2023-09-07 International Business Machines Corporation Resistive random-access memory random number generator
US11765910B2 (en) 2019-11-12 2023-09-19 Imec Vzw Bipolar selector device for a memory array

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011040112A (ja) * 2009-08-06 2011-02-24 Toshiba Corp 不揮発性半導体記憶装置
JP5232935B2 (ja) * 2010-06-21 2013-07-10 パナソニック株式会社 抵抗変化素子の製造方法
US8618526B2 (en) 2010-08-17 2013-12-31 Panasonic Corporation Nonvolatile memory device and manufacturing method thereof
CN103098252B (zh) * 2010-09-17 2014-11-12 松下电器产业株式会社 电流控制元件和使用其的非易失性存储元件
US20130140515A1 (en) * 2011-02-23 2013-06-06 Yoshio Kawashima Nonvolatile memory element and method of manufacturing the same
US9343672B2 (en) * 2011-06-07 2016-05-17 Samsung Electronics Co., Ltd. Nonvolatile memory devices, nonvolatile memory cells and methods of manufacturing nonvolatile memory devices
JP2013004655A (ja) * 2011-06-15 2013-01-07 Sharp Corp 不揮発性半導体記憶装置およびその製造方法
CN103238214B (zh) * 2011-12-02 2015-10-21 松下电器产业株式会社 交叉点型电阻变化非易失性存储装置
AU2013249127B2 (en) * 2012-04-19 2017-02-16 Carnegie Mellon University A metal-semiconductor-metal (MSM) heterojunction diode
US8804402B2 (en) * 2012-08-31 2014-08-12 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device
CN105518892A (zh) * 2013-09-09 2016-04-20 J·J·卢皮诺 采用薄膜晶体管和肖特基二极管的非易失性存储器装置
JP6717192B2 (ja) * 2014-06-25 2020-07-01 日本電気株式会社 半導体装置、および半導体装置の製造方法
US9425390B2 (en) * 2014-10-16 2016-08-23 Micron Technology, Inc. Select device for memory cell applications
US9679945B2 (en) * 2015-09-04 2017-06-13 Kabushiki Kaisha Toshiba Semiconductor memory device and method for manufacturing the same
US10658030B2 (en) * 2017-11-29 2020-05-19 International Business Machines Corporation Synaptic crossbar memory array
CN108630810B (zh) * 2018-05-14 2022-07-19 中国科学院微电子研究所 1s1r存储器集成结构及其制备方法

Citations (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203098A (ja) 2005-01-24 2006-08-03 Sharp Corp 不揮発性半導体記憶装置
JP2006311910A (ja) 2005-05-09 2006-11-16 Shunji Kondo 簡易型消火器具
US20070015348A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Crosspoint resistor memory device with back-to-back Schottky diodes
US20070015329A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Metal/ZnOx/metal current limiter
US20070015330A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Metal/semiconductor/metal (MSM) back-to-back Schottky diode
JP2007158325A (ja) 2005-12-07 2007-06-21 Sharp Corp 双方向ショットキーダイオードを備えるクロスポイント型抵抗メモリ装置
US20070165442A1 (en) 2006-01-13 2007-07-19 Yasunari Hosoi Nonvolatile semiconductor memory device
JP2007267584A (ja) 2006-03-28 2007-10-11 Samsung Kwangju Electronics Co Ltd 安全回路を有する充電装置及びその充電方法
JP2007311772A (ja) 2006-05-17 2007-11-29 Sharp Corp 金属／半導体／金属の積層構造を有する双方向ショットキーダイオード及びその形成方法
US20080025072A1 (en) 2006-07-28 2008-01-31 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device
WO2008047530A1 (en) 2006-10-16 2008-04-24 Panasonic Corporation Non-volatile storage device and method for manufacturing the same
WO2008059701A1 (ja) 2006-11-17 2008-05-22 Panasonic Corporation 不揮発性記憶素子、不揮発性記憶装置、不揮発性半導体装置、および不揮発性記憶素子の製造方法
WO2008062688A1 (fr) 2006-11-20 2008-05-29 Panasonic Corporation Dispositif de stockage semiconducteur non volatile et son procédé de fabrication
WO2008117494A1 (ja) 2007-03-22 2008-10-02 Panasonic Corporation 記憶素子及び記憶装置
WO2009050861A1 (ja) 2007-10-15 2009-04-23 Panasonic Corporation 不揮発性記憶素子およびその製造方法、並びにその不揮発性記憶素子を用いた不揮発性半導体装置
US7535035B2 (en) * 2004-11-10 2009-05-19 Samsung Electronics Co., Ltd. Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same
US7911824B2 (en) * 2007-08-01 2011-03-22 Panasonic Corporation Nonvolatile memory apparatus
US7916516B2 (en) * 2007-02-23 2011-03-29 Panasonic Corporation Nonvolatile memory apparatus and method for writing data in nonvolatile memory apparatus
US7920402B2 (en) * 2006-11-17 2011-04-05 Panasonic Corporation Resistance variable memory apparatus

Patent Citations (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7535035B2 (en) * 2004-11-10 2009-05-19 Samsung Electronics Co., Ltd. Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same
JP2006203098A (ja) 2005-01-24 2006-08-03 Sharp Corp 不揮発性半導体記憶装置
US20090052225A1 (en) 2005-01-24 2009-02-26 Hidenori Morimoto Nonvolatile Semiconductor Memory Device
JP2006311910A (ja) 2005-05-09 2006-11-16 Shunji Kondo 簡易型消火器具
US20070284575A1 (en) 2005-07-18 2007-12-13 Sharp Laboratories Of America, Inc. Metal/semiconductor/metal current limiter
US20070015348A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Crosspoint resistor memory device with back-to-back Schottky diodes
US20070015329A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Metal/ZnOx/metal current limiter
US20070015328A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. MSM binary switch memory device
US20070015330A1 (en) 2005-07-18 2007-01-18 Sharp Laboratories Of America, Inc. Metal/semiconductor/metal (MSM) back-to-back Schottky diode
JP2007027755A (ja) 2005-07-18 2007-02-01 Sharp Corp Ｍｓｍバイナリスイッチメモリ素子
US20090032817A1 (en) 2005-07-18 2009-02-05 Tingkai Li Back-To-Back Metal/Semiconductor/Metal (MSM) Schottky Diode
US20080006814A1 (en) 2005-07-18 2008-01-10 Sharp Laboratories Of America, Inc. MSM binary switch memory
JP2007158325A (ja) 2005-12-07 2007-06-21 Sharp Corp 双方向ショットキーダイオードを備えるクロスポイント型抵抗メモリ装置
JP2007188603A (ja) 2006-01-13 2007-07-26 Sharp Corp 不揮発性半導体記憶装置
US20070165442A1 (en) 2006-01-13 2007-07-19 Yasunari Hosoi Nonvolatile semiconductor memory device
JP2007267584A (ja) 2006-03-28 2007-10-11 Samsung Kwangju Electronics Co Ltd 安全回路を有する充電装置及びその充電方法
JP2007311772A (ja) 2006-05-17 2007-11-29 Sharp Corp 金属／半導体／金属の積層構造を有する双方向ショットキーダイオード及びその形成方法
US20080025072A1 (en) 2006-07-28 2008-01-31 Sharp Kabushiki Kaisha Nonvolatile semiconductor memory device
JP2008034033A (ja) 2006-07-28 2008-02-14 Sharp Corp 不揮発性半導体記憶装置
WO2008047530A1 (en) 2006-10-16 2008-04-24 Panasonic Corporation Non-volatile storage device and method for manufacturing the same
US20090321711A1 (en) 2006-10-16 2009-12-31 Takeshi Takagi Nonvolatile memory element and manufacturing method thereof
WO2008059701A1 (ja) 2006-11-17 2008-05-22 Panasonic Corporation 不揮発性記憶素子、不揮発性記憶装置、不揮発性半導体装置、および不揮発性記憶素子の製造方法
US20090224224A1 (en) 2006-11-17 2009-09-10 Satoru Fujii Nonvolatile memory element, nonvolatile memory apparatus, nonvolatile semiconductor apparatus, and method of manufacturing nonvolatile memory element
US7920402B2 (en) * 2006-11-17 2011-04-05 Panasonic Corporation Resistance variable memory apparatus
WO2008062688A1 (fr) 2006-11-20 2008-05-29 Panasonic Corporation Dispositif de stockage semiconducteur non volatile et son procédé de fabrication
US20100032641A1 (en) 2006-11-20 2010-02-11 Takumi Mikawa Nonvolatile semiconductor memory apparatus and manufacturing method thereof
US7916516B2 (en) * 2007-02-23 2011-03-29 Panasonic Corporation Nonvolatile memory apparatus and method for writing data in nonvolatile memory apparatus
WO2008117494A1 (ja) 2007-03-22 2008-10-02 Panasonic Corporation 記憶素子及び記憶装置
EP2128901A1 (en) 2007-03-22 2009-12-02 Panasonic Corporation Storage element and storage device
US7911824B2 (en) * 2007-08-01 2011-03-22 Panasonic Corporation Nonvolatile memory apparatus
WO2009050861A1 (ja) 2007-10-15 2009-04-23 Panasonic Corporation 不揮発性記憶素子およびその製造方法、並びにその不揮発性記憶素子を用いた不揮発性半導体装置

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8384061B2 (en) * 2007-11-29 2013-02-26 Panasonic Corporation Nonvolatile memory device and manufacturing method
US20100258779A1 (en) * 2007-11-29 2010-10-14 Takumi Mikawa Nonvolatile memory device and manufacturing mehtod thereof
US20130016557A1 (en) * 2010-04-05 2013-01-17 Mosaid Technologies Incorporated Semiconductor memory device having a three-dimensional structure
US9142292B2 (en) 2011-02-02 2015-09-22 Panasonic Intellectual Property Management Co., Ltd. Method for reading data from nonvolatile storage element, and nonvolatile storage device
US9520188B2 (en) * 2011-03-24 2016-12-13 Kabushiki Kaisha Toshiba Semiconductor memory device
US20160086661A1 (en) * 2011-03-24 2016-03-24 Kabushiki Kaisha Toshiba Semiconductor memory device
US9105332B2 (en) 2012-03-15 2015-08-11 Panasonic Intellectual Property Management Co., Ltd. Variable resistance nonvolatile memory device
US20140098595A1 (en) * 2012-03-29 2014-04-10 Panasonic Corporation Non-volatile memory device
US8995170B2 (en) * 2012-03-29 2015-03-31 Panasonic Intellectual Property Management Co., Ltd. Non-volatile memory device
US8952470B2 (en) 2012-09-10 2015-02-10 James John Lupino Low cost high density nonvolatile memory array device employing thin film transistors and back to back Schottky diodes
US9853053B2 (en) 2012-09-10 2017-12-26 3B Technologies, Inc. Three dimension integrated circuits employing thin film transistors
US9006701B2 (en) * 2012-10-15 2015-04-14 Panasonic Intellectual Property Management Co., Ltd. Non-volatile memory device having bit lines and source lines arranged in parallel and manufacturing method thereof
US20140138607A1 (en) * 2012-10-15 2014-05-22 Panasonic Corporation Non-volatile memory device and manufacturing method thereof
US9530822B2 (en) 2013-04-28 2016-12-27 Alexander Mikhailovich Shukh High density nonvolatile memory
US9042158B2 (en) 2013-05-21 2015-05-26 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device with protective resistance film
US10475815B2 (en) 2013-09-09 2019-11-12 Tacho Holdings, Llc Three dimension integrated circuits employing thin film transistors
US20170330915A1 (en) * 2016-05-10 2017-11-16 Winbond Electronics Corp. Resistive random access memory
US10468458B2 (en) * 2016-05-10 2019-11-05 Winbond Electronics Corp. Resistive random access memory having selector and current limiter structures
US11765910B2 (en) 2019-11-12 2023-09-19 Imec Vzw Bipolar selector device for a memory array
US20230284462A1 (en) * 2022-03-01 2023-09-07 International Business Machines Corporation Resistive random-access memory random number generator
US11856798B2 (en) * 2022-03-01 2023-12-26 International Business Machines Corporation Resistive random-access memory random number generator

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