US7919793B2 - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit Download PDF

Info

Publication number
US7919793B2
US7919793B2 US12/588,938 US58893809A US7919793B2 US 7919793 B2 US7919793 B2 US 7919793B2 US 58893809 A US58893809 A US 58893809A US 7919793 B2 US7919793 B2 US 7919793B2
Authority
US
United States
Prior art keywords
cells
gate
cell
gate pad
metallic wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
US12/588,938
Other languages
English (en)
Other versions
US20100187573A1 (en
Inventor
Shusuke Iwata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Assigned to SONY CORPORATION reassignment SONY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: IWATA, SHUSUKE
Publication of US20100187573A1 publication Critical patent/US20100187573A1/en
Application granted granted Critical
Publication of US7919793B2 publication Critical patent/US7919793B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90Masterslice integrated circuits
    • H10D84/903Masterslice integrated circuits comprising field effect technology
    • H10D84/907CMOS gate arrays

Definitions

  • the present invention relates to a semiconductor integrated circuit in which a desired circuit is formed by arranging a plurality of circuit cells (for example standard cells) including a transistor having a gate electrode in combination with each other and interconnecting the cells by a metallic wiring layer.
  • circuit cells for example standard cells
  • gate delay a ratio between delay within a logic circuit element (which delay will hereinafter be referred to as a “gate delay”) and wiring delay is changing greatly.
  • an amount of delay in a circuit part up to a preceding stage connected to each of a plurality of inputs of a certain gate circuit can be estimated with a certain degree of accuracy, it is not possible to estimate timing in consideration of the delay of each input with respect to the operation of the gate circuit and a tolerable amount of delay (delay margin). Estimations of timing in such individual gate circuits are totaled, and timing design is made for correct operation in a whole signal path. However, uncertainty of wiring delay introduces a large error into estimation of timing in the whole signal path.
  • a path delay time estimated by a logic synthesis tool and a path delay time in an actually completed LSI deviate from each other, and erroneous operation, that is, erroneous logical inversion tends to occur.
  • a difficulty in securing a noise margin due to the lowering of voltage also spurs an increase in frequency of erroneous logical inversion.
  • ECOs Engineing Change Orders: requests for a circuit change after design
  • ECOs Engineing Change Orders: requests for a circuit change after design
  • a reserve cell will hereinafter be referred to as an “ECO cell” or an “ECO filler.”
  • ECO cell aided design Such a design method will hereinafter be referred to as an “ECO cell aided design.”
  • a vertical direction and a horizontal direction are standardized into a few types, for example about three types.
  • the size in the so-called vertical direction is referred to as the “height” of standard cells, and the height is standardized or unified into about three types. Because the size (height) of the cells is confused with structural height in a direction perpendicular to a semiconductor substrate and thus causes misunderstanding, the size of the cells will not hereinafter be referred to as “height.” Instead, this size will hereinafter be referred to as a “common cell length” for convenience.
  • a part of an element isolation region and an impurity diffused layer for transistor formation in the above-described reserve cell for dealing with an ECO inherits standard specifications for standard cells.
  • a characteristic defect that does not satisfy a desire of the client is expected at a time of sample evaluation, or the characteristic defect may be found in actual sample evaluation.
  • delay adjustment is made by a reserve cell (ECO cell).
  • ECO cell a reserve cell
  • a buffer or the like changed from an adjacent ECO cell is inserted into a path with too large an amount of delay.
  • Inverters or the like changed from adjacent ECO cells and corresponding in number to a desired amount of additional delay are inserted into a path desired to be provided with an even larger amount of delay.
  • an ECO cell is used for recovery of a logical error.
  • ECO cells are arranged in free spaces after arrangement of standard cells, and thus have limitations in the common cell length direction. It is therefore difficult to freely detour a metallic wiring layer in the common cell length direction.
  • circuit cells such as standard cells, ECO cells and the like not to be easily varied in transistor characteristics.
  • a semiconductor integrated circuit including: a plurality of standard cells including a transistor having a gate electrode and arranged in combination with each other; a metallic wiring layer interconnecting the plurality of standard cells to form a desired circuit; and a plurality of reserve cells having a gate electrode, unconnected with the metallic wiring layer and arranged on a periphery of the plurality of standard cells.
  • each of the gate electrodes of the plurality of standard cells and the plurality of reserve cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad sections of the plurality of reserve cells in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.
  • a requirement that length of the gate pad sections of the reserve cells in the direction orthogonal to the gate finger sections be the predetermined value as described above (however, of course, the length should not exceed a cell size in this direction) is set.
  • wiring intersection with a part of a gate pad section as a bridge line is made possible by a so-called underbridge structure, for example, without detouring the metallic wiring layer to an end side of a gate finger section. That is, this gate pad part has a length equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance, and the metallic wiring layer is made to intersect the central part of the length of the gate pad part.
  • the metallic wiring layer can be connected on both one end side and another end side of the bridge line (a part of the gate pad section).
  • the direction of the length of the gate pad part necessary as such a bridge line is desirably a so-called arbitrary cell length direction.
  • the arbitrary cell length direction in this case is a direction orthogonal to the common cell length direction (predetermined direction) along the gate finger section.
  • the common cell length is standardized into at least one type of length for ease of standard cell design and arrangement.
  • cell length in the arbitrary cell length direction is free from such a regulation.
  • the cell size in the arbitrary cell length direction may be slightly increased by applying the above-described requirement that the length of the gate pad section in the arbitrary cell length direction be the predetermined value or more.
  • a size increase in the arbitrary cell length direction does not involve a disadvantage greater than the size increase, for example a great disadvantage of occurrence of unnecessary spaces as a result of impairing ease of arrangement obtained in cell-based circuit design.
  • the gate pad section is a part for supplying a voltage (signal) to a gate.
  • a voltage signal
  • an electric field is applied to a transistor channel in a nonuniform manner in a direction of length of the gate finger section due to effect of gate resistance.
  • characteristics of the transistors also tend to vary. While an electric field is applied uniformly when the gate pad section is present on both side ends of the gate finger section, cell size in the common cell length direction is increased by an amount corresponding to one gate pad section.
  • two gate finger sections extend from a gate pad section to sides opposite to each other in a predetermined direction (common cell length direction).
  • This constitution remedies a difference in gate resistance, and nonuniformity in the manner of application of an electric field which nonuniformity is caused by the difference in gate resistance.
  • variations in transistor characteristics are reduced without an increase in cell size in the common cell length direction being involved.
  • a semiconductor integrated circuit including: a plurality of circuit cells including a transistor and arranged in combination with each other; and a metallic wiring layer interconnecting the plurality of circuit cells to form a desired circuit.
  • a gate electrode of the transistor within the plurality of circuit cells has a gate pad section and two gate finger sections extending from the gate pad section to sides opposite to each other in a predetermined direction, and length of the gate pad section in at least one of the plurality of circuit cells forming the desired circuit in a direction orthogonal to the predetermined direction is equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.
  • the application of a requirement that the length of the gate pad section in the so-called arbitrary cell length direction be equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance is not limited to reserve cells. That is, a gate pad may be formed in so-called standard cells so as to satisfy the maximum length requirement enabling such an underbridge structure.
  • circuit cells is used as a concept including reserve cells and standard cells.
  • the present invention it is possible to provide a semiconductor integrated circuit that can increase a degree of freedom of wiring without increasing the number of layers of metallic wiring and size in the common cell length direction and which has circuit cells in a pattern not easily affected by variations in transistor characteristics.
  • FIG. 1A is a diagram schematically showing the plane of an integrated circuit according to an embodiment with attention directed to a cell arrangement
  • FIG. 1B is a plan view of an example of constitution of an ECO cell according to the embodiment
  • FIG. 1C is an enlarged view of a gate pad section
  • FIG. 2 is a plan view of an inverter shown as an example after wiring in the ECO cell according to the embodiment
  • FIG. 3A is a plan view of an ECO cell according to a comparative example
  • FIG. 3B is a plan view of an inverter after wiring in the ECO cell according to the comparative example
  • FIG. 3C is a plan view of a NAND gate circuit shown as an example of wiring of another comparative example
  • FIG. 4 is a plan view of another example of wiring of a comparative example
  • FIG. 5 is a plan view of another example of wiring of a comparative example
  • FIG. 6 is a plan view of another example of wiring of a comparative example
  • FIG. 7 is a plan view of an example of wiring to which the present invention is applied as opposed to FIGS. 4 to 6 ;
  • FIG. 8 is a flowchart describing the procedure of a design method in the embodiment.
  • FIG. 9 is a plan view immediately after arrangement of standard cells.
  • FIGS. 10A and 10B are schematic sectional views of an integrated circuit showing a well structure.
  • FIG. 1A is a diagram schematically showing the plane of an integrated circuit according to the embodiment with attention directed to a cell arrangement.
  • Standard cells SC are standard cells.
  • Standard cells SC are functional circuit cells of an inverter, a NAND gate and the like, which are designed in advance, standardized, and registered in a library.
  • Standard cells SC are a set of data, but may refer to a part of a device manufactured on the basis of the data.
  • standard cells registered in a library are combined and arranged.
  • the arrangement substantially connects a power supply voltage line and a reference voltage line (for example a GND line) to each other on data.
  • a desired circuit is obtained by connecting signal lines and the like after the arrangement.
  • the arrangement and wiring up to this point is operation on data by a design aiding device.
  • FIG. 1A is a schematic plan view directing attention to the cell arrangement of the semiconductor integrated circuit.
  • FIG. 1A is used also as a diagram of cell arrangement on data.
  • a desired circuit is realized by combining and arranging standard cells SC of various sizes.
  • the desired circuit in this case can be realized arbitrarily according to the nature of the functional circuits of the individual standard cells SC and the combination of the standard cells SC as long as the desired circuit is a logic circuit.
  • FIG. 1A is a generalized diagram, and the nature of the desired circuit itself is arbitrary.
  • a standard cell design system is used in design of an ASIC (Application Specific Integrated Circuit), an ASSP (Application Specific Standard Product) and the like.
  • An ASIC is an IC developed and manufactured for a specialized use of each client.
  • An ASSP is an IC developed and manufactured as a general-purpose part for a plurality of clients.
  • the standard cell SC is generally standardized or unified in cell length in a direction along one of two sides orthogonal to each other.
  • This cell length direction will hereinafter be referred to as a “common cell length direction.”
  • the size in the common cell length direction is not limited to one type, but may be a few types, for example three types when the whole IC is viewed. However, as viewed locally as in one circuit block, the common cell length is one uniform length. In FIG. 1A , the same cell size is set in the vertical direction of the paper surface of FIG. 1A , and thus this direction is the common cell length direction.
  • the cell size can be determined arbitrarily in a direction orthogonal to the common cell length direction. However, a size that can be taken discretely (specified by a grid number) though arbitrary is generally determined due to requests for design efficiency and consistency.
  • the direction orthogonal to the common cell length direction will hereinafter be referred to as an “arbitrary cell length direction.”
  • ECO FILLER ECO cells
  • the ECO cells have the same size as the standard cells SC in the common cell length direction. While the ECO cells have the same cell size in FIG. 1A , the ECO cells can take a few types of cell sizes in the arbitrary cell length direction.
  • the ECO cells are different from the standard cells SC in degree of contribution to the desired circuit.
  • the standard cells SC themselves form the desired circuit.
  • the ECO cells are arranged as “reserve cells” that do not normally form the desired circuit.
  • FIG. 1B shows an example of configuration of an ECO cell.
  • FIG. 1B is a diagram of layout of an ECO cell for realizing a most basic gate circuit such as an inverter, a NAND gate or the like.
  • a semiconductor substrate of the ECO cell shown in FIG. 1B has an N-type well (hereinafter referred to as an N-well) 10 N for forming a PMOS transistor and a P-type well (hereinafter referred to as a P-well) 10 P for forming an NMOS transistor.
  • the N-well 10 N and the P-well 10 P are formed so as to be separated from each other in the common cell length direction within the semiconductor substrate.
  • impurity diffused layers ( 11 P and 11 N) forming a source region and a drain region or the like to be described later, for example, are formed inside the pattern of the N-well 10 N and the P-well 10 P.
  • a well-in-well structure, or a triple well structure, for example, may be employed. Apart from whether the well-in-well structure is employed, the N-well 10 N and the P-well 10 P in FIG.
  • 1B represent two substrate regions where no element isolation region is formed, and indicate that an N-type impurity layer or a part of the N-type impurity layer is formed on one side of the two substrate regions, and that a P-type impurity layer or a part of the P-type impurity layer is formed on the other side.
  • the N-well 10 N in the upper part of the paper surface of FIG. 1B in the common cell length direction will be referred to as a “PMOS formation region.”
  • the P-well 10 P in the lower region of the paper surface of FIG. 1B will be referred to as an “NMOS formation region.”
  • Two gate electrodes 20 A and 20 B composed of a gate metal layer GM are formed.
  • the gate metal layer GM in this case has for example a structure of a polysilicon single layer or a multilayer structure of polysilicon and a high melting point metal.
  • the gate electrodes 20 A and 20 B are formed simultaneously by processing the gate metal layer GM into a predetermined pattern by photolithography and etching.
  • Each of the gate electrodes 20 A and 20 B has a pattern in which one gate pad section and two gate finger sections are formed integrally.
  • the gate electrode 20 A has a gate pad section 21 A disposed around a boundary between the PMOS formation region 10 N and the NMOS formation region 10 P.
  • the gate pad section 21 A has a pattern in an L-shaped form in which a metallic wiring intersecting section 211 that is long and narrow in the arbitrary cell length direction and a trunk section 212 are formed integrally.
  • the gate electrode 20 A has a gate finger section 22 A extending from an end side of the trunk section 212 so as to intersect the P-type diffused layer 11 P.
  • the gate electrode 20 A has a gate finger section 23 A extending from the middle of a longer side of the metallic wiring intersecting section 211 so as to intersect the N-type diffused layer 11 N.
  • the width of the gate finger sections 22 A and 23 A defines the so-called gate length of the transistors.
  • the length of a part of the gate finger section 22 A which part intersects the P-type diffused layer 11 P defines the so-called gate width of the PMOS transistor.
  • the length of a part of the gate finger section 23 A which part intersects the N-type diffused layer 11 N defines the so-called gate width of the NMOS transistor.
  • the gate electrode 20 B has a gate pad section 21 B disposed around the boundary between the PMOS formation region 10 N and the NMOS formation region 10 P.
  • the gate pad section 21 B desirably has a pattern in an L-shaped form in which a metallic wiring intersecting section 211 and a trunk section 212 are formed integrally.
  • the gate pad section 21 B is disposed in the vicinity of the gate pad section 21 A.
  • the gate pad sections 21 A and 21 B are disposed in the vicinity of each other such that the L-shapes of the gate pad sections 21 A and 21 B are combined with each other and the gate pad sections 21 A and 21 B as a whole are contained in a rectangular region.
  • Such an arrangement in which the L-shapes of the gate pad sections 21 A and 21 B are combined with each other and the gate pad sections 21 A and 21 B are contained in a rectangular region is not essential. However, when the gate pad sections have an L-shape, such a combination arrangement saves the entire arrangement area most, and is desirable in that sense.
  • the gate pad section 21 B has the pattern of a figure obtained by rotating the gate pad section 21 A by 180 degrees.
  • the gate electrode 20 B has a gate finger section 22 B extending from the middle of a longer side of the metallic wiring intersecting section 211 in the gate pad section 21 B so as to intersect the P-type diffused layer 11 P.
  • the gate electrode 20 B has a gate finger section 23 B extending from an end side of the trunk section 212 so as to intersect the N-type diffused layer 11 N.
  • the width of the gate finger sections 22 B and 23 B defines the so-called gate length of the transistors.
  • the length of a part of the gate finger section 22 B which part intersects the P-type diffused layer 11 P defines the so-called gate width of the PMOS transistor.
  • the length of a part of the gate finger section 23 B which part intersects the N-type diffused layer 11 N defines the so-called gate width of the NMOS transistor.
  • the gate pad sections 21 A and 21 B each have a predetermined length L in the arbitrary cell length direction.
  • the “length in the arbitrary cell length direction” refers to the size of a largest part in the direction.
  • the predetermined length L assumes a value satisfying a requirement that the predetermined length L be “equal to or more than a sum total value of three times a minimum line width in a metallic wiring layer and twice a minimum separation distance.”
  • an upper limit of the predetermined length L is the cell size in the arbitrary cell length direction. Contents signifying this requirement are clear when connections in the metallic wiring layer are necessary, and will thus be described later in the section of examples of wiring of ECO cells.
  • the shapes of the gate pad sections 21 A and 21 B are arbitrary, and do not need to be the L-shape.
  • ECO cells ECO FILLER
  • delay adjustment may be needed simultaneously.
  • connection of the metallic wiring layer is made in ECO cells at necessary positions only in the above-described cases where the ECO cells are necessary.
  • FIG. 2 shows an example of wiring of the ECO cell when an inverter allowing input to be taken from either of a left side and a right side of the paper surface is realized.
  • the layout of the ECO cell shown in FIG. 2 is made by adding the layout of contacts (1st contacts: 1 C) in a first layer provided in a first interlayer insulating film not shown in the figure and a metallic wiring layer of a first layer (first wiring layer: 1 M) to the ground layout of FIG. 1B .
  • gate finger sections of the gate electrode 20 A and the gate electrode 20 B divide the P-type diffused layer 11 P into three parts.
  • the wide central part of the three diffused layer parts of the P-type diffused layer 11 P is connected via a 1st contact 41 ( 1 C) to a branch part of a power supply voltage supplying line VDD formed of the first wiring layer ( 1 M) over the 1st contact 41 .
  • a trunk line of the power supply voltage supplying line VDD is disposed in the arbitrary cell length direction along a cell boundary.
  • the other gate finger sections of the gate electrode 20 A and the gate electrode 20 B divide the N-type diffused layer 11 N into three parts.
  • the wide central part of the three diffused layer parts of the N-type diffused layer 11 N is connected via a 1st contact 42 ( 1 C) to a branch part of a reference voltage supplying line VSS formed of the first wiring layer ( 1 M) over the 1st contact 42 .
  • a trunk line of the reference voltage supplying line VSS is disposed in the arbitrary cell length direction along a cell boundary on an opposite side from the power supply voltage supplying line VDD.
  • a PMOS transistor is formed which has the gate finger section 22 A of the gate electrode 20 A intersecting the P-type diffused layer 11 P as a gate.
  • the source region of the PMOS transistor is formed in the P-type diffused layer part connected to the 1st contact 41 ( 1 C).
  • the P-type diffused layer part on an opposite side from the P-type diffused layer part connected to the 1st contact 41 ( 1 C) with the gate finger section 22 A interposed between the P-type diffused layer parts forms the drain region of the PMOS transistor.
  • Two 1st contacts 43 ( 1 C) and 44 ( 1 C) are formed on the drain region of the PMOS transistor.
  • An NMOS transistor is formed which has the gate finger section 23 A of the gate electrode 20 A intersecting the N-type diffused layer 11 N as a gate.
  • the source region of the NMOS transistor is formed in the N-type diffused layer part connected to the 1st contact 42 ( 1 C).
  • the N-type diffused layer part on an opposite side from the N-type diffused layer part connected to the 1st contact 42 ( 1 C) with the gate finger section 23 A interposed between the N-type diffused layer parts forms the drain region of the NMOS transistor.
  • One 1st contact 45 ( 1 C) is formed on the drain region of the NMOS transistor.
  • the gate pad section 21 A is provided as a gate part having a role of connecting the gates of the PMOS transistor and the NMOS transistor and a role of a contact (landing) pad.
  • a 1st contact 46 ( 1 C) is formed near one end part of the metallic wiring intersecting section 211 of the gate pad section 21 A.
  • a first input line 31 ( 1 M) is connected to the 1st contact 46 ( 1 C).
  • a 1st contact 47 ( 1 C) is formed on a side near another end part of the metallic wiring intersecting section 211 .
  • a second input line 32 ( 1 M) is connected to the 1st contact 47 ( 1 C).
  • the first input line 31 ( 1 M) and the second input line 32 ( 1 M) may be provided alternatively according to on which side in the arbitrary cell length direction (on which of the left side and the right side of the paper surface of FIG. 2 ) a gate circuit in a stage preceding the inverter is disposed.
  • the second input line 32 ( 1 M) may be used to branch into a path in which a signal from the first input line 31 is passed through the ECO cell (inverter) shown in FIG. 2 and then output and a path in which the signal is not passed through the ECO cell (inverter).
  • the metallic wiring intersecting section 211 is formed in the shape of a strip long in the arbitrary cell length direction for a purpose of widening a region between the two 1st contacts 46 ( 1 C) and 47 ( 1 C).
  • a drain connecting line 33 ( 1 M) as a kind of internal connecting line is disposed between the two 1st contacts 46 ( 1 C) and 47 ( 1 C) so as to be orthogonal to the metallic wiring intersecting section 211 .
  • One end part side of the drain connecting line 33 ( 1 M) is connected to the drain region of the PMOS transistor via the 1st contacts 43 ( 1 C) and 44 ( 1 C).
  • Another end part side of the drain connecting line 33 ( 1 M) is connected to the drain region of the NMOS transistor via the 1st contact 45 ( 1 C).
  • the output can be taken out from the drain connecting line 33 ( 1 M) in either direction (of a left direction and a right direction of the paper surface of FIG. 2 ) in the arbitrary cell length direction.
  • the first wiring layer ( 1 M) can be orthogonal to the vicinity of the central part of the metallic wiring intersecting section 211 , and contacts can be provided on both sides of the orthogonal part.
  • a requirement of a minimum length (reference “L” in FIG. 1C ) of the metallic wiring intersecting section 211 for this is a length where three pieces of wiring and two spaces between the pieces of wiring can be formed supposing that the width of contacts is the same as wiring layer width.
  • a requirement imposed on the metallic wiring intersecting section 211 is to satisfy a condition that the length of the metallic wiring intersecting section 211 in the arbitrary cell length direction be “equal to or more than a sum total value of three times a minimum line width in the metallic wiring layer and twice a minimum separation distance.”
  • FIGS. 3A , 3 B, and 3 C show an ECO cell to which the present invention is not applied as opposed to the ECO cell shown in FIG. 1B and FIG. 2 .
  • FIG. 3A shows the ECO cell when wiring is not connected yet.
  • FIG. 3B and FIG. 3C show the ECO cell after the wiring.
  • FIG. 3B represents a case where an inverter (INV.) cell is realized by the wiring.
  • FIG. 3C represents a case where a NAND cell is realized by the wiring.
  • Gate electrodes 20 C and 20 D shown in FIGS. 3A to 3C have two gate finger sections ( 22 A and 23 A or 22 B and 23 B). These two gate finger sections intersect a P-type diffused layer 11 P and an N-type diffused layer 11 N, respectively.
  • the gate electrodes 20 C and 20 D have the constitution of the gate finger sections in common with the gate electrodes 20 A and 20 B in FIG. 1B and FIG. 2 .
  • the gate electrodes 20 C and 20 D are different from the gate electrodes 20 A and 20 B in the shape of gate pad sections.
  • Gate pad sections 21 C of the gate electrodes 20 C and 20 D in the comparative example have a rectangular shape. This rectangular shape is of such a size as to simply play a role of a contact landing pad.
  • the inverter (INV.) shown in FIG. 3B does not use a gate on a right side, which fact itself is not essential.
  • the gate pad sections 21 C are of a rectangular shape and of a size without the predetermined length L in the arbitrary cell length direction which length can be intersected by a wiring layer as in FIG. 2 .
  • the position of a wiring layer forming an input (IN) and an output (OUT) are fixed in the arbitrary cell length direction.
  • the input (IN) is fixed for input from the right side of the paper surface
  • the output (OUT) is fixed for output to the left side of the paper surface.
  • the provision of a space for wiring to detour by sacrificing gate width or use of a second wiring layer ( 2 M) as an even higher layer is essential.
  • an output (OUT) can produce output to either of the left and the right.
  • the wiring of the output (OUT) is an obstacle to two inputs, that is, a first input (IN 1 ) and a second input (IN 2 ).
  • the provision of a space for wiring to detour by sacrificing gate width or use of a second wiring layer ( 2 M) as an even higher layer is essential.
  • the provision of a space for wiring to detour by sacrificing gate width or use of a second wiring layer ( 2 M) as an even higher layer is essential.
  • the present embodiment shown in FIG. 2 enables the input and the output to be assigned to the left and the right arbitrarily.
  • a through path in which a signal does not go through the ECO cell can be provided. At this time, it is not necessary to provide a space for wiring to detour by sacrificing gate width. Further, it is not necessary to use a second wiring layer ( 2 M) as an even higher layer.
  • FIG. 7 is a diagram showing the layout of a second example of wiring in the present embodiment.
  • FIGS. 4 to 6 show comparative examples of the second example of wiring.
  • a circuit realized by ECO cells shown in these figures is an example when wiring is more complex.
  • a connection between nodes as indicated by a dashed and dotted line in FIG. 4 needs to be established with as short a wiring length as possible.
  • the comparative example of FIG. 5 uses a metallic wiring layer of an even higher second layer (second wiring layer: 2 M), and thus has a disadvantage of correspondingly increasing manufacturing cost.
  • the comparative example of FIG. 6 has a long connecting line 30 ( 1 M) for forming a detour route instead of using the second wiring layer ( 2 M).
  • the detour route in this case is possible only in a case of standard cells SC in a block that is large in the common cell length direction and which has a margin for wiring.
  • the second example of wiring to which the present invention is applied as in FIG. 7 has a shorter connecting line 31 ( 1 M) for forming a detour route than the connecting line 30 ( 1 M) in FIG. 6 .
  • a contact for the connecting line 31 is provided at an end part of a metallic wiring intersecting section 211 (GM) of a gate pad section.
  • GM metallic wiring intersecting section 211
  • the present invention can be carried out to optimize the ease of wiring by examples of application of the invention.
  • a request for a circuit change after design occurs in a stage of sample evaluation within an own company or by a client. Because a large amount of additional cost is incurred once a photomask is fabricated and after a product or a sample is fabricated, a design system using the ECO is excellent in that the design system makes a circuit change after the photomask relatively easy.
  • Post Mask ECO is an effective system for recovering an error in timing estimation which error is revealed after LSI trial manufacture or a logical error in a short turnaround time (TAT).
  • FIG. 8 shows a flow of LSI design including a flow of the “Post Mask ECO.”
  • LSI design an architecture design is made in step ST 1 .
  • a register transfer level (RTL) design is made in step ST 2 .
  • a net list (Netlist) 100 is created by a synthesis tool from the RTL in step ST 3 .
  • the net list refers to the data of information on connection between terminals in an electronic circuit.
  • step ST 4 the net list 100 is input to a placement and routing (P&R) tool, and a layout design is made.
  • P&R placement and routing
  • the P&R tool places standard cells in an optimum position from the net list 100 and timing limitations.
  • FIG. 9 shows a state after standard cells SC are placed and wired.
  • a ratio of occurrence of free spaces is said to be generally about 10 percent to 30 percent, though different depending on the use of the LSI or the like.
  • ECO cells (ECO FILLER) are laid over places where the standard cells SC are not placed, as shown in FIG. 1A .
  • the “Post Mask ECO” system provides two kinds of ECO cells, that is, an ECO filler and an ECO logic cell (ECO LOGIC CELL). ECO logic cells shown in the first example of wiring or the second example of wiring described above may be created by wiring ECO fillers. However, for a shorter TAT, the “Post Mask ECO” system registers a logic cell in an anticipated circuit form in a library in advance, and replaces an ECO filler at an occurrence position with the logic cell.
  • ECO fillers have a layout form as shown in FIG. 3A (comparative example) or FIG. 1B (present embodiment).
  • a photomask (Mask) is fabricated in step ST 5 .
  • an LSI is produced on a trial basis using the fabricated photomask.
  • the LSI produced on a trial basis is evaluated in step ST 7 to determine whether a correct output is obtained in response to a predetermined input, whether a correct output is obtained even when an input is intentionally delayed to a certain extent, and whether a correct output is obtained even when there is a frequency variation or a voltage variation, for example.
  • step ST 8 When there is no logical error and there is a sufficient timing margin, it is determined that there is no problem in step ST 8 . The flow proceeds to step ST 9 , where mass production is started.
  • step ST 8 When a problem is detected in step ST 8 , a net list correction is made in step ST 10 , and thus the net list 100 used for placement and routing is rewritten.
  • step ST 8 The layout design by placement and routing, the photomask fabrication, the LSI trial production, and the LSI evaluation in steps ST 4 to ST 7 are performed again.
  • step ST 8 the process proceeds to mass production in step ST 9 .
  • steps ST 4 to ST 8 and step ST 10 are repeated until the problem is solved.
  • an error can be corrected by only making correction in upper layers from 1st contacts ( 1 C).
  • prior evaluation may be performed on a part of LSIs at a time of mass production without trial production as in FIG. 8 being performed. That is, when the TAT is desired to be shortened, a wafer lot (a set of wafers to be processed in one period) at the time of mass production of LSIs in which processing is completed up to gates is set on standby in advance. A part of wafers or an evaluation chip is evaluated with a package assembly as an evaluation sample. When no problem is found in the evaluation, the other wafers of the same wafer lot are manufactured and mass-produced.
  • a first advantage is that wiring is possible without sacrificing the gate width of transistors even when common cell length (so-called cell height) is small.
  • the cell height (cell size in the common cell length direction) of ECO cells included in an ASIC, an ASSP and the like based on standard cells needs to coincide with that of the standard cells SC.
  • the height (cell size in the common cell length direction) of standard cells SC has been decreasing.
  • the layout design of ECO cells is becoming difficult.
  • a second advantage is excellent compatibility with pad arrangements for suppressing variations in transistor characteristics.
  • GM gate metal
  • the gate pad sections 21 A and 21 B having the metallic wiring intersecting section 211 facilitate intersections of wiring and the gate metal at the central part of the cell in which part the intersections of the wiring and the gate metal concentrate.
  • the present invention can be suitably applied in combination with the shape of a gate electrode when there is great limitation on the pattern shape of the gate metal (GM) due to a need for disposing a gate pad section around the central part in the common cell length direction.
  • GM gate metal
  • a third advantage is that a metallic wiring layer can be formed by only a minimum of a first wiring layer ( 1 M).
  • a node change occurs in the layout design of standard cells SC.
  • the layout design is made with (GM+ 1 M) or (GM+ 1 M+ 2 M: second wiring layer).
  • (GM+ 1 M+ 2 M) uses more metallic wiring layers, and thus increases LSI manufacturing cost.
  • the present embodiment makes it possible to form an underbridge structure by the shape of the metallic wiring intersecting section instead of node change using the second wiring layer 2 M.
  • cost can be reduced by an amount corresponding to a small number of wiring layers used.
  • cell size in the arbitrary cell length direction may be increased slightly by applying the present invention.
  • cell expansion in the arbitrary cell length direction is performed into unnecessary regions in most cases, thus not leading to any disadvantage. Even if the cell expansion is disadvantageous, the cell expansion does not disturb arrangement regularity unlike cell expansion in the common cell length direction, and is thus not a great disadvantage.
  • the plane pattern shape of the gate (and impurity diffused layer) can be determined freely, and therefore an underbridge structure can be made relatively easily.
  • the present invention can be applied to either of standard cells and ECO cells. However, for the above-described reasons, the present invention has great effects when applied to ECO cells.
  • the gate pad section 21 A may be of any shape as long as at least the necessary length L shown in FIG. 1C is obtained.
  • combining the L-shapes of two gate pad sections on the left and the right as shown in FIG. 1B makes the entire arrangement efficient, and reduces space.
  • the gate pad section of a gate other than the two gates on both sides preferably maintain the relation of FIG. 1B to another gate pad section disposed on one of the left and the right.
  • the gate pad section of the central gate is formed into a pattern at least partially having an L-shape that can be combined with another gate pad section disposed on either of the left and the right. “At least partially having” in this case is to the effect that a part other than a part having the L-shape does not need to exist and that when the part other than the part having the L-shape exists, the shape of the part other than the part having the L-shape is arbitrary.
  • a gate pad section in an ECO cell is desired to satisfy the requirement of a minimum length L of the gate pad section.
  • FIG. 10A is a schematic sectional view taken along a line X-X in FIG. 1B .
  • FIG. 10B is a schematic sectional view taken along a line Y-Y in FIG. 1B .
  • a semiconductor integrated circuit illustrated in FIG. 10A and FIG. 10B is formed in a P-type semiconductor substrate (P-substrate 1 ) made of P-type silicon or the like.
  • N-well 10 N is formed large and deep within the P-substrate 1 .
  • the N-well 10 N is therefore referred to as a “deep N-well.”
  • a P-well 10 P having a smaller area and a shallower junction than the N-well 10 N is formed within the N-well 10 N.
  • the N-well 10 N shown in FIG. 1B represents a part opened from an element isolation region not shown in the figure in a plane pattern.
  • the P-well 10 P shown in FIG. 1B represents a part opened from an element isolation region not shown in the figure in a plane pattern.

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
US12/588,938 2009-01-23 2009-11-03 Semiconductor integrated circuit Expired - Fee Related US7919793B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009-012955 2009-01-23
JP2009012955A JP5509599B2 (ja) 2009-01-23 2009-01-23 半導体集積回路

Publications (2)

Publication Number Publication Date
US20100187573A1 US20100187573A1 (en) 2010-07-29
US7919793B2 true US7919793B2 (en) 2011-04-05

Family

ID=42353457

Family Applications (1)

Application Number Title Priority Date Filing Date
US12/588,938 Expired - Fee Related US7919793B2 (en) 2009-01-23 2009-11-03 Semiconductor integrated circuit

Country Status (3)

Country Link
US (1) US7919793B2 (enrdf_load_stackoverflow)
JP (1) JP5509599B2 (enrdf_load_stackoverflow)
CN (1) CN101794774B (enrdf_load_stackoverflow)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981494B2 (en) 2011-09-20 2015-03-17 Samsung Electronics Co., Ltd. Eco logic cell and design change method using eco logic cell
US9634026B1 (en) 2016-07-13 2017-04-25 Qualcomm Incorporated Standard cell architecture for reduced leakage current and improved decoupling capacitance
US20170116366A1 (en) * 2015-10-26 2017-04-27 Samsung Electronics Co., Ltd. Engineering change order (eco) cell, layout thereof and integrated circuit including the eco cell
US20180004883A1 (en) * 2016-07-01 2018-01-04 Globalfoundries Inc. Method, apparatus and system for wide metal line for sadp routing
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
US11488948B2 (en) 2020-03-30 2022-11-01 Samsung Electronics Co., Ltd. Semiconductor devices, layout design methods for the same, and methods for fabricating the same
US20230068097A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Base layout cell

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5552775B2 (ja) 2009-08-28 2014-07-16 ソニー株式会社 半導体集積回路
CN102129493B (zh) * 2011-03-02 2013-03-06 福州瑞芯微电子有限公司 数字ic设计流程中实现自动化eco网表的方法
US9831230B2 (en) * 2013-08-13 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell layout, semiconductor device having engineering change order (ECO) cells and method
CN108701653B (zh) * 2016-02-25 2022-07-29 株式会社索思未来 半导体集成电路装置
US11270992B2 (en) * 2019-11-05 2022-03-08 Samsung Electronics Co., Ltd. Semiconductor devices
CN114664725B (zh) * 2020-12-23 2025-07-29 华润微电子(重庆)有限公司 GaN器件互联结构及其制备方法
CN113161346B (zh) * 2021-03-17 2022-04-01 长鑫存储技术有限公司 集成电路及其布局方法
US12205894B2 (en) * 2022-03-17 2025-01-21 Macronix International Co., Ltd. Routing pattern

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369412B1 (en) * 1998-01-29 2002-04-09 Sanyo Electric Co., Ltd. Semiconductor integrated device comprising a plurality of basic cells
US20050044522A1 (en) * 2003-08-21 2005-02-24 Kawasaki Microelectronics, Inc. Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure
JP2006269900A (ja) 2005-03-25 2006-10-05 Yamaha Corp 半導体集積回路の設計方法
US20070111405A1 (en) * 2005-11-15 2007-05-17 Shinji Watanabe Design method for semiconductor integrated circuit
US7562326B2 (en) * 2007-08-09 2009-07-14 United Microelectronics Corp. Method of generating a standard cell layout and transferring the standard cell layout to a substrate

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0828485B2 (ja) * 1988-06-20 1996-03-21 日本電信電話株式会社 相補型misマスタスライスlsiの基本セル
JP3130918B2 (ja) * 1990-10-31 2001-01-31 富士通株式会社 設計変更用セル及びこれを用いたレイアウト方法
JP3060673B2 (ja) * 1991-11-13 2000-07-10 日本電気株式会社 半導体集積回路

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369412B1 (en) * 1998-01-29 2002-04-09 Sanyo Electric Co., Ltd. Semiconductor integrated device comprising a plurality of basic cells
US20050044522A1 (en) * 2003-08-21 2005-02-24 Kawasaki Microelectronics, Inc. Layout method of semiconductor integrated circuit, layout structure thereof, and photomask for forming the layout structure
JP2006269900A (ja) 2005-03-25 2006-10-05 Yamaha Corp 半導体集積回路の設計方法
US20070111405A1 (en) * 2005-11-15 2007-05-17 Shinji Watanabe Design method for semiconductor integrated circuit
US7562326B2 (en) * 2007-08-09 2009-07-14 United Microelectronics Corp. Method of generating a standard cell layout and transferring the standard cell layout to a substrate

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981494B2 (en) 2011-09-20 2015-03-17 Samsung Electronics Co., Ltd. Eco logic cell and design change method using eco logic cell
US20170116366A1 (en) * 2015-10-26 2017-04-27 Samsung Electronics Co., Ltd. Engineering change order (eco) cell, layout thereof and integrated circuit including the eco cell
US10192860B2 (en) * 2015-10-26 2019-01-29 Samsung Electronics Co., Ltd. Engineering change order (ECO) cell, layout thereof and integrated circuit including the ECO cell
US20180004883A1 (en) * 2016-07-01 2018-01-04 Globalfoundries Inc. Method, apparatus and system for wide metal line for sadp routing
US10846452B2 (en) * 2016-07-01 2020-11-24 Globalfoundries Inc. Method, apparatus and system for wide metal line for SADP routing
US11205033B2 (en) * 2016-07-01 2021-12-21 Globalfoundries Inc. Method, apparatus and system for wide metal line for SADP routing
US9634026B1 (en) 2016-07-13 2017-04-25 Qualcomm Incorporated Standard cell architecture for reduced leakage current and improved decoupling capacitance
US11488947B2 (en) 2019-07-29 2022-11-01 Tokyo Electron Limited Highly regular logic design for efficient 3D integration
US11488948B2 (en) 2020-03-30 2022-11-01 Samsung Electronics Co., Ltd. Semiconductor devices, layout design methods for the same, and methods for fabricating the same
US20230068097A1 (en) * 2021-08-27 2023-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Base layout cell
US11868697B2 (en) * 2021-08-27 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd Base layout cell

Also Published As

Publication number Publication date
CN101794774B (zh) 2012-03-21
JP2010171243A (ja) 2010-08-05
US20100187573A1 (en) 2010-07-29
CN101794774A (zh) 2010-08-04
JP5509599B2 (ja) 2014-06-04

Similar Documents

Publication Publication Date Title
US7919793B2 (en) Semiconductor integrated circuit
CN101752368B (zh) 具有可变设计规则的标准单元架构和方法
JP5292005B2 (ja) 半導体集積回路
JP2001339047A (ja) 半導体装置
US20200051977A1 (en) Integrated circuit including multiple-height cell and method of manufacturing the integrated circuit
US10114919B2 (en) Placing and routing method for implementing back bias in FDSOI
CN112310224A (zh) 半导体器件
US7747976B2 (en) Semiconductor cell with power layout not contacting sides of its rectangular boundary and semiconductor circuit utilizing semiconductor cells
US12147750B2 (en) Multiplexer
CN114586152A (zh) 采用euv光刻的标准单元和电网架构
KR20160105263A (ko) 시스템 온 칩 및 이의 레이아웃 설계 방법
US20240363558A1 (en) Integrated circuit device
US11217528B2 (en) Semiconductor structure having buried power rail disposed between two fins and method of making the same
US20120001655A1 (en) Base cell for implementing an engineering change order (eco)
CN117999651A (zh) 用于利用减小的接触栅极多晶硅间距和双高度单元来减小电压降的标准单元设计架构
US11392743B2 (en) Multiplexer
TWI869798B (zh) 解耦合電容器單元、積體電路及其製造方法
US20230290767A1 (en) Semiconductor devices
US12406125B2 (en) Integrated circuit layout including standard cells and method to form the same
JP2011199034A (ja) 半導体装置
US20010045572A1 (en) Semiconductor interated circuit and method of manufacturing the same
JP2002170930A (ja) 半導体装置、その製造方法および記憶媒体
JP2005032768A (ja) 半導体装置
US20240266344A1 (en) Integrated circuit including backside wiring and method of designing the integrated circuit
JP2002016143A (ja) 半導体集積回路およびその設計方法

Legal Events

Date Code Title Description
AS Assignment

Owner name: SONY CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:IWATA, SHUSUKE;REEL/FRAME:023507/0503

Effective date: 20091027

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

LAPS Lapse for failure to pay maintenance fees

Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCH Information on status: patent discontinuation

Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362

FP Lapsed due to failure to pay maintenance fee

Effective date: 20230405