US7880314B2 - Wiring substrate and electronic component mounting structure - Google Patents

Wiring substrate and electronic component mounting structure Download PDF

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Publication number
US7880314B2
US7880314B2 US12/330,946 US33094608A US7880314B2 US 7880314 B2 US7880314 B2 US 7880314B2 US 33094608 A US33094608 A US 33094608A US 7880314 B2 US7880314 B2 US 7880314B2
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solder resist
conductive pattern
interval group
conductive patterns
rectangle portion
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US20090152716A1 (en
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Tsuyoshi Sohara
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD. reassignment SHINKO ELECTRIC INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SOHARA, TSUYOSHI
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0616—Random array, i.e. array with no symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/0989—Coating free areas, e.g. areas other than pads or lands free of solder resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a wiring substrate on which an electronic component is flip-chip bonded and an electronic component mounting structure.
  • an underfill resin 112 is filled in a clearance between a surface of the wiring substrate 100 and the semiconductor element 102 .
  • the conductive patterns 106 , 106 are formed on the mounting surface of the wiring substrate 100 so as to be exposed at a position where the tip ends of the bumps 104 , 104 of the semiconductor device 102 as shown in FIG. 7 .
  • a wide portion 106 a of which width is wider than other portions is formed in a middle portion of the conductive pattern 106 .
  • the tip end of the bump 104 of the semiconductor device 102 comes into contact with the wide portion 106 a.
  • solder resists 114 , 116 Both ends of the conductive pattern 106 , 106 are covered with solder resists 114 , 116 .
  • Japanese Patent Unexamined Publications JP-A-11-186322 and JP-A-2000-77471 proposes following bonding methods.
  • solder powders are applied to whole exposed surfaces of the conductive patterns 106 , 106 , then the solder powders are fused to cover the wide portion 106 a of the conductive pattern 106 with fused solder, and then the tip end of the bump 104 of the semiconductor element 102 is brought into contact with the wide portions 106 a of the conductive patterns 106 .
  • the solder 108 covering whole exposed surfaces of the conductive patterns 106 gathers around peripheral surfaces of the bumps 104 respectively due to a surface tension, then, the gathered solder becomes solidified and joins together the bumps 104 and the conductive patterns 106 .
  • the solder that covers whole exposed surfaces of the conductive patterns 106 can be utilized in joining the bumps 104 of the semiconductor element 102 and the conductive patterns 106 . Thus, both can be connected electrically without fail.
  • the conductive patterns 106 , 106 exposed on the mounting surface of the wiring substrate 100 are formed sometimes such that, as shown in FIG. 8 , the interval between adjacent conductive patterns 106 , 106 becomes narrow or wide depending upon the relationship to the electrode terminals 102 a, 102 a of the mounted semiconductor element 102 .
  • the inventor of the present invention has found the fact that an amount of brazing metal that covers exposed surfaces of adjacent conductive patterns must be adjusted and thus an amount of the brazing metal can be adjusted easily by adjusting an exposed length of the conductive pattern, and has arrived at the present invention.
  • a wiring substrate on which an electronic component is flip-chip bonded including:
  • solder resist which is formed on the substrate main body and having an opening
  • the conductive patterns include a narrow interval group and a wide interval group, an interval between the adjacent conductive patterns belonging to the narrow interval group being narrower than an interval between the adjacent conductive patterns belonging to the wide interval group, and
  • an exposure length of the conductive patterns of the narrow interval group is shorter than an exposure length of the conductive patterns of the wide interval group.
  • an electronic component mounting structure including:
  • solder resist which is formed on the substrate and having an opening
  • the conductive patterns include a narrow interval group and a wide interval group, an interval between the adjacent conductive patterns belonging to the narrow interval group being narrower than an interval between the adjacent conductive patterns belonging to the wide interval group,
  • an exposure length of the conductive patterns of the narrow interval group is shorter than an exposure length of the conductive patterns of the wide interval group
  • each of the bumps are flip-chip bonded to the respective exposure surface of the conductive pattern by brazing metal.
  • both ends of the conductive patterns may be covered with the solder resist, and the exposure length of the conductive pattern may be adjusted by the solder resist.
  • the opening maybe hollow rectangular shape such that the solder resist has a hollow rectangle portion and a solid rectangle portion arranged inside the hollow rectangle portion, and a part of an inner edge of the hollow rectangle portion of the solder resist may protrude inwardly at a position corresponding to the narrow interval group of the conductive pattern.
  • the opening may be hollow rectangular shape such that the solder resist has a hollow rectangle portion and a solid rectangle portion arranged inside the hollow rectangle portion, and a part of an outer edge of the solid rectangle portion of the solder resist may protrude outwardly at a position corresponding to the narrow interval group of the conductive-pattern.
  • the opening may be hollow rectangular shape such that the solder resist has a hollow rectangle portion and a solid rectangle portion arranged inside the hollow rectangle portion, a part of an inner edge of the hollow rectangle portion of the solder resist may protrude inwardly at a position corresponding to the narrow interval group of the conductive pattern, and a part of an outer edge of the solid rectangle portion of the solder resist may protrude outwardly at a position corresponding to the narrow interval group of the conductive pattern.
  • the opening may be rectangular shape, a part of an inner edge of opening of the solder resist may protrude inwardly at a position corresponding to the narrow interval group of the conductive pattern.
  • the conductive pattern may have a wide portion of which width is larger than the other portion of the conductive pattern.
  • the brazing metal powder is applied on the exposed surface of the conductive pattern, an amount of the fused brazing metal is proportional to an exposed square of the conductive pattern.
  • the amount of the brazing metal applied on the conductive pattern having short exposure length is smaller than the amount of the brazing metal applied on the conductive pattern having long exposure length.
  • the exposure lengths of the conductive patterns belonging to the narrow interval group are set shorter than that belonging to the wide interval group.
  • the amount of the brazing metal applied on the conductive patterns belonging to the narrow interval group is small and the shortcircuit between the terminals can be surely avoided.
  • FIG. 1 is a front view explaining an example of a wiring substrate according to the present invention
  • FIG. 2A is a partial sectional view of the wiring substrate of the present invention at a position corresponding to a narrow interval group of the conductive pattern;
  • FIG. 2B is a partial sectional view of the wiring substrate of the present invention at a position corresponding to a wide interval group of the conductive pattern;
  • FIG. 3 is a front view explaining another example of a wiring substrate according to the present invention.
  • FIG. 4 is a front view explaining still another example of a wiring substrate according to the present invention.
  • FIG. 5 is a front view explaining still another example of a wiring substrate according to the present invention.
  • FIG. 6 is a sectional view explaining a semiconductor device in which a semiconductor element is mounted on a mounting surface of a wiring substrate in the related art
  • FIG. 7 is a front view showing the wiring substrate shown in FIG. 6 ;
  • FIG. 8 is a front view showing another example of the wiring substrate in the related art.
  • FIG. 9 is a partial sectional view explaining a state that a semiconductor element is mounted on a mounting surface of the wiring substrate shown in FIG. 8 in the related art.
  • FIG. 1 An example of a mounting surface, on which a semiconductor element as an electronic component is mounted, formed on one surface side of a wiring substrate according to the present invention, is shown in FIG. 1 .
  • a wiring substrate 10 shown in FIG. 1 a wiring pattern is stacked in a multi-layered fashion, like the wiring substrate shown 100 in FIG. 6 .
  • One surface side of the wiring substrate 10 shown in FIG. 1 is formed as a mounting surface on which a semiconductor element 20 as an electronic component is mounted.
  • a plurality of conductive patterns 12 , 12 are formed in a frame-like space between an outside solder resist 14 shaped like a frame and an inside solder resist 16 formed inside the solder resist 14 on the mounting surface to expose therefrom. That is, an exposure surface of the conductive patterns 12 , 12 are exposed from on opening of the solder resist 14 , 16 .
  • a wide portion 12 b whose width is wider than other portions of the conductive pattern 12 is formed in the conductive patterns 12 , 12 respectively. Tip ends of the bumps protruded from the electrode terminals of the semiconductor element 20 come into contact with the wide portions 12 b respectively.
  • an interval between exposed surfaces of adjacent conductive patterns 12 ′, 12 ′ in the portion encircled with a dot-dash line is narrower than an interval between exposed surfaces of other adjacent conductive patterns 12 a , 12 a .
  • Such conductive patterns 12 ′, 12 ′ whose interval between exposed surfaces is narrow constitute a narrow interval group 12 A of the conductive pattern.
  • Exposed lengths of the conductive patterns 12 ′, 12 ′ constituting the narrow interval group 12 A of the conductive pattern shown in FIG. 1 are formed shorter than the exposed lengths of other conductive patterns 12 a , 12 a constituting the wide interval group of the conductive pattern.
  • the exposed length is defined in a direction in which the conductive pattern 12 extends from an edge of the opening of the solder resist 14 , 16 .
  • FIG. 2 shows a state that solder powders are applied to whole exposed surfaces of the conductive patterns 12 , 12 , which are exposed from the mounting surface of the wiring substrate 10 shown in FIG. 1 , and are fused, then the tip ends of the bumps provided on the electrode terminals of the semiconductor element as the electronic component are brought into contact with the conductive patterns 12 , 12 of which whole exposed surfaces are covered with the fused solder, and then the conductive patterns 12 and the bumps of the semiconductor element are joined together.
  • FIG. 2A shows a state that bumps 24 , 24 provided on electrode terminals 22 of the semiconductor element 20 are joined to the wide portions 12 b of the conductive patterns 12 ′, 12 ′ constituting the narrow interval group 12 A of the conductive pattern.
  • the exposed lengths of the conductive patterns 12 ′, 12 ′ constituting the narrow interval group 12 A of the conductive pattern are shorter than the exposed lengths of the conductive patterns 12 a , 12 a constituting the wide interval group of the conductive pattern. Therefore, an amount of fused solder that covers respective exposed surfaces of the conductive patterns 12 ′, 12 ′ is smaller than an amount of fused solder that covers respective exposed surfaces of the conductive patterns 12 a , 12 a.
  • an amount of fused solder that covers respective exposed surfaces of the conductive patterns 12 a, 12 a can be made larger than an amount of fused solder that covers respective exposed surfaces of the conductive patterns 12 ′, 12 ′. Therefore, when the tip ends of the bumps 24 of the semiconductor element 20 are brought into contact with the wide portions 12 b of the conductive patterns 12 a , 12 a of which whole exposed surfaces are covered with the fused solder respectively, an amount of solder that gathers around peripheral surfaces of the bumps 24 respectively due to surface tension can be increased, as shown in FIG. 2B . Thus, the bumps 24 and the conductive patterns 12 a can be joined strongly.
  • the spherical solders 26 , 26 formed around mutually adjacent bumps 24 , 24 are increased in size, nevertheless the interval between the bumps 24 , 24 is set sufficiently wide and the spherical solders 26 , 26 never come in touch with each other.
  • the exposed lengths of the conductive patterns 12 ′, 12 ′ constituting the narrow interval group 12 A of the conductive pattern are shortened by extending a portion of the outside solder resist 14 corresponding to the narrow interval group 12 A of the conductive pattern to the inner side of the solder resist 16 .
  • the exposed lengths of the conductive patterns 12 ′, 12 ′ may be shortened by extending a portion of the inside solder resist 16 corresponding to the narrow interval group 12 A of the conductive pattern to the outside solder resist 14 side.
  • the opening of the solder resist 14 , 16 is hollow rectangular shape such that the solder resist has a hollow rectangle portion 14 and a solid rectangle portion 16 arranged inside the hollow rectangle portion 14 , and a part of an inner edge of the hollow rectangle portion 14 of the solder resist protrudes inwardly at a position corresponding to the narrow interval group 12 A of the conductive pattern 12 .
  • the exposed lengths of the conductive patterns 12 ′ constituting the narrow interval group 12 A of the conductive pattern can be shortened.
  • FIG. 3 and FIG. 4 the same reference numbers as those shown in FIG. 1 are affixed to the same members as those shown in FIG. 1 , and their detailed explanation will be omitted herein.
  • the opening of the solder resist 14 , 16 is hollow rectangular shape such that the solder resist has a hollow rectangle portion 14 and a solid rectangle portion 16 arranged inside the hollow rectangle portion 14 , and a part of an outer edge of the solid rectangle portion 16 of the solder resist protrudes outwardly at a position corresponding to the narrow interval group 12 A of the conductive pattern 12 .
  • respective exposed surfaces of the conductive patterns 12 , 12 are formed along the outer peripheral edge of the wiring substrate 10 .
  • respective exposed surfaces of the conductive patterns 12 , 12 may be formed in a center portion of the wiring substrate 10 .
  • the wide portions 12 b with which the tip ends of the bumps 24 of the semiconductor element 20 are brought into contact are formed at the end portions of respective exposed surfaces of the conductive patterns 12 , 12 and respective rear end portions of the conductive patterns 12 , 12 are covered with the outside solder resist 14 .
  • an interval between exposed surfaces of the adjacent conductive patterns 12 ′, 12 ′ encircled with a dot-dash line is set narrower than the interval between exposed surfaces of other adjacent conductive patterns 12 ′, 12 ′.
  • Such conductive patterns 12 ′, 12 ′ in which the interval between adjacent exposed surfaces is set narrow constitute the narrow interval group 12 A of the conductive pattern.
  • other conductive patterns 12 a , 12 a in which the interval between adjacent exposed surfaces is set wider than the interval between adjacent exposed surfaces of the conductive patterns 12 ′, 12 ′ constitute the wide interval group of the conductive pattern.
  • the exposed lengths of the conductive patterns 12 ′, 12 ′ constituting the narrow interval group 12 A of the conductive pattern shown in FIG. 5 are formed shorter than the exposed lengths of other conductive patterns 12 a , 12 a constituting the wide interval group of the conductive pattern.
  • the exposed lengths of the conductive patterns 12 ′, 12 ′ are shortened by extending a portion of the outside solder resist 14 corresponding to the narrow interval group 12 A of the conductive pattern toward the inside direction.
  • the wiring substrate 10 shown in FIG. 1 to FIG. 5 can be formed by the publicly known manufacturing method, for example, the build-up method.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)
US12/330,946 2007-12-12 2008-12-09 Wiring substrate and electronic component mounting structure Active 2029-08-06 US7880314B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-321390 2007-12-12
JP2007321390A JP5107012B2 (ja) 2007-12-12 2007-12-12 配線基板及び電子部品の実装構造の製造方法

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US20090152716A1 US20090152716A1 (en) 2009-06-18
US7880314B2 true US7880314B2 (en) 2011-02-01

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US20110316162A1 (en) * 2010-06-24 2011-12-29 Ko Wonjun Integrated circuit packaging system with trenches and method of manufacture thereof

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US8076232B2 (en) * 2008-04-03 2011-12-13 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US8129841B2 (en) 2006-12-14 2012-03-06 Stats Chippac, Ltd. Solder joint flip chip interconnection
USRE47600E1 (en) 2003-11-10 2019-09-10 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
US8026128B2 (en) 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US9029196B2 (en) 2003-11-10 2015-05-12 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
US7659633B2 (en) 2004-11-10 2010-02-09 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8350384B2 (en) 2009-11-24 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming electrical interconnect with stress relief void
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USRE44500E1 (en) 2003-11-10 2013-09-17 Stats Chippac, Ltd. Semiconductor device and method of forming composite bump-on-lead interconnection
US20070105277A1 (en) 2004-11-10 2007-05-10 Stats Chippac Ltd. Solder joint flip chip interconnection
US8216930B2 (en) 2006-12-14 2012-07-10 Stats Chippac, Ltd. Solder joint flip chip interconnection having relief structure
US8841779B2 (en) 2005-03-25 2014-09-23 Stats Chippac, Ltd. Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate
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