US7477226B2 - Shift register - Google Patents

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US7477226B2
US7477226B2 US11/139,515 US13951505A US7477226B2 US 7477226 B2 US7477226 B2 US 7477226B2 US 13951505 A US13951505 A US 13951505A US 7477226 B2 US7477226 B2 US 7477226B2
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node
shift register
transistor
output
state
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US20050264514A1 (en
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Binn Kim
Soo Young Yoon
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LG Display Co Ltd
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LG Display Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate

Definitions

  • This invention relates to a driving circuit for a liquid crystal display, and more particularly to a shift register employing an amorphous silicon thin film transistor.
  • a liquid crystal display used as a display device for a television or a computer controls light transmittance of a liquid crystal using an electric field.
  • the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.
  • gate lines and data lines are arranged in such a manner to cross each other.
  • the crossing gate lines and data lines define a plurality of liquid crystal cells.
  • the liquid crystal display panel is provided with pixel electrodes and a common electrode for applying an electric field to each liquid crystal cell.
  • Each of the pixel electrodes is connected, via source and drain terminals of a thin film transistor as a switching device, to any one of the data lines.
  • a gate terminal of the thin film transistor is connected to an adjacent gate line.
  • the driving circuit includes a gate driver for driving the gate lines, and a data driver for driving the data lines.
  • the gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel.
  • the data driver applies a video signal to each data line in conjunction with the scanning signal applied to the gate lines.
  • the LCD controls light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with a video signal for each liquid crystal cell, thereby displaying a picture.
  • the gate driver generates a scanning signal for sequentially driving the gate lines using a shift register.
  • the data driver generates a sampling signal for sequentially sampling video signals provided externally by a certain unit using the shift register.
  • FIG. 1 is a block diagram illustrating a configuration of a related art two-phase shift register.
  • the shift register includes 1st to nth stages connected in cascade.
  • the 1st to nth stages are commonly supplied with first and second clock signals C 1 and C 2 along with high-level and low-level driving voltages (not shown), and are supplied with a start pulse Vst, which may be an output signal of the previous stage.
  • the 1st stage outputs a first output signal Out 1 in response to the start pulse Vst and the first and second clock signals C 1 and C 2 .
  • the 2nd to nth stages output 2nd to nth output signals, respectively, in response to the output signal of the previous stage and the first and second clock signals C 1 and C 2 .
  • the 1st to nth stages have an identical circuit configuration and sequentially shift a signal corresponding to the start pulse Vst.
  • the 1st to nth output signals Out 1 to Outn are supplied with a scanning signal for sequentially driving the gate lines of the liquid crystal display panel, or with a sampling signal for sequentially sampling a video signal within the data driver.
  • FIG. 2 illustrates a detailed circuit configuration of one stage shown in FIG. 1 .
  • the stage includes an output buffer part 20 having a pull-up NMOS transistor T 5 for outputting a first clock signal C 1 to an output line under control of a Q nodes and a pull-down NMOS transistor T 6 for outputting a low-level driving voltage VSS under control of a QB node, and a controller part 10 having first to fourth NMOS transistors T 1 to T 4 for controlling the Q node and the QB node.
  • the stage is supplied with high-level and low-level voltages VDD and VSS, a start pulse Vst, and a first and second clock signals C 1 and C 2 .
  • the first clock signal C 1 is a signal in which a high-state voltage and a low-state voltage, each having a certain pulse width, are alternately supplied as illustrated in FIG. 3
  • the second clock signal C 2 (not shown) is inverted relative to the first clock signal C 1 .
  • the start pulse Vst is either supplied externally or from the output signal of the previous stage.
  • a high-state voltage of start pulse Vst is supplied in synchronization with a high-state voltage of the second clock signal C 2 .
  • the first NMOS transistor T 1 is turned on by the high-state voltage of the second clock signal C 2 to thereby apply the high-state voltage of the start pulse Vst to the Q node, thereby pre-charging the Q node.
  • the high-stage voltage pre-charged into the Q node turns on the fifth NMOS transistor T 5 to thereby apply the low-state voltage of the first clock signal C 1 to the output line.
  • the second NMOS transistor T 2 is also turned on by the high-state voltage of the second clock signal C 2 to thereby apply the high-level driving voltage VDD to the QB node.
  • the high-level driving voltage VDD supplied to the QB node turns on the sixth NMOS transistor T 6 to thereby supply a low-level driving voltage VSS.
  • the output line of the stage outputs a low-state output signal OUT.
  • the first NMOS transistor T 1 is turned off by the low-state voltage of the second clock signal C 2 to thereby float the Q node into a high state.
  • the pull-up NMOS transistor T 5 maintains a turn-on state.
  • the floated Q node is boot-strapped by an affect of a parasitic capacitor CGD formed by an overlap between the gate electrode and the drain electrode of the pull-up NMOS transistor T 5 . Accordingly, the voltage at the Q node is raised further to turn on the pull-up NMOS transistor T 5 , thereby rapidly supplying the high-state voltage of the first clock signal C 1 to the output line.
  • the Q node floated into a high state turns on the fourth NMOS transistor T 4
  • the high-state first clock signal C 1 turns on the third NMOS transistor T 3 to supply the low-level driving voltage VSS to the QB node, thereby turning off the pull-down NMOS transistor T 6 .
  • the output line of the stage outputs a high-state output signal OUT.
  • the first NMOS transistor T 1 is turned on by the high-state voltage of the second clock signal C 2 to supply the low-state voltage of the start pulse Vst to the Q node, thereby turning off the pull-up NMOS transistor T 5 .
  • the second NMOS transistor T 2 is turned on by the high-state voltage of the second clock signal C 2 to supply the high-level driving voltage VDD to the QB node, thereby turning on the pull-down NMOS transistor T 6 to output the low-level driving voltage VSS to the output line.
  • the third NMOS transistor T 3 is turned off by the low-state voltage of the first clock signal C 1
  • the fourth NMOS transistor T 4 is turned off by the low-state voltage of the Q node, thereby keeping the high-level driving voltage VDD at the QB node.
  • the output line of the stage outputs a low-state output signal OUT.
  • the first NMOS transistor T 1 is turned off by the low-state voltage of the second clock signal C 2 to thereby float the Q node.
  • the second NMOS transistor T 2 is turned off by the low-state voltage of the second clock signal C 2
  • the fourth NMOS transistor T 4 is turned off by the Q node floated into a low state, so that the QB node is floated in a high state that is slightly lower than the high-level driving voltage VDD supplied in the previous period C even though the third NMOS transistor T 3 is turned on by a high-state voltage of the first clock signal C 1 .
  • the pull-down NMOS transistor T 6 maintains a turn-on state to thereby output the low-level driving voltage VSS to the output line.
  • the output line of the stage outputs a low-state output signal OUT.
  • the C and D periods are alternately repeated, so that the output signal OUT of the stage continuously maintains a low state.
  • the amorphous silicon thin film transistor may not function properly due to bias stress when a direct current voltage DV is continuously supplied to the thin film transistor's gate terminal.
  • a high-level driving voltage VDD is applied to the QB node, which is, the gate node of the pull-down NMOS transistor T 6 , providing a direct current voltage during a majority of periods (i.e., during the remaining period excluding the A and B periods when the Q node becomes a high state) as can be seen in FIG. 3 .
  • Persistent direct current voltage on the gate of pull-down NMOS transistor T 6 causes a gate bias stress on the transistor, which changes the transistor's threshold voltage Vzh.
  • a minimum voltage applied to the QB node for the purpose of keeping the Q node at the turn-off voltage is referred to as a clamping voltage, which needs to be more than a certain voltage level.
  • a change of threshold voltage Vth in pull-down NMOS transistor T 6 due to the gate bias stress reduces the clamping voltage applied to the QB node (i.e., an applied voltage—Vth). Therefore, a problem arises in that an erroneous operation of the shift register, such as a multiple output generation, occurs below a certain voltage on the QB node.
  • the present invention is directed to a shift register that substantially obviates one or more of the aforementioned problems due to limitations and disadvantages of the related art.
  • the present invention achieves this by providing a shift register capable of preventing a gate bias stress on a pull-down transistor.
  • An advantage of the present invention is that it enables a shift register to be fabricated with amorphous silicon.
  • Another advantage of the present invention is that it enables a shoft register to be integrated into an LCD panel.
  • a shift register having a plurality of stages that comprises first, second, and third driving voltage supply lines; at least two clock signal supply lines; an output buffer having an output pull-up transistor and a first and second output pull-down transistors; a first controller having an input connected to a start signal supply line and an output connected to a first node; and a second controller having an input connected to the first and second voltage supply lines and an output connected to the gates of the first and second output pull-down transistors.
  • a shift register having a plurality of stages that comprises an output buffer having first transistor and an even and odd transistor, the even and odd transistors having the same polarity a first controller for controlling a state of the output buffer; and a second controller for switching between the even and odd transistor.
  • FIG. 1 is a schematic block diagram illustrating a configuration of a related art two-phase shift register
  • FIG. 2 is a detailed circuit diagram of one stage illustrated in FIG. 1 ;
  • FIG. 3 is a driving waveform diagram of the stage illustrated in FIG. 2 ;
  • FIG. 4 is a detailed circuit diagram of a stage of a shift register according to an embodiment of the present invention.
  • FIG. 5 is an exemplary driving waveform diagram of the stage illustrated in FIG. 4 .
  • FIG. 4 is a circuit diagram illustrating a configuration of any one of a plurality of stages connected in cascade in a shift register according to an embodiment of the present invention.
  • FIG. 5 is a driving waveform diagram of a stage illustrated in FIG. 4 .
  • a stage of the shift register includes an output buffer having a pull-up transistor NT 7 for outputting a first clock signal CLK 1 to an output line under control of a Q node, and first and second pull-down transistors NT 8 A and NT 8 B for outputting a third driving voltage VSS to the output line under control of QB 1 and QB 2 nodes; a first controller having first to third transistors NT 1 to NT 3 for pre-charging and discharging the Q node; and a second controller having transistors NT 4 A to NT 6 B for making an alternate driving current while dividing the QB 1 and QB 2 nodes into odd and even frames.
  • Transistors NT 1 to NT 8 B may employ NMOS transistors or PMOS transistors. For purposes of illustration, a case of employing NMOS transistors only will be described.
  • the first transistor NT 1 of the first controller may be connected, in a diode configuration, to an input line of start pulse Vst to pre-charge a high-state voltage of the start pulse Vst into the Q node.
  • the transistors NT 2 A and NT 2 B discharge the Q node under control of the respective QB 1 and QB 2 nodes, and the third transistor NT 3 is controlled by an output voltage OUTi+1 of the next stage to discharge the Q node.
  • the second controller includes transistors NT 4 A and NT 4 B for charging first and second high-level voltages VDD 1 and VDD 2 into the QB 1 and QB 2 nodes; respectively, transistors NT 5 A to NT 5 D for discharging the QB 1 and QB 2 nodes under control of the start pulse Vst and the Q node; a transistor NT 6 A for discharging the QB 2 node under control of the QB 1 node, and a transistor NT 6 B for discharging the QB 1 node under control of the QB 2 node.
  • a first pull-down transistor NT 8 A is driven under control of the QB 1 node at an odd frame at which the first driving voltage VDD 1 is a high-level state
  • a second pull-down transistor NT 8 B is driven under control of the QB 2 node at an even frame at which the second driving voltage VDD 2 is a high-level state.
  • the first and second pull-down transistors NT 8 A and NT 8 B are alternately driven at the odd and even frames in this manner, so that it becomes possible to minimize a stress caused by a direct current bias.
  • the particular stage illustrated in FIG. 4 is supplied with the first clock signal CLK 1 of the phase-inverted first and second clock signals CLK 1 and CLK 2 , and the next stage is supplied with the second clock signal CLK 2 .
  • Each stage is alternately supplied with the first and second clock signals CLK 1 and CLK 2 .
  • each stage is supplied with the first and second driving voltages VDD 1 and VDD 2 having the polarities inverted in opposition to each other at the odd and even frames, and each stage is supplied with the third driving voltage VSS.
  • the first driving voltage VDD 1 becomes a high state while the second driving voltage VDD 2 becomes a low state.
  • the transistor NT 4 A connected, in a diode configuration, to the supply line for the first driving voltage VDD 1 maintains an on state
  • the transistor NT 4 B connected, in a diode type, to the supply line for the second driving voltage VDD 2 maintains an off state.
  • the QB 1 node makes an operation opposite to the QB 2 node at the odd frame, thereby allowing the first pull-down transistor NT 8 A to operate opposite to the pull-up transistor NT 7 .
  • the QB 2 node maintains a low state, thereby allowing the second pull-down transistor NT 8 B to maintain an off state.
  • the low-state voltage of the first clock signal CLK 1 , the high-state voltage of the second clock signal CLK 2 and the high-state voltage of the start pulse Vst are supplied.
  • the first transistor NT 1 is turned on by the high-state voltage of the start pulse Vst to pre-charge the Q node into a high-state voltage.
  • the pull-up transistor NT 7 is turned on by the high-state voltage of the Q node, thereby applying the low-state voltage of the first clock signal CLK 1 as an output signal OUT 1 .
  • the transistor NT 4 A is turned on by the high-state first driving voltage VDD 1 and the transistors NT 5 A and NT 5 B are respectively turned on by high-state voltages of the start pulse Vst and the Q node, so that the QB 1 node becomes a low state by the driving voltage VSS. Further, the transistor NT 4 B is turned off by a low-state second driving voltage VDD, and the transistors NT 5 C and NT 5 D are respectively turned on by the high-state voltages of the start pulse Vst and the Q node, so that the QB 2 node becomes a low state by the third driving voltage VSS. Accordingly, the first and second pull-down transistors NT 8 A and NT 8 B are turned off.
  • the high-state voltage of the first clock signal CLK 1 , the low-state voltage of the second clock signal CLK 2 and the low-state voltage of the start pulse Vst are supplied.
  • the first transistor NT 1 is turned off by the low-state voltage of the start pulse Vst
  • the third transistor NT 3 is turned off by the low-state voltage of the next stage output signal OUTi+1, thereby floating the Q node into a high state.
  • the Q node, which is floated into a high state is bootstrapped in response to the high-state voltage of the first clock signal CLK 1 by a coupling action of the parasitic capacitor CGD defined by an overlap between the gate electrode and the source electrode of the pull-up transistor NT 7 .
  • a voltage at the Q node is further raised to more certainly turn on the pull-up transistor NT 7 , thereby applying the high-state voltage of the first clock signal CLK 1 as an output signal OUTi.
  • an additional capacitor (not shown) may be provided in parallel to the parasitic capacitor CGD.
  • the transistor NT 4 A is turned on by the high-state first driving voltage VDD 1 while the transistor NT 5 B is turned on by the high-stage voltage at the bootstrapped Q node, so that the QB 1 node becomes a low state by the third driving voltage VSS.
  • the transistor NT 5 D is turned on by the high-state voltage at the Q node, so that the QB 2 node maintains a low state. Accordingly, the first and second pull-down transistors NT 8 A and NT 8 B are turned off.
  • period C the low-state voltage of the first clock signal CLK 1 , the high-state voltage of the second clock signal CLK 2 and the low-state voltage of the start pulse Vst are supplied.
  • the first transistor NT 1 is turned off by the low-state voltage of the start pulse Vst, and the third transistor NT 3 is turned on by the high-state voltage of the next stage output signal OUTi+1 to apply the third driving voltage VSS to the Q node, thereby turning off the pull-up transistor NT 7 .
  • All the transistors NT 5 A to NT 5 D are turned off by the low-state voltages of the start pulse Vst and the Q node; and the high-state first driving voltage VDD 1 is charged, via the transistor NT 4 A remaining at a turn-on state, into the QB 1 node.
  • the first pull-down transistor NT 8 A is turned on to thereby apply the third driving voltage VSS as an output signal OUTi.
  • the transistor NT 6 A is turned on to maintain the QB 2 node at a low state, and the transistor NT 2 A is turned on to maintain the Q node at a low state.
  • the high-state voltage of the first clock signal CLK 1 , the low-state voltage of the second clock signal CLK 2 , and the low-state voltage of the start pulse Vst are supplied.
  • the first and third transistors NT 1 and NT 3 are respectively turned off by the low-state voltages of the start pulse Vst and the next stage output signal OUTi+1, so that the Q node maintains the previous low state.
  • All the transistors NT 5 A-NT 5 D are turned off by the low-state voltages of the start pulse Vst and the Q node, and the QB 1 node maintains a high state by the transistor NT 4 A, which maintains an on state.
  • the first pull-down transistor NT 8 A is turned on to apply the third driving voltage VSS as an output signal OUTi. Further, by the high-state voltage at the QB 1 node, the transistor NT 6 A is turned on to keep the QB 2 node at a low state while the transistor NT 2 A is turned on to fix the Q node at a low state.
  • the transistor NT 4 A connected, in a diode configuration, to the supply line for the first driving voltage VDD 1 maintains an off state
  • the transistor NT 4 B connected, in a diode configuration, to the supply line for the second driving voltage VDD 2 maintains an on state.
  • the QB 2 node operates opposite to the Q node at the even frame, thereby allowing the second pull-down transistor NT 8 B to operate opposite to the pull-up transistor NT 7 .
  • the QB 1 node maintains a low state, thereby allowing the first pull-down transistor NT 8 A to maintain a turn-off state.
  • the low-state voltage of the first clock signal CLK 1 , the high-state voltage of the second clock signal CLK 2 , and the high-state voltage of the start pulse Vst are supplied.
  • the first transistor NT 1 is turned on by the high-state voltage of the start pulse Vst to thereby pre-charge the high-state voltage of the start pulse Vst into the Q node.
  • the pull-up transistor NT 7 is turned on by the high-state voltage of the Q node, thereby applying the low-state voltage of the first clock signal CLK 1 as an output signal OUTi.
  • the transistor NT 4 B is turned on by the high-state second driving voltage VDD 2 while the transistors NT 5 C and NT 5 D are respectively turned on by high-state voltages of the start pulse Vst and the Q node, so that the QB 2 node is driven to a low state by the third driving voltage VSS.
  • the transistor NT 4 A is turned off by the low-state first driving voltage VDD 1
  • the transistors NT 5 A and NT 5 B are respectively turned on by the high-state voltages of the start pulse Vst and the Q node, so that the QB 1 node is driven to a low state by the third driving voltage VSS. Accordingly, the first and second pull-down transistors NT 8 A and NT 8 B are turned off.
  • the high-state voltage of the first clock signal CLK 1 , the low-state voltage of the second clock signal CLK 2 , and the low-state voltage of the start pulse Vst are supplied.
  • the first transistor NT 1 is turned off by the low-state voltage of the start pulse Vst
  • the third transistor NT 3 is turned off by the low-state voltage of the next stage output signal OUTi+1, thereby floating the Q node into a high state.
  • the Q node, which is floated into a high state is bootstrapped in response to the high-state voltage of the first clock signal CLK 1 to more certainly turn on the pull-up transistor NT 7 , thereby applying the high-state voltage of the first clock signal CLK 1 as an output signal OUTi.
  • the transistor NT 4 B is turned on by the high-state second driving voltage VDD 2 while the transistor NT 5 D is turned on by the high-state voltage at the bootstrapped Q node, so that the QB 2 node becomes a low state by the third driving voltage VSS. Further, the transistor NT 5 B is turned on by the high-state voltage at the Q node, so that the QB 1 node maintains a low state. Accordingly, the first and second pull-down transistors NT 8 A and NT 8 B are turned off.
  • the low-state voltage of the first clock signal CLK 1 , the high-state voltage of the second clock signal CLK 2 , and the low-state voltage of the start pulse Vst are supplied.
  • the first transistor NT 1 is turned off by the low-state voltage of the start pulse Vst, and the third transistor NT 3 is turned on by the high-state voltage of the next stage output signal OUTi+1 to apply the third driving voltage VSS to the Q node, thereby turning off the pull-up transistor NT 7 .
  • All the transistors NT 5 A to NT 5 D are turned off by the low-state voltages of the start pulse Vst and the Q node, and the high-state second driving voltage VDD 2 is charged, via the transistor NT 4 B remaining at a turn-on state, into the QB 2 node.
  • the second pull-down transistor NT 8 B is turned on to thereby apply the third driving voltage VSS as an output signal OUTi.
  • the transistor NT 6 B is turned on to keep the QB 1 node at a low state, and the transistor NT 2 B is turned on to more certainly maintain the Q node at a low state.
  • the high-state voltage of the first clock signal CLK 1 , the low-state voltage of the second clock signal CLK 2 , and the low-state voltage of the start pulse Vst are supplied.
  • the first and third transistors NT 1 and NT 3 are respectively turned off by the low-state voltages of the start pulse Vst and the next stage output signal OUTi+1, so that the Q node maintains the a previous low state.
  • All the transistors NT 5 A-NT 5 D are turned off by the low-state voltages of the start pulse Vst and the Q node, and the QB 2 node maintains a high state by the transistor NT 4 B maintaining a turn-on state.
  • the second pull-down transistor NT 8 B is turned on to apply the third driving voltage VSS as an output signal OUTi. Further, by the high-state voltage at the QB 2 node, the transistor NT 6 B is turned on to keep the QB 1 node at a low state while the transistor NT 2 B is turned on to fix the Q node at a low state.
  • the shift register according to the embodiment of the present invention can alternately drive the dual pull-down transistors NT 8 A and NT 8 B at the odd and even frames, thereby minimizing a gate bias stress.
  • the transistors NT 5 A and NT 5 B for discharging the QB 1 node and the transistors NT 4 A and NT 4 B for charging the QB 1 and QB 2 nodes can alternately be driven at the odd and even frames, thereby minimizing a gate bias stress.
  • the transistors NT 4 A and NT 4 B are connected, in a diode type, to the respective supply line for the first and second driving voltages VDD 1 and VDD 2 .
  • the transistors NT 4 A and NT 4 B are connected in a diode configuration such that a high-state voltage is loaded on all the gate/source/drain electrodes at an operating frame while a low-state voltage is loaded on all the gate/source/drain electrodes at an idle frame, so that deterioration may be mitigated.
  • a structure capable of minimizing a bias stress is applied to improve a life of the panel.
  • the shift register according to the present invention can implement all of the transistors NT 2 A and NT 2 B for discharging the Q node and the transistors NT 4 A to NT 6 B for charging and discharging the QB 1 node and the QB 2 node, along with the pull-down transistors NT 8 A and NT 8 B, to use alternating transistors to drive the odd and even frames, thereby minimizing a gate bias stress.
  • the shift register connects the transistors NT 4 A and NT 4 B, in a diode configuration, to the respective supply line for the first and second driving voltages VDD 1 and VDD 2 such that a high-state voltage is loaded on all the gate/source/drain electrodes at an operating frame while a low-state voltage is loaded on all the gate/source/drain electrodes at an idle frame, so may be mitigated. Accordingly, a bias stress can be minimized to improve a life of the panel.
  • the shift register according to the present invention may prevent a circuit malfunction caused by a gate bias stress when it employs an amorphous silicon thin film transistor.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110080385A1 (en) * 2009-10-07 2011-04-07 Nec Lcd Technologies, Ltd. Shift register circuit, scanning line driving circuit, and display device
US8743044B2 (en) 2006-09-29 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Display device
US9311876B2 (en) 2008-06-17 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US9368519B2 (en) 2009-09-16 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US9508301B2 (en) 2011-05-13 2016-11-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US20170004790A1 (en) * 2015-07-02 2017-01-05 Apple Inc. Display Gate Driver Circuits with Dual Pulldown Transistors
US11967598B2 (en) 2006-09-29 2024-04-23 Semiconductor Energy Laboratory Co., Ltd. Display device

Families Citing this family (59)

* Cited by examiner, † Cited by third party
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US20030052848A1 (en) * 2001-09-20 2003-03-20 Matsushita Electric Industrial Co., Ltd Signal transmission circuit, solid-state imaging device, camera and liquid crystal display
KR101023726B1 (ko) * 2004-03-31 2011-03-25 엘지디스플레이 주식회사 쉬프트 레지스터
KR101110133B1 (ko) * 2004-12-28 2012-02-20 엘지디스플레이 주식회사 액정표시장치 게이트 구동용 쉬프트레지스터
TWI278183B (en) * 2005-07-01 2007-04-01 Au Optronics Corp Shift register and level shifter thereof
JP4912000B2 (ja) * 2006-03-15 2012-04-04 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
US7283603B1 (en) * 2006-04-07 2007-10-16 Au Optronics Corporation Shift register with four phase clocks
KR101232153B1 (ko) * 2006-05-11 2013-02-13 엘지디스플레이 주식회사 게이트 구동회로
US8330492B2 (en) 2006-06-02 2012-12-11 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device and electronic device
KR100801352B1 (ko) * 2006-06-12 2008-02-11 한양대학교 산학협력단 쉬프트 레지스터 및 이의 구동방법
TWI366814B (en) * 2006-07-12 2012-06-21 Wintek Corp Shift register
EP1895545B1 (en) 2006-08-31 2014-04-23 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device
JP5468196B2 (ja) * 2006-09-29 2014-04-09 株式会社半導体エネルギー研究所 半導体装置、表示装置及び液晶表示装置
TWI585730B (zh) * 2006-09-29 2017-06-01 半導體能源研究所股份有限公司 顯示裝置和電子裝置
JP5116277B2 (ja) 2006-09-29 2013-01-09 株式会社半導体エネルギー研究所 半導体装置、表示装置、液晶表示装置、表示モジュール及び電子機器
TWI332645B (en) * 2006-10-17 2010-11-01 Au Optronics Corp Driving circuit of liquid crystal display device
KR101237199B1 (ko) * 2006-11-16 2013-02-25 엘지디스플레이 주식회사 쉬프트 레지스터와 이를 이용한 액정표시장치
KR101329791B1 (ko) * 2007-07-16 2013-11-15 삼성디스플레이 주식회사 액정 표시 장치
CN101465165B (zh) * 2007-12-20 2011-05-25 胜华科技股份有限公司 移位寄存器
KR101286539B1 (ko) * 2008-04-15 2013-07-17 엘지디스플레이 주식회사 쉬프트 레지스터
TWI386904B (zh) * 2008-05-12 2013-02-21 Chimei Innolux Corp 平面顯示器
JP5442234B2 (ja) 2008-10-24 2014-03-12 株式会社半導体エネルギー研究所 半導体装置及び表示装置
CN101727800B (zh) * 2008-10-27 2012-05-30 瀚宇彩晶股份有限公司 半导体栅极驱动电路及其驱动方法
US8872751B2 (en) * 2009-03-26 2014-10-28 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device having interconnected transistors and electronic device including the same
CN102081969B (zh) * 2009-12-01 2014-06-25 群康科技(深圳)有限公司 移位寄存电路及双向传输栅极驱动电路
KR101828961B1 (ko) * 2010-03-02 2018-02-13 가부시키가이샤 한도오따이 에네루기 켄큐쇼 펄스 신호 출력 회로 및 시프트 레지스터
JP5165777B2 (ja) * 2011-04-07 2013-03-21 三菱電機株式会社 シフトレジスタ回路およびそれを備える画像表示装置
CN102654982B (zh) * 2011-05-16 2013-12-04 京东方科技集团股份有限公司 移位寄存器单元电路、移位寄存器、阵列基板及液晶显示器
JP6116149B2 (ja) 2011-08-24 2017-04-19 株式会社半導体エネルギー研究所 半導体装置
CN102368380A (zh) * 2011-09-14 2012-03-07 深圳市华星光电技术有限公司 液晶显示面板与栅极驱动电路
KR101382108B1 (ko) 2012-06-15 2014-04-08 엘지디스플레이 주식회사 액정표시장치 및 그 구동방법
CN102867543B (zh) * 2012-09-29 2015-09-16 合肥京东方光电科技有限公司 移位寄存器、栅极驱动器及显示装置
CN103294252B (zh) 2012-10-11 2016-03-23 上海天马微电子有限公司 触摸屏显示装置
CN102968956B (zh) * 2012-11-30 2014-12-31 华南理工大学 有源有机电致发光显示器的扫描驱动器及其驱动方法
CN103226979B (zh) * 2013-02-18 2016-03-09 合肥京东方光电科技有限公司 一种双向移位寄存器单元、双向移位寄存器及显示装置
CN103137061B (zh) * 2013-02-18 2015-12-09 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路及显示装置
CN103151010B (zh) * 2013-02-27 2014-12-10 京东方科技集团股份有限公司 一种移位寄存器和显示装置
JP2014167841A (ja) * 2013-02-28 2014-09-11 Kyocera Corp シフトレジスタ回路および画像表示装置
KR101992158B1 (ko) * 2013-04-30 2019-09-30 엘지디스플레이 주식회사 게이트 쉬프트 레지스터와 이를 이용한 표시장치
CN103927972B (zh) * 2013-12-05 2016-03-02 华南理工大学 栅极驱动单元及栅极扫描驱动器及其驱动方法
TWI517117B (zh) * 2014-01-20 2016-01-11 友達光電股份有限公司 移位暫存器及其控制方法
TWI527044B (zh) * 2014-05-05 2016-03-21 友達光電股份有限公司 移位暫存器
CN103996370B (zh) * 2014-05-30 2017-01-25 京东方科技集团股份有限公司 移位寄存器单元、栅极驱动电路、显示装置及驱动方法
CN104134430B (zh) * 2014-07-04 2016-08-17 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路及显示装置
JP6601667B2 (ja) * 2014-12-03 2019-11-06 Ｔｉａｎｍａ Ｊａｐａｎ株式会社 シフトレジスタ回路及びゲートドライバ並びに表示装置
CN104778928B (zh) 2015-03-26 2017-04-05 京东方科技集团股份有限公司 一种移位寄存器、栅极驱动电路、显示面板及显示装置
KR102328835B1 (ko) * 2015-07-31 2021-11-19 엘지디스플레이 주식회사 게이트 구동 회로와 이를 이용한 표시장치
KR20180024854A (ko) 2016-08-31 2018-03-08 엘지디스플레이 주식회사 유기전계발광표시장치 및 이의 구동방법
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KR102487712B1 (ko) * 2017-12-29 2023-01-11 엘지디스플레이 주식회사 표시 장치
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CN108538268B (zh) * 2018-04-20 2020-08-04 南京中电熊猫液晶显示科技有限公司 一种双向扫描栅极驱动电路
JP6620260B1 (ja) * 2019-07-11 2019-12-11 株式会社半導体エネルギー研究所 半導体装置及び電子機器
CN110610676B (zh) * 2019-09-30 2021-10-26 合肥京东方卓印科技有限公司 显示装置、栅极驱动电路、移位寄存电路及其驱动方法
JP7078653B2 (ja) * 2020-01-21 2022-05-31 株式会社半導体エネルギー研究所 表示装置
WO2022109920A1 (zh) * 2020-11-26 2022-06-02 京东方科技集团股份有限公司 驱动方法、栅极驱动单元和显示触控装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093655A (en) * 1985-10-16 1992-03-03 Sanyo Electric Co., Ltd. Liquid-crystal display apparatus
US5859630A (en) * 1996-12-09 1999-01-12 Thomson Multimedia S.A. Bi-directional shift register
US7321355B2 (en) * 2003-03-07 2008-01-22 Hannstar Display Corporation Liquid crystal display

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100830903B1 (ko) * 2001-12-27 2008-05-22 삼성전자주식회사 쉬프트 레지스터 및 이를 갖는 액정표시장치
KR100804038B1 (ko) * 2002-04-04 2008-02-18 삼성전자주식회사 쉬프트 레지스터 및 이를 갖는 액정표시장치

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093655A (en) * 1985-10-16 1992-03-03 Sanyo Electric Co., Ltd. Liquid-crystal display apparatus
US5859630A (en) * 1996-12-09 1999-01-12 Thomson Multimedia S.A. Bi-directional shift register
US7321355B2 (en) * 2003-03-07 2008-01-22 Hannstar Display Corporation Liquid crystal display

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11967598B2 (en) 2006-09-29 2024-04-23 Semiconductor Energy Laboratory Co., Ltd. Display device
US9536903B2 (en) 2006-09-29 2017-01-03 Semiconductor Energy Laboratory Co., Ltd. Display device
US8743044B2 (en) 2006-09-29 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Display device
US8902145B2 (en) 2006-09-29 2014-12-02 Semiconductor Energy Laboratory Co., Ltd. Display device
US10297618B2 (en) 2006-09-29 2019-05-21 Semiconductor Energy Laboratory Co., Ltd. Display device
US9842861B2 (en) 2006-09-29 2017-12-12 Semiconductor Energy Laboratory Co., Ltd. Display device
US10930683B2 (en) 2006-09-29 2021-02-23 Semiconductor Energy Laboratory Co., Ltd. Display device
US9311876B2 (en) 2008-06-17 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US11455968B2 (en) 2008-06-17 2022-09-27 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US11837189B2 (en) 2008-06-17 2023-12-05 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US10121435B2 (en) 2008-06-17 2018-11-06 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US10971103B2 (en) 2008-06-17 2021-04-06 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US10665195B2 (en) 2008-06-17 2020-05-26 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US11620962B2 (en) 2008-06-17 2023-04-04 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, display device, and electronic device
US9368519B2 (en) 2009-09-16 2016-06-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US11545105B2 (en) 2009-09-16 2023-01-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US10181304B2 (en) 2009-09-16 2019-01-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US9934747B2 (en) 2009-09-16 2018-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US10446103B2 (en) 2009-09-16 2019-10-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US9830878B2 (en) 2009-09-16 2017-11-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US10902814B2 (en) 2009-09-16 2021-01-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic appliance
US20110080385A1 (en) * 2009-10-07 2011-04-07 Nec Lcd Technologies, Ltd. Shift register circuit, scanning line driving circuit, and display device
US8681085B2 (en) 2009-10-07 2014-03-25 Nlt Technologies, Ltd. Shift register circuit, scanning line driving circuit, and display device
TWI562156B (en) * 2011-05-13 2016-12-11 Semiconductor Energy Lab Co Ltd Semiconductor device
US11295649B2 (en) 2011-05-13 2022-04-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10559606B2 (en) 2011-05-13 2020-02-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device employing N-channel type transistors
US10062717B2 (en) 2011-05-13 2018-08-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11682332B2 (en) 2011-05-13 2023-06-20 Semionductor Energy Laboratory Co., Ltd. Semiconductor device
US9508301B2 (en) 2011-05-13 2016-11-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10037738B2 (en) * 2015-07-02 2018-07-31 Apple Inc. Display gate driver circuits with dual pulldown transistors
US20170004790A1 (en) * 2015-07-02 2017-01-05 Apple Inc. Display Gate Driver Circuits with Dual Pulldown Transistors

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KR20050113967A (ko) 2005-12-05

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